'K4-208 Forward Middle Module'
Features
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12 x ABCD3T, VDC, DORIC4A
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Module has been tested using the Redundant Clock/Command inputs with Spydata
outputs and Pseudo-Opto readout.
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Module mounted on 'new' Liverpool cooling frame within a Faraday cage.
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There is 1 'screened fan-in' on this module. This is located at chip
locations: M8, S9, S10.
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A Foil Screen has also been added to this module underneath the wirebonds
linking the fan-in to chip, chip locations M0, S1, S2.
Module Configuration
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All data taken with Edge Detect Off and data compression set to mode 1
(X1X).
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FEBias = 220uA FEShape = 30uA.
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VDD = 4.0V VCC =
3.5V
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Data taken with module trimmed at 2.0fC (old data file). Note that not
using the trim data file has no affect upon the performance.
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Module Temperature 38C (typically)
Tests and Results
The addition of the screened foil has increased the noise considerably
and introduced instability.
Using either the Redundant Clk/Com inputs or alternatively the VDC/DORIC
route has no affect upon the performance.
All data is taken with Qcal = 3.0fC
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Single chip performance Scurves, M0
only, all other remaining chips have their FEBias and SHAPEBias set
to 0.
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Single chip performance Scurves, M8
only, all other remaining chips have their FEBias and SHAPEBias set
to 0
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6 chip performance Scurves, M0, S1, S2, S3, S4, E5, Link0.
All other chips bias set to 0.
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6 chip performance Scurves, M8, S9, S10, S11, S12, E13, Link1.
All other chips bias set to 0.
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Full module, Noise
Profile and Scurves for Link0
and link1.
Comments
The screened foil is approx 1.5mm wide and runs continuous underneath
the bonds of the 3 chips. The foil is connected to Agnd via conductive
glue......I measure 6.5ohms between the foil and Agnd. This could be a
source of the problems that I am encountering.
02/08/01 New Results 
Since the addition of the screened foil has unfortunately had the affect
to increase input noise and instability, the following has been done to
try to restore module performance to what one would expect ie ENC ~ 1500e
and stable(?) operation.
25/07/01 Additional 10uF Tantalum Capacitors
have been added in parallel to the VCC/VDD 1uF Capacitors (C36 and C39)
adjacent to the module power connector.
The addition of the 10uF capacitors has brought the noise under control,
ENC <1600e, but profile is not flat. The noise occupancy is still a
problem with uneven distribution and excess occupancy.
Solder 50um wire from Agnd on VCC decoupling capacitors, chip locations
M0, E5, M8 and E13, to the substrate.
Comparison plots, noise occupancy
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For comments etc. please contact Ashley
Greenall
Last modified: 02/08/2001