[University of Liverpool Crest]
Department of Physics, High Energy Particle Physics Group

Proposal by Liverpool University to join the CDF Collaboration

The proposal is available as ( PS file of 46K ), which should be used to produce a printed copy or can be read in text format.

We have performed some studies on the likely hit and track occupancies which will be found in Layer00 for various different detector configurations. These studies are ongoing and preliminary and are only reproduced here so as to provide rapid communication with design teams at Fermilab. Feel free to comment and criticise!

The first study was for an 8-fold detector with 50 micron pitch. It was not realistic since it assumed an infinite z acceptance. Nonetheless, the report is useful for defining the quantities used to evaluate the performance and for several informative plots.

The second study assumed the detector was 80cm long in z, with eight sensors of 10cm. The third study summarised the first two, and considered twelve other possible designs for Layer00.

We have also started looking at engineering designs for the mechanical construction of Layer00. Relatively few solutions present themselves, assuming that we want to:
  • Place the detector at a radius of about 1.6 cm;
  • restrict the number of readouts to about 100 chips, each with 128 channels;
  • have an integral number of readout chips per sensor;
  • provide full 2 pi coverage with some overlap;
  • cut the silicon from a small number of 4 or 6 inch wafers.

    One is for an 8-fold detector with 50 micron pitch and 8 sensors of 10cm each in z. This would require two readout chips per sensor giving a total of 128. The problem with this design is seen in the occupancy studies where 38% of tracks deposit their charge over 4 or more strips.

    A second design is for a 12-fold detector with 75 micron pitch and 10 sensors in z (6 of 8cm and 4 or 6.5cm). Two 6.5cm long would be daisychained and readout together. This would require one readout chip per sensor giving a total of 96 readout chips. This design also makes optimum use of 4 inch silicon wafers from which three 8cm sensors and two 6.5cm sensors could be cut.

    At the moment, we are working on a 14- or 16-fold design with 50 micron pitch and one readout chip per sensor. ...Watch this space for breaking news...