NET "Clock"	 LOC = "C9"  | IOSTANDARD = LVCMOS33;
NET "OSC_40"	 LOC = "E10" | IOSTANDARD = LVCMOS33;
#
NET "ETH_COL"	 LOC = "U6"  | IOSTANDARD = LVCMOS33;
NET "ETH_CRS"	 LOC = "U13" | IOSTANDARD = LVCMOS33;
#
NET "ETH_RX_DV"	 LOC = "V2"  | IOSTANDARD = LVCMOS33;
NET "ETH_RX_CLK" LOC = "V3"  | IOSTANDARD = LVCMOS33;
NET "ETH_RX_ERR" LOC = "U14" | IOSTANDARD = LVCMOS33;
NET "ETH_RXD[3]" LOC = "V14" | IOSTANDARD = LVCMOS33;
NET "ETH_RXD[2]" LOC = "U11" | IOSTANDARD = LVCMOS33;
NET "ETH_RXD[1]" LOC = "T11" | IOSTANDARD = LVCMOS33;
NET "ETH_RXD[0]" LOC = "V8"  | IOSTANDARD = LVCMOS33;
#
NET "ETH_TX_EN"	 LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "ETH_TX_CLK" LOC = "T7"  | IOSTANDARD = LVCMOS33;
NET "ETH_TX_ERR" LOC = "R6"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "ETH_TXD[3]" LOC = "T5"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "ETH_TXD[2]" LOC = "R5"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "ETH_TXD[1]" LOC = "T15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "ETH_TXD[0]" LOC = "R11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
#
NET "ETH_MDC"	 LOC = "P9"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "ETH_MDIO"	 LOC = "U5"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
#
NET "USB_nTXE"	 LOC = "E8"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 24;
NET "USB_nRXF"	 LOC = "B4"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 24;
NET "USB_nRD"	 LOC = "C7"  | IOSTANDARD = LVTTL | PULLUP;
NET "USB_WR"	 LOC = "F8"  | IOSTANDARD = LVTTL | PULLUP;
NET "USB_DAT[7]" LOC = "B6"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 24;
NET "USB_DAT[6]" LOC = "F7"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 24;
NET "USB_DAT[5]" LOC = "E7"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 24;
NET "USB_DAT[4]" LOC = "D5"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 24;
NET "USB_DAT[3]" LOC = "D7"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 24;
NET "USB_DAT[2]" LOC = "C5"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 24;
NET "USB_DAT[1]" LOC = "A6"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 24;
NET "USB_DAT[0]" LOC = "A4"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 24;
#
NET "PMT[1]"	 LOC = "C12" | IOSTANDARD = LVCMOS33;
NET "PMT[0]"	 LOC = "D12" | IOSTANDARD = LVCMOS33;
#
NET "SIT[3]"	 LOC = "A15" | IOSTANDARD = LVCMOS33;
NET "SIT[2]"	 LOC = "B15" | IOSTANDARD = LVCMOS33;
NET "SIT[1]"	 LOC = "C3"  | IOSTANDARD = LVCMOS33;
NET "SIT[0]"	 LOC = "C15" | IOSTANDARD = LVCMOS33;
NET "SITR"	 LOC = "D9"  | IOSTANDARD = LVCMOS33;
#
NET "SYS_ADR[3]" LOC = "C11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "SYS_ADR[2]" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "SYS_ADR[1]" LOC = "E9"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "SYS_ADR[0]" LOC = "F9"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
#
NET "SYS_CLK[3]" LOC = "D14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 24;
NET "SYS_CLK[2]" LOC = "A14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 24;
NET "SYS_CLK[1]" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 24;
NET "SYS_CLK[0]" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 24;
#
NET "SYS_TRG[3]" LOC = "A16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 24;
NET "SYS_TRG[2]" LOC = "B14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 24;
NET "SYS_TRG[1]" LOC = "A13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 24;
NET "SYS_TRG[0]" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 24;
#
NET "SYS_RES[3]" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 24;
NET "SYS_RES[2]" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 24;
NET "SYS_RES[1]" LOC = "B13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 24;
NET "SYS_RES[0]" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 24;
#
NET "TST_SYN"	 LOC = "D10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
NET "TST_TRG"	 LOC = "G9"  | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
NET "TST_DV0"	 LOC = "B11" | IOSTANDARD = LVCMOS33;
NET "TST_PUL"	 LOC = "A8"  | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
NET "TST_RES"	 LOC = "A11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
NET "TST_SCL"	 LOC = "E13" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "TST_SDA"	 LOC = "C4"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
#
NET "SW[3]"	 LOC = "N17" | IOSTANDARD = LVTTL | PULLUP;
NET "SW[2]"	 LOC = "H18" | IOSTANDARD = LVTTL | PULLUP;
NET "SW[1]"	 LOC = "L14" | IOSTANDARD = LVTTL | PULLUP;
NET "SW[0]"	 LOC = "L13" | IOSTANDARD = LVTTL | PULLUP;
#
NET "BTN"	 LOC = "V4"  | IOSTANDARD = LVTTL | PULLDOWN;
NET "BTS"	 LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN;
NET "BTW"	 LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN;
NET "BTE"	 LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN;
NET "BTC"	 LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN;
#
NET "ROTA"	 LOC = "K18" | IOSTANDARD = LVTTL | PULLUP;
NET "ROTB"	 LOC = "G18" | IOSTANDARD = LVTTL | PULLUP;
#
# ==== Analog-to-Digital Converter (ADC) ====
# some connections shared with SPI Flash, DAC, ADC, and AMP
#
NET "AD_CONV"	 LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6;
#
# ==== Programmable Gain Amplifier (AMP) ====
# some connections shared with SPI Flash, DAC, ADC, and AMP
#
NET "AMP_CS"	 LOC = "N7"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6;
NET "AMP_SHDN"	 LOC = "P7"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6;
#
# ==== Digital-to-Analog Converter (DAC) ====
# some connections shared with SPI Flash, DAC, ADC, and AMP
#
NET "DAC_CLR"	 LOC = "P8"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "DAC_CS"	 LOC = "N8"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
#
# ==== 1-Wire Secure EEPROM (DS)
#
NET "DS_WIRE"	 LOC = "U4"  | IOSTANDARD = LVTTL    | SLEW = SLOW | DRIVE = 8;
#
# ==== FPGA Configuration Mode, INIT_B Pins (FPGA) ====
#
NET "FPGA_M0"     LOC = "M10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "FPGA_M1"     LOC = "V11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "FPGA_M2"     LOC = "T10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "FPGA_INIT_B" LOC = "T3"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4;
#
# NET "FPGA_RDWR_B" LOC = "U10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4;
# NET "FPGA_HSWAP"  LOC = "B3"  | IOSTANDARD = LVCMOS33;
#
# ==== Character LCD (LCD) ====
#
NET "LCD_E"	 LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "LCD_RS"	 LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "LCD_RW"	 LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
#
# LCD data connections are shared with StrataFlash connections SF_D<11:8>
#
# NET "SF_D[8]"	 LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
# NET "SF_D[9]"	 LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
# NET "SF_D[10]" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
# NET "SF_D[11]" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
#
# ==== PS/2 Mouse/Keyboard Port (PS2) ====
#
NET "PS2_CLK"	 LOC = "G14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
NET "PS2_DATA"	 LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
#
# ==== RS-232 Serial Ports (RS232) ====
#
NET "RS232_DCE_RXD" LOC = "R7"  | IOSTANDARD = LVTTL;
NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
NET "RS232_DTE_RXD" LOC = "U8"  | IOSTANDARD = LVTTL;
NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
#
# ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V)
#
NET "SD_A[0]"	 LOC = "T1" | IOSTANDARD = SSTL2_I;
NET "SD_A[1]"	 LOC = "R3" | IOSTANDARD = SSTL2_I;
NET "SD_A[2]"	 LOC = "R2" | IOSTANDARD = SSTL2_I;
NET "SD_A[3]"	 LOC = "P1" | IOSTANDARD = SSTL2_I;
NET "SD_A[4]"	 LOC = "F4" | IOSTANDARD = SSTL2_I;
NET "SD_A[5]"	 LOC = "H4" | IOSTANDARD = SSTL2_I;
NET "SD_A[6]"	 LOC = "H3" | IOSTANDARD = SSTL2_I;
NET "SD_A[7]"	 LOC = "H1" | IOSTANDARD = SSTL2_I;
NET "SD_A[8]"	 LOC = "H2" | IOSTANDARD = SSTL2_I;
NET "SD_A[9]"	 LOC = "N4" | IOSTANDARD = SSTL2_I;
NET "SD_A[10]"	 LOC = "T2" | IOSTANDARD = SSTL2_I;
NET "SD_A[11]"	 LOC = "N5" | IOSTANDARD = SSTL2_I;
NET "SD_A[12]"	 LOC = "P2" | IOSTANDARD = SSTL2_I;
#
NET "SD_BA[0]"	 LOC = "K5" | IOSTANDARD = SSTL2_I;
NET "SD_BA[1]"	 LOC = "K6" | IOSTANDARD = SSTL2_I;
NET "SD_CAS"	 LOC = "C2" | IOSTANDARD = SSTL2_I;
NET "SD_CK_N"	 LOC = "J4" | IOSTANDARD = SSTL2_I;
NET "SD_CK_P"	 LOC = "J5" | IOSTANDARD = SSTL2_I;
NET "SD_CKE"	 LOC = "K3" | IOSTANDARD = SSTL2_I;
NET "SD_CS"	 LOC = "K4" | IOSTANDARD = SSTL2_I;
#
NET "SD_DQ[0]"	 LOC = "L2" | IOSTANDARD = SSTL2_I;
NET "SD_DQ[1]"	 LOC = "L1" | IOSTANDARD = SSTL2_I;
NET "SD_DQ[2]"	 LOC = "L3" | IOSTANDARD = SSTL2_I;
NET "SD_DQ[3]"	 LOC = "L4" | IOSTANDARD = SSTL2_I;
NET "SD_DQ[4]"	 LOC = "M3" | IOSTANDARD = SSTL2_I;
NET "SD_DQ[5]"	 LOC = "M4" | IOSTANDARD = SSTL2_I;
NET "SD_DQ[6]"	 LOC = "M5" | IOSTANDARD = SSTL2_I;
NET "SD_DQ[7]"	 LOC = "M6" | IOSTANDARD = SSTL2_I;
NET "SD_DQ[8]"	 LOC = "E2" | IOSTANDARD = SSTL2_I;
NET "SD_DQ[9]"	 LOC = "E1" | IOSTANDARD = SSTL2_I;
NET "SD_DQ[10]"	 LOC = "F1" | IOSTANDARD = SSTL2_I;
NET "SD_DQ[11]"	 LOC = "F2" | IOSTANDARD = SSTL2_I;
NET "SD_DQ[12]"	 LOC = "G6" | IOSTANDARD = SSTL2_I;
NET "SD_DQ[13]"	 LOC = "G5" | IOSTANDARD = SSTL2_I;
NET "SD_DQ[14]"	 LOC = "H6" | IOSTANDARD = SSTL2_I;
NET "SD_DQ[15]"	 LOC = "H5" | IOSTANDARD = SSTL2_I;
#
NET "SD_LDM"	 LOC = "J2" | IOSTANDARD = SSTL2_I;
NET "SD_LDQS"	 LOC = "L6" | IOSTANDARD = SSTL2_I;
NET "SD_RAS"	 LOC = "C1" | IOSTANDARD = SSTL2_I;
NET "SD_UDM"	 LOC = "J1" | IOSTANDARD = SSTL2_I;
NET "SD_UDQS"	 LOC = "G3" | IOSTANDARD = SSTL2_I;
NET "SD_WE"	 LOC = "D1" | IOSTANDARD = SSTL2_I;
#
# Path to allow connection to top DCM connection
#
NET "SD_CK_FB"	 LOC = "B9" | IOSTANDARD = LVCMOS33;
#
# Prohibit VREF pins
#
CONFIG PROHIBIT = "D2";
CONFIG PROHIBIT = "G4";
CONFIG PROHIBIT = "J6";
CONFIG PROHIBIT = "L5";
CONFIG PROHIBIT = "R4";
#
# ==== Intel StrataFlash Parallel NOR Flash (SF) ====
#
NET "SF_A0[0]"	 LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_A0[1]"	 LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_A0[2]"	 LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_A0[3]"	 LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_A0[4]"	 LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_A0[5]"	 LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_A0[6]"	 LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_A0[7]"	 LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_A0[8]"	 LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_A0[9]"	 LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_A0[10]"	 LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_A0[11]"	 LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_A0[12]"	 LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_A0[13]"	 LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_A0[14]"	 LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_A0[15]"	 LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_A0[16]"	 LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_A0[17]"	 LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_A0[18]"	 LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_A0[19]"	 LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_A1[20]"	 LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_A1[21]"	 LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_A1[22]"	 LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_A1[23]"	 LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
#
NET "SF_BYTE"	 LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_CE0"	 LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
#
NET "SF_D[1]"	 LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_D[2]"	 LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_D[3]"	 LOC = "V9"  | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_D[4]"	 LOC = "U9"  | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_D[5]"	 LOC = "R9"  | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_D[6]"	 LOC = "M9"  | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_D[7]"	 LOC = "N9"  | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_D[8]"	 LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_D[9]"	 LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_D[10]"	 LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_D[11]"	 LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_D[12]"	 LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_D[13]"	 LOC = "P6"  | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_D[14]"	 LOC = "R8"  | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_D[15]"	 LOC = "T8"  | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
#
NET "SF_OE"	 LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
NET "SF_STS"	 LOC = "B18" | IOSTANDARD = LVCMOS33;
NET "SF_WE"	 LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
#
# ==== STMicro SPI serial Flash (SPI) ====
# some connections shared with SPI Flash, DAC, ADC, and AMP
#
NET "SPI_MISO"	 LOC = "N10" | IOSTANDARD = LVCMOS33 ;
NET "SPI_MOSI"	 LOC = "T4"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6;
NET "SPI_SCK"	 LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6;
NET "SPI_SS_B"	 LOC = "U3"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6;
NET "SPI_ALT_CS_JP11" LOC = "R12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6;
#
# ==== VGA Port (VGA) ====
#
NET "VGA_BLUE"	 LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST;
NET "VGA_GREEN"	 LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST;
NET "VGA_HSYNC"	 LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST;
NET "VGA_RED"	 LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST;
NET "VGA_VSYNC"	 LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST;
#
# ==== Xilinx CPLD (XC) ====
#
# NET "XC_CMD[0]"  LOC = "P18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW;
# NET "XC_CMD[1]"  LOC = "N18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW;
# NET "XC_CPLD_EN" LOC = "B10" | IOSTANDARD = LVTTL;
#
# NET "XC_D[0]"	 LOC = "G16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW;
# NET "XC_D[1]"	 LOC = "F18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW;
# NET "XC_D[2]"	 LOC = "F17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW;
# NET "XC_TRIG"	 LOC = "R17" | IOSTANDARD = LVCMOS33;
# NET "XC_GCK0"	 LOC = "H16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
# NET "GCLK10"	 LOC = "C9"  | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
#
NET "ETH_TX_CLK" CLOCK_DEDICATED_ROUTE = FALSE;
NET "ETH_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE;
#
NET "RXB_CLK"    CLOCK_DEDICATED_ROUTE = FALSE;
NET "CRC_CLK"    CLOCK_DEDICATED_ROUTE = FALSE;
#
NET "USB_WR"     CLOCK_DEDICATED_ROUTE = FALSE;
NET "USB_nRD"    CLOCK_DEDICATED_ROUTE = FALSE;
#
NET "iRAM_WR"    CLOCK_DEDICATED_ROUTE = FALSE;
NET "RD_CYCLE"   CLOCK_DEDICATED_ROUTE = FALSE;
#
NET "COM_RES"    CLOCK_DEDICATED_ROUTE = FALSE;
#
NET "PMT[0]"     CLOCK_DEDICATED_ROUTE = FALSE;
NET "PMT[1]"     CLOCK_DEDICATED_ROUTE = FALSE;
NET "TRG_AND"    CLOCK_DEDICATED_ROUTE = FALSE;
#NET "TRG_FAN"	 CLOCK_DEDICATED_ROUTE = FALSE;
NET "TST_SDA"    CLOCK_DEDICATED_ROUTE = FALSE;
#
NET "RS232_DCE_RXD" CLOCK_DEDICATED_ROUTE = FALSE;