-- Temperature logger via RS232 UART
-- carrier frequency = 40 MHz

-- .000 173 610 sec / packet
-- .000 017 360 sec / bit
--  694 or 695 counts (40 MHz) per bit


-- Magic numbers for 57600/8-N-1:

-- Start   347
-- Bit 7  1042
-- Bit 6  1736
-- Bit 5  2431
-- Bit 4  3125
-- Bit 3  3820
-- Bit 2  4514
-- Bit 1  5209
-- Bit 0  5903
-- Stop   6598
-- EOF    6945


-- Packet 0:  101-----
-- Packet 1:  ---MMMMM
-- Packet 2:  ---LLLLL
-- ...
-- Packet 25: ---MMMMM
-- Packet 26: ---LLLLL
-- Packet 27: 010-----

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Tlog is
    Port (
	CLK:     in std_logic;
        RXD:     in std_logic;
	Temp0:  out std_logic_vector(9 downto 0);
	Temp1:  out std_logic_vector(9 downto 0);
	Temp2:  out std_logic_vector(9 downto 0);
	Temp3:  out std_logic_vector(9 downto 0);
	Temp4:  out std_logic_vector(9 downto 0);
	Temp5:  out std_logic_vector(9 downto 0);
	Temp6:  out std_logic_vector(9 downto 0);
	Temp7:  out std_logic_vector(9 downto 0);
	Temp8:  out std_logic_vector(9 downto 0);
	Temp9:  out std_logic_vector(9 downto 0);
	Temp10: out std_logic_vector(9 downto 0);
	Temp11: out std_logic_vector(9 downto 0);
        Temp12: out std_logic_vector(9 downto 0)
	);
end Tlog;

architecture Behavioral of Tlog is

-- signals
--------------------------------------------
	signal RX_CYC: std_logic;
	signal RX_CNT: natural range 8191;

	signal RX_REG: std_logic_vector(7 downto 0);

	signal NEW_PAC: std_logic;
	signal PAC_CNT: natural range 0 to 31;

begin


-- RX cycle
--------------------------------------------
	process(RXD, RX_TERM)
	begin
		if (RX_TERM = '1') then
			RX_CYC <= '0';
		elsif (RXD'event and RXD = '0') then -- (!) check polarity
			RX_CYC <= '1';
		end if;
	end process;
--------------------------------------------

-- Counter
--------------------------------------------
	process(CLK, RX_CYC)
	begin
		if (CLK'event and CLK = '1') then
			if (RX_CYC = '1') then
				RX_CNT <= RX_CNT + 1;
			else
				RX_CNT <= 0;
			end if;
		end if;
	end process;
--------------------------------------------

-- Terminate cycle
--------------------------------------------
	process(CLK, RX_CNT)
	begin
		if (CLK'event and CLK = '0') then
			if (RX_CNT >= 6945) then
				RX_TERM <= '1';
			else
				RX_TERM <= '0';
			end if;
		end if;
--------------------------------------------

-- Latch input data
--------------------------------------------
	process(CLK, RX_CNT, RXD)
	begin
		if (CLK'event and CLK = '0') then
			case RX_CNT is
				when 1042 =>
					RX_REG(7) <= RXD;
				when 1736 =>
					RX_REG(6) <= RXD;
				when 2431 =>
					RX_REG(5) <= RXD;
				when 3125 =>
					RX_REG(4) <= RXD;
				when 3820 =>
					RX_REG(3) <= RXD;
				when 4514 =>
					RX_REG(2) <= RXD;
				when 5209 =>
					RX_REG(1) <= RXD;
				when 5903 =>
					RX_REG(0) <= RXD;
				when others =>
					null;
			end case;
		end if;
	end process;
--------------------------------------------

-- Meet arriving train
--------------------------------------------
	process(CLK, RX_CNT, RX_REG)
	begin
		if (CLK'event and CLK = '0') then
			if (RX_CNT = 3125) then
				if (RX_REG(7 downto 5) = "101") then
					NEW_PAC <= '1';
				elsif (RX_REG(7 downto 5) = "000") then
					NEW_PAC <= '0';
				else
					null;
			else
				null;
			end if;
		end if;				
	end process;
--------------------------------------------

-- Increment packet counter
--------------------------------------------
	process(RX_CYC, NEW_PAC)
	begin
		if (RX_CYC'event and RX_CYC = '1') then
			if (NEW_PAC = '1') then
				PAC_CNT <= 0;
			else
				PAC_CNT <= PAC_CNT + 1;
			end if;
		end if;
	end process;
--------------------------------------------

-- Latch packet data
--------------------------------------------
	process(RX_CYC, PAC_CNT, RX_REG);
	begin
		if (RX_CYC'event and RX_CYC = '0') then
			case PAC_CNT is
				when 0 =>
					Temp0(9 downto 5)  <= RX_REG(4 downto 0);
				when 1 =>
					Temp0(4 downto 0)  <= RX_REG(4 downto 0);
				when 2 =>
					Temp1(9 downto 5)  <= RX_REG(4 downto 0);
				when 3 =>
					Temp1(4 downto 0)  <= RX_REG(4 downto 0);
				when 4 =>
					Temp2(9 downto 5)  <= RX_REG(4 downto 0);
				when 5 =>
					Temp2(4 downto 0)  <= RX_REG(4 downto 0);
				when 6 =>
					Temp3(9 downto 5)  <= RX_REG(4 downto 0);
				when 7 =>
					Temp3(4 downto 0)  <= RX_REG(4 downto 0);
				when 8 =>
					Temp4(9 downto 5)  <= RX_REG(4 downto 0);
				when 9 =>
					Temp4(4 downto 0)  <= RX_REG(4 downto 0);
				when 10 =>
					Temp5(9 downto 5)  <= RX_REG(4 downto 0);
				when 11 =>
					Temp5(4 downto 0)  <= RX_REG(4 downto 0);
				when 12 =>
					Temp6(9 downto 5)  <= RX_REG(4 downto 0);
				when 13 =>
					Temp6(4 downto 0)  <= RX_REG(4 downto 0);
				when 14 =>
					Temp7(9 downto 5)  <= RX_REG(4 downto 0);
				when 15 =>
					Temp7(4 downto 0)  <= RX_REG(4 downto 0);
				when 16 =>
					Temp8(9 downto 5)  <= RX_REG(4 downto 0);
				when 17 =>
					Temp8(4 downto 0)  <= RX_REG(4 downto 0);
				when 18 =>
					Temp9(9 downto 5)  <= RX_REG(4 downto 0);
				when 19 =>
					Temp9(4 downto 0)  <= RX_REG(4 downto 0);
				when 20 =>
					Temp10(9 downto 5) <= RX_REG(4 downto 0);
				when 21 =>
					Temp10(4 downto 0) <= RX_REG(4 downto 0);
				when 22 =>
					Temp11(9 downto 5) <= RX_REG(4 downto 0);
				when 23 =>
					Temp11(4 downto 0) <= RX_REG(4 downto 0);
				when others =>
					null;
			end case;
		end if;
	end process;
--------------------------------------------

end Behavioral;