library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

library XilinxCoreLib;
use XilinxCoreLib.all;

entity ntc is
    Port (
	Clock: in std_logic;
	nCS:   out std_logic;
	SCLK:  out std_logic;
	SO:    in std_logic;
	Data : out std_logic_vector(10 downto 0));
end ntc;

architecture Behavioral of ntc is

-- signals
--------------------------------------------
	signal INT_CNT: natural range 0 to 64;
	signal INT_CLK: std_logic;

	signal PER_CNT: natural range 0 to 65535;

	signal NTC_ACQ: std_logic_vector(10 downto 0);

begin


-- 1 MHz interface clock
--------------------------------------------
	process(Clock)
	begin
		if (Clock'event and Clock = '1') then
			INT_CNT <= INT_CNT + 1;
		end if;
	end process;
--------------------------
	process(Clock, INT_CNT)
	begin
		if (Clock'event and Clock = '0') then
			case INT_CNT is
				when 0 =>
					INT_CLK <= '0';
				when 32 =>
					INT_CLK <= '1';
				when others =>
					null;
			end case;
		end if;
	end process;
--------------------------------------------

-- 1/10 sec conversion period
--------------------------------------------
	process(INT_CLK)
	begin
		if (INT_CLK'event and INT_CLK = '0') then
			PER_CNT <= PER_CNT + 1;
		end if;
	end process;
--------------------------------------------

-- NTC chip select
--------------------------------------------
	process(INT_CLK, PER_CNT)
	begin
		if (INT_CLK'event and INT_CLK = '1') then
			case PER_CNT is
				when 1 =>
					nCS <= '0';
				when 23 =>
					nCS <= '1';
				when others =>
					null;
			end case;
		end if;
	end process;
--------------------------------------------

-- NTC clock control
--------------------------------------------
	process(INT_CLK, PER_CNT)
	begin
		if (INT_CLK'event and INT_CLK = '1') then
			case PER_CNT is
				when 0 =>
					SCLK <= '0';
				when 2 =>
					SCLK <= '1';
				when 3 =>
					SCLK <= '0';
				when 4 =>
					SCLK <= '1';
				when 5 =>
					SCLK <= '0';
				when 6 =>
					SCLK <= '1';
				when 7 =>
					SCLK <= '0';
				when 8 =>
					SCLK <= '1';
				when 9 =>
					SCLK <= '0';
				when 10 =>
					SCLK <= '1';
				when 11 =>
					SCLK <= '0';
				when 12 =>
					SCLK <= '1';
				when 13 =>
					SCLK <= '0';
				when 14 =>
					SCLK <= '1';
				when 15 =>
					SCLK <= '0';
				when 16 =>
					SCLK <= '1';
				when 17 =>
					SCLK <= '0';
				when 18 =>
					SCLK <= '1';
				when 19 =>
					SCLK <= '0';
				when 20 =>
					SCLK <= '1';
				when 21 =>
					SCLK <= '0';
				when 22 =>
					SCLK <= '1';
				when 23 =>
					SCLK <= '0';
				when others =>
					null;
			end case;
		end if;
	end process;
--------------------------------------------
--------------------------------------------

-- NTC data acquisition
--------------------------------------------
	process(INT_CLK, PER_CNT, SO)
	begin
		if (INT_CLK'event and INT_CLK = '1') then
			case PER_CNT is
				when 2 =>
					NTC_ACQ(10) <= SO;
				when 4 =>
					NTC_ACQ(9)  <= SO;
				when 6 =>
					NTC_ACQ(8)  <= SO;
				when 8 =>
					NTC_ACQ(7)  <= SO;
				when 10 =>
					NTC_ACQ(6)  <= SO;
				when 12 =>
					NTC_ACQ(5)  <= SO;
				when 14 =>
					NTC_ACQ(4)  <= SO;
				when 16 =>
					NTC_ACQ(3)  <= SO;
				when 18 =>
					NTC_ACQ(2)  <= SO;
				when 20 =>
					NTC_ACQ(1)  <= SO;
				when 22 =>
					NTC_ACQ(0)  <= SO;
				when others =>
					null;
			end case;
		end if;
	end process;
--------------------------------------------

-- Latch NTC data (Clock <-)
--------------------------------------------
	process(INT_CLK, PER_CNT, NTC_ACQ)
	begin
		if (INT_CLK'event and INT_CLK = '1') then
			case PER_CNT is
				when 23 =>
					Data <= NTC_ACQ;
				when others =>
					null;
			end case;
		end if;
	end process;
--------------------------------------------

end Behavioral;