{ OnSiRoC II Sequencer code for DMILL APC steering with Decoder chip } { X = 29 Y = 30 Z = 31 'ppcf': based on 'ppc1', but faster: only 14*48ns readout, less time for specials use fast sequencer clock for Decoder loading use FAST sequencer clock for sample phase use SLOW sequencer clock for re-read use FAST sequencer clock for readout Read out 10 APC128s: 5 'early' and 5 'late' Ireg = 000 1000 for DMILL Add 8 special events at end of readout. 25 CONVERTS PER SPECIAL 18.7.96 } {=====================================================================} { } { Part 1: basic Sequencer MACROs } { } {=====================================================================} { Sequencer bits: bits 00-03 for Decoder via 'F1' connector: 00 Phi_1 = clock 1 01 Phi_2 = clock 2 02 D = 'data' = 'bit-in' 03 CE = Out/SR CE = 0 => 'SR' = load Decoder shift register CE = 1 => 'Out' = pass to APC bits 00-03 are mirrored on front-panel lemos 04 Clock chopper disable 05 any, may be jumper-selected to appear on lemo SQD out 06 any, may be jumper-selected to appear on lemo SQD out 07 any, may be jumper-selected to appear on lemo SQD out 08 OnSiRoC clock: 0/1 = Fast/Slow clock. Slow = 10 MHz / ( n+1 ), n set by jumpers 09 Pipeline counter 10 Channel Counter 1 for pedestal memory 11 Channel counter 2 for raw data memory 12 Pipeline loop on, for OVFL SBI generation 13 SQD13 = Stop 1 = scan mode active 14 Sequencer memory low/high = 0/1 15 SQD15 = Stop 2 = readout done, FER, wait for start from VME } { Sequencer bits are enumerated from right=00 to left=15: 1111 1100 0000 0000 5432 1098 7654 3210 } {- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -} { APC shift register 'race-through' with zeroes. both clocks high, not chopped. SQD8 = 0 => Fast sequencer clock, opt31 } MACRO Reset_APC_SR 0000 0000 0001 1011 ENDMACRO MACRO Reset_APC_SR_Slow 0000 0001 0001 1011 ENDMACRO {- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -} { APC shift register 'race-through' with ones. SQD6 and SQD7 = 1 => both clocks high, not chopped. SQD8 = 0 => Fast sequencer clock, opt31 } MACRO Set_Latches 0000 0000 0001 1111 ENDMACRO {- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -} { Fast sample clock chopped SQD8 = 0 => using FAST seq. clock SQD12 = 0 => OVFL off. SQD9 = 1 => Pipeline counter on. } MACRO Phi_1_Fast 0000 0010 0000 1001 ENDMACRO MACRO Phi_2_Fast 0000 0010 0000 1010 ENDMACRO MACRO Clock_Fast Phi_1_Fast Phi_2_Fast ENDMACRO {- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -} { Fast sample clock with SBI chopped SQD8 = 0 => using FAST seq. clock SQD12 = 0 => OVFL off. SQD9 = 1 => Pipeline counter on. } MACRO Phi_1_SBI_Fast 0000 0010 0000 1101 ENDMACRO MACRO Clock_SBI_Fast Phi_1_SBI_Fast Phi_2_Fast ENDMACRO {- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -} { Slow sample clock with SBI chopped SQD8 = 0 => using FAST seq. clock SQD12 = 0 => OVFL off. SQD9 = 1 => Pipeline counter on. } MACRO Phi_1_Slow_SBI 0000 0011 0000 1101 ENDMACRO MACRO Phi_2_Slow 0000 0011 0000 1010 ENDMACRO MACRO Clock_Slow_SBI Phi_1_Slow_SBI Phi_2_Slow ENDMACRO MACRO Phi_1_Slow 0000 0011 0000 1001 ENDMACRO MACRO Clock_Slow Phi_1_Slow Phi_2_Slow ENDMACRO {- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -} { Pipeline loop 32 buffers with pipeline counter on Fast sample clock SBI on first } MACRO Pipe_Loop_Fast_SBI Clock_SBI_Fast INSERT 31 TIMES Clock_Fast ENDINSERT ENDMACRO {- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -} { unused at the moment: } { Fast sample clock OVFL chopped SQD8 = 0 => using FAST seq. clock SQD12 = 1 => OVFL on. SQD9 = 1 => Pipeline counter on. } MACRO Phi_1_Fast_OVFL 0001 0010 0000 1001 ENDMACRO MACRO Phi_2_Fast_OVFL 0001 0010 0000 1010 ENDMACRO MACRO Clock_Fast_OVFL Phi_1_Fast_OVFL Phi_2_Fast_OVFL ENDMACRO { Pipeline loop OVFL 32 buffers with pipeline counter on Fast sample clock } MACRO Pipe_Loop_Fast_OVFL INSERT 31 TIMES Clock_Fast_OVFL ENDINSERT ENDMACRO {- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -} { } { misc. MACROs } { } {- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -} MACRO Zero_Slow 0000 0001 0000 0000 ENDMACRO MACRO Zero_Fast 0000 0000 0000 0000 ENDMACRO MACRO Zero_Slow_Out 0000 0001 0000 1000 ENDMACRO MACRO Zero_Fast_Out 0000 0000 0000 1000 ENDMACRO MACRO Zero_Fast_Out_CVT 0000 1000 0010 1000 ENDMACRO MACRO Zero_Fast_Out_CVT_Special 0000 1000 0000 1000 0000 1000 1010 1000 0000 1000 0000 1000 ENDMACRO MACRO RO_End_Slow 1010 0001 0000 1000 ENDMACRO MACRO RO_End_Fast 1010 0000 0000 1000 ENDMACRO MACRO Scope_Trigger Zero_Slow Zero_Slow 0000 0001 0100 1000 {Lemo SQD, middle jumper} Zero_Slow Zero_Slow ENDMACRO {===================================================================} { Decoder bit-01 = 0 <=> select Sample clocks for APC bit-01 = 1 <=> select Readout clocks for APC bit-02 = 1 <=> SR NOT connected to Calibrate registers bit-03 = 1 <=> SR NOT connected to 'special events' registers bit-04 = 1 <=> SR NOT connected to Current source registers bit-05 = 1 <=> RESET switch open <=> preamp sensitive bit-05 = 0 <=> preamp is being resetted bit-06 = 0 <=> IS = 1 bit-07 = 0 <=> SR = 1 bit-08 = 0 <=> R12 = 1 = closed => 1 M½ preamp discharge resistor bit-09 = 1 <=> CS = 0 = open => no extra feedback capacitor (would give lower voltage gain) bit-10 = 0 <=> SEB = 1 => pipeline buffers disconnected bit-11 = 0 <=> LE = 1 bit-12 TO 15 = 0 => RBE high (depending on Decoder internal bond) } { In the SR_IN command the decoder bits are enumerated from right=1 to left = 16 (or 48 with Calibrate, or 56 with Bus, or 63 with current source, or 64 with RG) } {===================================================================} ROUTINE $1 Scan_Mode { scan mode: use only Fast clock ! (opt31, opt41) } Zero_Fast Zero_Fast Zero_Fast { select Fast clock for Decoder loading: 96ns/bit } { === 1 === } { CS2 off, inverted!?! } SR_IN 1 ENDSR_IN { bit 8 unchanged: SLOW clock } { Current source: high = active } { bit 63 = strongest FET bit 57 = weakest FET } { Decoder bits 63-57: 000 1000 for DMILL } SR_IN 000 1000 ENDSR_IN { Bus off: Decoder bits 56-49: 1111 1111 } SR_IN 1111 1111 ENDSR_IN { no calibrate: } SR_IN 0000 0000 0000 0000 0000 0000 0000 0000 ENDSR_IN { Decoder bit 16-1: Initialize APC for scan mode (data taking) } SR_IN 1 1111 011 0000 0000 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 1 => 'late' RBE off } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 1 => 'early' RBE off } { bit 11 = 0 => LE = high } { bit 10 = 1 => SEB low => connect buffers for reset } { bit 09 = 1 => CS open } { bit 08 = 0 => R12 closed } { bit 07 = 0 => SR closed } { bit 06 = 0 => IS closed } { bit 05 = 0 => Reset closed } { bit 04 = 0 => fill Current source regs next } { bit 03 = 0 => fill Bus regs next } { bit 02 = 0 => fill Calibrate regs next } { bit 01 = 0 => select S-Phi } Zero_Fast_Out {need to switch to 'out' to load sub-registers} Zero_Fast_Out { clear sample shift register:} INSERT 64 TIMES Reset_APC_SR ENDINSERT {uses Fast clock: opt31} { === 2 === } { Decoder bits 16-1: prepare latch: set RBE for early and late hybrids select R-Phi } Zero_Fast { switch from out to in } Zero_Fast SR_IN 1 0110 011 0000 1111 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 0 => 'late' RBE on } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 0 => 'early' RBE on } { bit 11 = 0 => LE = high = close enable } { bit 10 = 1 => SEB low => connect buffers } { bit 09 = 1 => CS open } { bit 08 = 0 => R12 closed } { bit 07 = 0 => SR closed } { bit 06 = 0 => IS closed } { bit 05 = 0 => Reset closed } { bit 04 = 1 => don't fill Current source regs } { bit 03 = 1 => don't fill Bus regs next } { bit 02 = 1 => don't fill Calibrate regs } { bit 01 = 1 => select R-Phi } Zero_Fast_Out {need to switch to 'out' to load sub-registers} Zero_Fast_Out { Readout shift register race-through with ones: } INSERT 128 TIMES Set_Latches ENDINSERT {Fast clock: opt31} { Be careful here: we want to nail RPhi1, RPhi2 and RBI at high. 'Zero_Fast' has Phi1, Phi2, D all zero. We want to switch to 'IN' with Phi1, Phi2, D all high: } 0000 0000 0001 0111 { switch from out to in, Fast clock (opt21), not chopped } { === 3 === } Zero_Fast { switch from out to in } Zero_Fast { Decoder bits 16-1: enable sampling (scan mode) - select sample clocks: bit-01 = 0 - open reset switch: bit-05 = 1 } SR_IN 1 0110 011 0001 1110 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 0 => 'late' RBE on } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 0 => 'early' RBE on } { bit 11 = 0 => LE = high } { bit 10 = 1 => SEB low => connect buffers for data } { bit 09 = 1 => CS open } { bit 08 = 0 => R12 closed } { bit 07 = 0 => SR closed } { bit 06 = 0 => IS closed } { bit 05 = 1 => Reset open => preamp sensitive } { bit 04 = 1 => don't fill Current source regs } { bit 03 = 1 => don't fill Bus regs next } { bit 02 = 1 => don't fill Calibrate regs } { bit 01 = 0 => select S-Phi } Zero_Fast_Out {need to switch to 'out' to load sub-registers} Zero_Fast_Out { set SQD 13 to signal end of set-up phase } MACRO SQD13 0010 0000 0000 1000 ENDMACRO SQD13 LOOP Pipe_Loop_Fast_SBI ENDLOOP {=====================================================================} { } { Readout } { } {=====================================================================} ROUTINE $2 ReadOut { use only slow clock during readout ! (opt41) } Zero_Slow_Out Zero_Slow_Out { 10.10.95: scan phase was interrupted anywhere during a clock cycle. Add one more phi 2 Slow, no PIC: } 0000 0001 0000 1010 Zero_Slow Zero_Slow Scope_Trigger {Lemo SQD OUT, Slow, opt31} { === 5 === } { Calibrate off: Decoder bits 17-48 all zero, may be superfluous} Zero_Slow { switch from out to in } Zero_Slow SR_IN 0000 0000 0000 0000 0000 0000 0000 0000 ENDSR_IN { Setup APC for re-read: bit 06 = 1 <=> IS = low <=> disconnect detector bit 07 = 1 <=> SR = low <=> prepare re-read bit 08 = 1 <=> R12= low <=> discharge resistor not used, use reset bit 09 = 1 <=> CS = low <=> don't use extra feedback cap bit 10 = 0 <=> SEB= high<=> SE low <=> disconnect buffers bit 11 = 0 <=> LE = high<=> keep latch switches closed } { Decoder bits 16-1:} SR_IN 1 0110 001 1111 1100 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 0 => 'late' RBE on } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 0 => 'early' RBE on } { bit 11 = 0 => LE = high } { bit 10 = 0 => SEB high => disconnect buffers} { bit 09 = 1 => CS open } { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open => preamp sensitive } { bit 04 = 1 => don't fill Current source regs } { bit 03 = 1 => don't fill Bus regs next } { bit 02 = 0 => fill Calibrate regs next} { bit 01 = 0 => select S-Phi } Zero_Slow_Out {need to switch to 'out' to load sub-registers} Zero_Slow_Out { === 6 === } { Reset preamp: } Zero_Slow { switch from out to in } Zero_Slow SR_IN 1 0110 001 1110 1110 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 0 => 'late' RBE on } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 0 => 'early' RBE on } { bit 11 = 0 => LE = high } { bit 10 = 0 => SEB high => disconnect buffers} { bit 09 = 1 => CS open } { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 0 => Reset closed => resetting } { bit 04 = 1 => don't fill Current source regs } { bit 03 = 1 => don't fill Bus regs next } { bit 02 = 1 => don't fill Calibrate regs next } { bit 01 = 0 => select S-Phi } Zero_Slow_Out {need to switch to 'out' to load sub-registers} Zero_Slow_Out { don't clear the sample shift register, we advance from where the trigger stopped the pipeline } { essential wait state to get rid of saw tooth base line } INSERT 250 TIMES Zero_Slow_Out ENDINSERT {- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -} { Slow sample clock for re-read, chopped SQD9 = 1 => increment pipeline counter SQD12 = 1 => generate OVFL for SBI at buffer 0. } MACRO Phi_1_OVFL_Slow 0001 0011 0000 1001 ENDMACRO MACRO Phi_2_OVFL_Slow 0001 0011 0000 1010 ENDMACRO MACRO Clock_OVFL_Slow Phi_1_OVFL_Slow Phi_2_OVFL_Slow ENDMACRO {- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -} Zero_Slow_Out Zero_Slow_Out { synchronize OVFL with SPhi1 by incrementing SQD9 = pipeline counter: for modified OnSiRoC II, after the 'last bug' fix} INSERT 63 TIMES 0000 0011 0000 1000 ENDINSERT {SLOW clock} { wrap around to buffer 30 from trigger position: } INSERT 30 TIMES Clock_OVFL_Slow ENDINSERT { we take buffer 30 = -2 as pedestal } Zero_Slow_Out Zero_Slow_Out { === 7 === } { prepare re-read: open Reset switch } Zero_Slow { switch Decoder from out to in } Zero_Slow SR_IN 1 0110 001 1111 1110 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 0 => 'late' RBE on } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 0 => 'early' RBE on } { bit 11 = 0 => LE = high } { bit 10 = 0 => SEB high => disconnect buffers} { bit 09 = 1 => CS open } { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open => preamp sensitive } { bit 04 = 1 => don't fill Current source regs } { bit 03 = 1 => don't fill Bus regs next } { bit 02 = 1 => don't fill Calibrate regs next } { bit 01 = 0 => select S-Phi } Zero_Slow_Out {need to switch to 'out' to load sub-registers} Zero_Slow_Out { === 8 === } { SEB low => connect buffer } Zero_Slow { switch from out to in } Zero_Slow SR_IN 1 0110 011 1111 1110 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 0 => 'late' RBE on } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 0 => 'early' RBE on } { bit 11 = 0 => LE = high } { bit 10 = 1 => SEB low => re-read buffers } { bit 09 = 1 => CS open } { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open => preamp sensitive } { bit 04 = 1 => don't fill Current source regs } { bit 03 = 1 => don't fill Bus regs next } { bit 02 = 1 => don't fill Calibrate regs next } { bit 01 = 0 => select S-Phi } Zero_Slow_Out {need to switch to 'out' to load sub-registers} Zero_Slow_Out Zero_Slow { wait for preamp risetime: 100 ns } Zero_Slow { === 9 === } { SEB high } Zero_Slow { switch from out to in } Zero_Slow SR_IN 1 0110 001 1111 1110 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 0 => 'late' RBE on } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 0 => 'early' RBE on } { bit 11 = 0 => LE = high } { bit 10 = 0 => SEB high => buffer disconnected agin } { bit 09 = 1 => CS open } { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open => preamp sensitive } { bit 04 = 1 => don't fill Current source regs } { bit 03 = 1 => don't fill Bus regs next } { bit 02 = 1 => don't fill Calibrate regs next } { bit 01 = 0 => select S-Phi } Zero_Slow_Out {need to switch to 'out' to load sub-registers} Zero_Slow_Out { clock to buffer 0 (leaving out 31)(pedestal): } Clock_OVFL_Slow Clock_OVFL_Slow { === 8b === } { SEB low again} Zero_Slow { switch from out to in } Zero_Slow SR_IN 1 0110 011 1111 1110 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 0 => 'late' RBE on } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 0 => 'early' RBE on } { bit 11 = 0 => LE = high } { bit 10 = 1 => SEB low => re-read buffers } { bit 09 = 1 => CS open } { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open => preamp sensitive } { bit 04 = 1 => don't fill Current source regs } { bit 03 = 1 => don't fill Bus regs next } { bit 02 = 1 => don't fill Calibrate regs next } { bit 01 = 0 => select S-Phi } Zero_Slow_Out {need to switch to 'out' to load sub-registers} Zero_Slow_Out Zero_Slow { wait for preamp risetime: 100 ns } Zero_Slow { === 9b === } { SEB high again } Zero_Slow { switch from out to in } Zero_Slow SR_IN 1 0110 001 1111 1110 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 0 => 'late' RBE on } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 0 => 'early' RBE on } { bit 11 = 0 => LE = high } { bit 10 = 0 => SEB high => buffer disconnected agin } { bit 09 = 1 => CS open } { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open => preamp sensitive } { bit 04 = 1 => don't fill Current source regs } { bit 03 = 1 => don't fill Bus regs next } { bit 02 = 1 => don't fill Calibrate regs next } { bit 01 = 0 => select S-Phi } Zero_Slow_Out {need to switch to 'out' to load sub-registers} Zero_Slow_Out { clock to buffer 1 (pedestal): } Clock_OVFL_Slow { === 8c === } { SEB low again} Zero_Slow { switch from out to in } Zero_Slow SR_IN 1 0110 011 1111 1110 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 0 => 'late' RBE on } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 0 => 'early' RBE on } { bit 11 = 0 => LE = high } { bit 10 = 1 => SEB low => re-read buffers } { bit 09 = 1 => CS open } { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open => preamp sensitive } { bit 04 = 1 => don't fill Current source regs } { bit 03 = 1 => don't fill Bus regs next } { bit 02 = 1 => don't fill Calibrate regs next } { bit 01 = 0 => select S-Phi } Zero_Slow_Out {need to switch to 'out' to load sub-registers} Zero_Slow_Out Zero_Slow { wait for preamp risetime: 100 ns } Zero_Slow { === 9c === } { SEB high again } Zero_Slow { switch from out to in } Zero_Slow SR_IN 1 0110 001 1111 1110 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 0 => 'late' RBE on } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 0 => 'early' RBE on } { bit 11 = 0 => LE = high } { bit 10 = 0 => SEB high => buffer disconnected agin } { bit 09 = 1 => CS open } { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open => preamp sensitive } { bit 04 = 1 => don't fill Current source regs } { bit 03 = 1 => don't fill Bus regs next } { bit 02 = 1 => don't fill Calibrate regs next } { bit 01 = 0 => select S-Phi } Zero_Slow_Out {need to switch to 'out' to load sub-registers} Zero_Slow_Out { === 9x === } { LE low => all latch caps disconnected from readout amp } Zero_Slow { switch from out to in } Zero_Slow SR_IN 1 0110 101 1111 1110 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 0 => 'late' RBE on } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 0 => 'early' RBE on } { bit 11 = 0 => LE = low } { bit 10 = 0 => SEB high => buffer disconnected } { bit 09 = 1 => CS open } { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open => preamp sensitive } { bit 04 = 1 => don't fill Current source regs } { bit 03 = 1 => don't fill Bus regs next } { bit 02 = 1 => don't fill Calibrate regs next } { bit 01 = 0 => select S-Phi } Zero_Slow_Out {need to switch to 'out' to load sub-registers} Zero_Slow_Out { === 10 === } { select R-Phi } Zero_Slow { switch from out to in } Zero_Slow SR_IN 1 0110 101 1111 1111 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 0 => 'late' RBE on } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 0 => 'early' RBE on } { bit 11 = 1 => LE = open } { bit 10 = 0 => SEB high => buffer disconnected } { bit 09 = 1 => CS open } { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open => preamp sensitive } { bit 04 = 1 => don't fill Current source regs } { bit 03 = 1 => don't fill Bus regs next } { bit 02 = 1 => don't fill Calibrate regs next } { bit 01 = 1 => select R-Phi } { be very careful here: Rphi1, RPhi2 and RBI were all nailed at high during the scan phase and up to now. We had a permanent race-through with one's in the readout register. Perhaps this is not so good. Can we just have RPhi2 and RBI high and still connect the latch capacitors to the readout amp? No, we RPhi1 to reset thew readout amp. Now, switch to out, with RPhi selected, still at high:} 0000 0001 0001 1111 {need to switch to 'out' to load sub-registers} 0000 0001 0001 1111 { Readout shift register reset with zeroes: RBI removed in race-through mode => latches disconnected. } INSERT 64 TIMES Reset_APC_SR_Slow ENDINSERT Zero_Slow_Out Zero_Slow_Out { === 11 === } { close Reset, RBE off, select S-Phi} Zero_Slow { switch from out to in } Zero_Slow SR_IN 1 1111 101 1110 1110 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 1 => 'late' RBE off } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 1 => 'early' RBE off } { bit 11 = 1 => LE = low } { bit 10 = 0 => SEB high => buffer disconnected } { bit 09 = 1 => CS open } { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 0 => Reset closed => resetting } { bit 04 = 1 => don't fill Current source regs } { bit 03 = 1 => don't fill Bus regs next } { bit 02 = 1 => don't fill Calibrate regs next } { bit 01 = 0 => select S-Phi } Zero_Slow_Out {need to switch to 'out' to load sub-registers} Zero_Slow_Out { === 12 === } { was select S-Phi, now done in 11 } Zero_Slow_Out {switch to slow for clocking with OVFL, opt31:} Zero_Slow_Out { synchronize OVFL with SPhi1 (just increment SQD9 = pipeline counter): } {INSERT 1 TIMES 0000 0011 0000 1000 ENDINSERT } {SLOW clock, just PIC} {clock to buffer 3 (with pulse):} Clock_OVFL_Slow { buffer 2 } Clock_OVFL_Slow { buffer 3 } Clock_OVFL_Slow { buffer 4 } Zero_Slow_Out Zero_Slow_Out { wait 10 us with reset closed } INSERT 100 TIMES Zero_Slow_Out ENDINSERT { === 13 === } { open reset <=> sensitive } Zero_Slow { switch Decoder from out to in } Zero_Slow SR_IN 1 1111 101 1111 1110 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 1 => 'late' RBE off } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 1 => 'early' RBE off } { bit 11 = 1 => LE = off } { bit 10 = 0 => SEB high => buffer disconnected } { bit 09 = 1 => CS open } { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open => preamp sensitive } { bit 04 = 1 => don't fill Current source regs } { bit 03 = 1 => don't fill Bus regs next } { bit 02 = 1 => don't fill Calibrate regs next } { bit 01 = 0 => select S-Phi } Zero_Slow_Out {need to switch to 'out' to load sub-registers} Zero_Slow_Out { === 14 === } { SEB = low connect buffer for subtract } Zero_Slow { switch from out to in } Zero_Slow SR_IN 1 1111 111 1111 1110 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 1 => 'late' RBE off } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 1 => 'early' RBE off } { bit 11 = 1 => LE = off } { bit 10 = 1 => SEB low => buffer connected for re-read } { bit 09 = 1 => CS open } { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open => preamp sensitive } { bit 04 = 1 => don't fill Current source regs } { bit 03 = 1 => don't fill Bus regs next } { bit 02 = 1 => don't fill Calibrate regs next } { bit 01 = 0 => select S-Phi } Zero_Slow_Out {need to switch to 'out' to load sub-registers} Zero_Slow_Out Zero_Slow { wait for preamp rise time } Zero_Slow { === 15a === } { SEB = high, disconnect buffer again } Zero_Slow { switch from out to in } Zero_Slow SR_IN 1 1111 101 1111 1110 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 1 => 'late' RBE off } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 1 => 'early' RBE off } { bit 11 = 1 => LE = off } { bit 10 = 0 => SEB high => buffer disconnected again } { bit 09 = 1 => CS open } { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open => preamp sensitive } { bit 04 = 1 => don't fill Current source regs } { bit 03 = 1 => don't fill Bus regs next } { bit 02 = 1 => don't fill Calibrate regs next } { bit 01 = 0 => select S-Phi } Zero_Slow_Out {need to switch to 'out' to load sub-registers} Zero_Slow_Out { clock to next buffer: 4 } Clock_OVFL_Slow { === 14b === } { SEB = low = connect buffer for subtract } Zero_Slow { switch from out to in } Zero_Slow SR_IN 1 1111 111 1111 1110 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 1 => 'late' RBE off } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 1 => 'early' RBE off } { bit 11 = 1 => LE = off } { bit 10 = 1 => SEB low => buffer connected for re-read } { bit 09 = 1 => CS open } { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open => preamp sensitive } { bit 04 = 1 => don't fill Current source regs } { bit 03 = 1 => don't fill Bus regs next } { bit 02 = 1 => don't fill Calibrate regs next } { bit 01 = 0 => select S-Phi } Zero_Slow_Out {need to switch to 'out' to load sub-registers} Zero_Slow_Out Zero_Slow { wait for preamp rise time } Zero_Slow { === 15b === } { SEB = high, disconnect buffer again } Zero_Slow { switch from out to in } Zero_Slow SR_IN 1 1111 101 1111 1110 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 1 => 'late' RBE off } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 1 => 'early' RBE off } { bit 11 = 1 => LE = off } { bit 10 = 0 => SEB high => buffer disconnected again } { bit 09 = 1 => CS open } { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open => preamp sensitive } { bit 04 = 1 => don't fill Current source regs } { bit 03 = 1 => don't fill Bus regs next } { bit 02 = 1 => don't fill Calibrate regs next } { bit 01 = 0 => select S-Phi } Zero_Slow_Out {need to switch to 'out' to load sub-registers} Zero_Slow_Out { clock to next buffer: 5 } Clock_OVFL_Slow { === 14c === } { SEB = low = connect buffer for subtract } Zero_Slow { switch from out to in } Zero_Slow SR_IN 1 1111 111 1111 1110 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 1 => 'late' RBE off } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 1 => 'early' RBE off } { bit 11 = 1 => LE = off } { bit 10 = 1 => SEB low => buffer connected for re-read } { bit 09 = 1 => CS open } { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open => preamp sensitive } { bit 04 = 1 => don't fill Current source regs } { bit 03 = 1 => don't fill Bus regs next } { bit 02 = 1 => don't fill Calibrate regs next } { bit 01 = 0 => select S-Phi } Zero_Slow_Out {need to switch to 'out' to load sub-registers} Zero_Slow_Out Zero_Slow { wait for preamp rise time } Zero_Slow { === 15c === } { select R-Phi SEB high => disconnect buffer again LE closed early RBE on } Zero_Slow { switch from out to in } Zero_Slow SR_IN 1 1110 001 1111 1111 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 1 => 'late' RBE off } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 0 => 'early' RBE on } { bit 11 = 0 => LE = high } { bit 10 = 0 => SEB high => buffer disconnected again } { bit 09 = 1 => CS open } { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open => preamp sensitive } { bit 04 = 1 => don't fill Current source regs } { bit 03 = 1 => don't fill Bus regs next } { bit 02 = 1 => don't fill Calibrate regs next } { bit 01 = 1 => select R-Phi } Zero_Slow_Out {need to switch to 'out' to load sub-registers} Zero_Slow_Out {- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -} { Macros for readout: } { bit 04 = 1 => clocks not chopped bit 08 = 0 => use FAST sequencer clock (48 ns per line) } MACRO Phi_1 0000 0000 0001 1001 ENDMACRO MACRO Phi_1_CVT 0000 1000 1011 1001 ENDMACRO MACRO Phi_2 0000 0000 0001 1010 ENDMACRO MACRO Phi_2_CVT 0000 1000 1011 1010 ENDMACRO MACRO Phi_Low 0000 0000 0001 1000 ENDMACRO MACRO Phi_Low_CVT 0000 1000 1011 1000 ENDMACRO MACRO Phi_1_RBI 0000 0000 0001 1101 ENDMACRO MACRO Phi_Low_RBI 0000 0000 0001 1100 ENDMACRO MACRO One_Strip_RO_RBI { first strip, with RBI } Phi_1_RBI Phi_1_RBI Phi_Low_RBI { keep this !! } INSERT 60 TIMES Phi_2 ENDINSERT Phi_Low { keep this !! } ENDMACRO MACRO One_Strip_RO_CVT { for 640 strips, CVT } Phi_1 { reset readout amplifier } Phi_1 { 96 ns reset is necessary. Else: 'banana' } Phi_Low { keep this !! } Phi_2 Phi_2 Phi_2 Phi_2 Phi_2 Phi_2 Phi_2 Phi_2 Phi_2 Phi_2 Phi_Low_CVT { convert for previous channel } ENDMACRO {- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -} {read out for 'early' Hybrid: } Zero_Fast_Out {switch to Fast clock for readout} Zero_Fast_Out One_Strip_RO_RBI INSERT 640 TIMES One_Strip_RO_CVT ENDINSERT {640 FADC converts} Zero_Fast_Out Zero_Fast_Out { wait for 'early' to discharge: } INSERT 240 TIMES Zero_Fast_Out ENDINSERT INSERT 240 TIMES Zero_Fast_Out ENDINSERT {-----------------------------------------------------------} { select 'late' Hybrid } Zero_Fast {switch from out to in } Zero_Fast SR_IN 1 0111 001 1111 1111 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 0 => 'late' RBE on } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 1 => 'early' RBE off } { bit 11 = 0 => LE = high } { bit 10 = 0 => SEB high => buffer disconnected } { bit 09 = 1 => CS open } { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open => preamp sensitive } { bit 04 = 1 => don't fill Current source regs } { bit 03 = 1 => don't fill Bus regs next } { bit 02 = 1 => don't fill Calibrate regs next } { bit 01 = 1 => select R-Phi } Zero_Fast_Out {need to switch to 'out' to load sub-registers} Zero_Fast_Out { read out 640 'late' strips: } One_Strip_RO_RBI INSERT 640 TIMES One_Strip_RO_CVT ENDINSERT { 640 FADC converts} Zero_Fast_Out Zero_Fast_Out {- - - - - - - - - - - - - - - - - - - - - - - - -- - - -- } { special events: read sensors } { Macros for Decoder shift register (bit 03 = 0 <=> 'SR'): use fast clock: bit 8 = 0. } MACRO Phi_1_SR_S 0000 0000 0000 0001 ENDMACRO MACRO Phi_1_D_SR_S 0000 0000 0000 0101 ENDMACRO MACRO Phi_2_SR_S 0000 0000 0000 0010 ENDMACRO MACRO Clock_SR_S Phi_1_SR_S Phi_2_SR_S ENDMACRO MACRO Clock_D_SR_S Phi_1_D_SR_S Phi_2_SR_S ENDMACRO MACRO Four_Clocks_SR_S Clock_SR_S Clock_SR_S Clock_SR_S Clock_SR_S ENDMACRO {- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -} { early Hybrid } { 1. Vanalog: } Zero_Fast { use fast clock for specials readout (18.7.1996)} Zero_Fast { Special event bits 56-49 = 1011 1110: } Clock_D_SR_S Clock_SR_S Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_SR_S { use calibration reg for preparing } { to download the bus reg: } SR_IN 1011 0101 1011 1011 1010 1111 1111 1111 ENDSR_IN { Set-up special events for 'early' Hybrid } { Decoder bits 16-1:} SR_IN 1 1111 001 0000 1011 ENDSR_IN { bit 16 = 1 (unused) } { bit 15 = 1 => 'late' RBE off } { bit 14 = 1 (unused) } { bit 13 = 1 (unused) } { bit 12 = 1 => 'early' RBE off } { bit 11 = 0 => LE = high } { bit 10 = 0 => SEB high => buffers disconnected } { bit 09 = 1 => CS open } { bit 08 = 0 => R12 closed } { bit 07 = 0 => SR closed } { bit 06 = 0 => IS closed } { bit 05 = 0 => Reset closed } { bit 04 = 1 => don't fill I-regs } { bit 03 = 0 => load Bus-regs next } { bit 02 = 1 => don't load Cal-regs next } { bit 01 = 1 => select R-Phi } Zero_Fast_Out {need to switch to 'out' to load sub-registers} Zero_Fast_Out INSERT 240 TIMES Zero_Fast_Out ENDINSERT INSERT 25 TIMES Zero_Fast_Out_CVT_Special ENDINSERT { 2. Aref: } Zero_Fast Zero_Fast { Decoder: move only the first eight bits to get the next 8 bits into the bus reg. careful about the first four bits!} Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_SR_S Clock_D_SR_S Clock_D_SR_S { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open } { bit 04 = 1 => don't fill I-regs } { bit 03 = 0 => load Bus-regs next } { bit 02 = 1 => don't load Cal-regs next } { bit 01 = 1 => select R-Phi } Zero_Fast_Out {need to switch to 'out' to load sub-registers} Zero_Fast_Out INSERT 20 TIMES Zero_Fast_Out ENDINSERT INSERT 25 TIMES Zero_Fast_Out_CVT_Special ENDINSERT { 3. V 2: } Zero_Fast Zero_Fast { shift for 8 more bits to get V2 } Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_SR_S Clock_D_SR_S Clock_D_SR_S { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open } { bit 04 = 1 => don't fill I-regs } { bit 03 = 0 => load Bus-regs next } { bit 02 = 1 => don't load Cal-regs next } { bit 01 = 1 => select R-Phi } Zero_Fast_Out {need to switch to 'out' to load sub-registers} Zero_Fast_Out INSERT 20 TIMES Zero_Fast_Out ENDINSERT INSERT 25 TIMES Zero_Fast_Out_CVT_Special ENDINSERT { 4. V Temperature: } Zero_Fast Zero_Fast { shift for 8 more bits to get VT } Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_SR_S Clock_D_SR_S Clock_D_SR_S { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open } { bit 04 = 1 => don't fill I-regs } { bit 03 = 0 => load Bus-regs next } { bit 02 = 1 => don't load Cal-regs next } { bit 01 = 1 => select R-Phi } Zero_Fast_Out {need to switch to 'out' to load sub-registers} Zero_Fast_Out INSERT 20 TIMES Zero_Fast_Out ENDINSERT INSERT 25 TIMES Zero_Fast_Out_CVT_Special ENDINSERT { 4b. all Bus regs to zero: } Zero_Fast Zero_Fast { shift for 8 more bits to reset to zero } Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_SR_S Clock_D_SR_S Clock_D_SR_S { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open } { bit 04 = 1 => don't fill I-regs } { bit 03 = 0 => load Bus-regs next } { bit 02 = 1 => don't load Cal-regs next } { bit 01 = 1 => select R-Phi } Zero_Fast_Out {need to switch to 'out' to load sub-registers} Zero_Fast_Out {- - - - - - - - - - - - - - - - - - - - - - - - -- - - -- } { late Hybrid } { 5. Vanalog: } Zero_Fast Zero_Fast { Special event bits 56-49 = 1101 1110: } Clock_D_SR_S Clock_D_SR_S Clock_SR_S Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_SR_S { use calibrate register to store 4 more bus register settings: } SR_IN 1101 0101 1101 1011 1100 1111 1111 1111 ENDSR_IN { Decoder bits 16-1:} SR_IN 1 1111 001 0000 1011 ENDSR_IN { bit 16 = 1 (unused) } { bit 15 = 0 => 'late' RBE off } { bit 14 = 1 (unused) } { bit 13 = 1 (unused) } { bit 12 = 1 => 'early' RBE off } { bit 11 = 0 => LE = high } { bit 10 = 0 => SEB high => buffers disconnected } { bit 09 = 1 => CS open } { bit 08 = 0 => R12 closed } { bit 07 = 0 => SR closed } { bit 06 = 0 => IS closed } { bit 05 = 0 => Reset closed } { bit 04 = 1 => don't fill I-regs } { bit 03 = 0 => load Bus-regs next } { bit 02 = 1 => don't load Cal-regs next } { bit 01 = 1 => select R-Phi } Zero_Fast_Out {need to switch to 'out' to load sub-registers} Zero_Fast_Out INSERT 240 TIMES Zero_Fast_Out ENDINSERT INSERT 25 TIMES Zero_Fast_Out_CVT_Special ENDINSERT { 6. Aref: } Zero_Fast Zero_Fast { shift 8 bits to get V1 } Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_SR_S Clock_D_SR_S Clock_D_SR_S { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open } { bit 04 = 1 => don't fill I-regs } { bit 03 = 0 => load Bus-regs next } { bit 02 = 1 => don't load Cal-regs next } { bit 01 = 1 => select R-Phi } Zero_Fast_Out {need to switch to 'out' to load sub-registers} Zero_Fast_Out INSERT 20 TIMES Zero_Fast_Out ENDINSERT INSERT 25 TIMES Zero_Fast_Out_CVT_Special ENDINSERT { 7. V 2: } Zero_Fast Zero_Fast { shift 8 more bits to get V2 } Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_SR_S Clock_D_SR_S Clock_D_SR_S { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open } { bit 04 = 1 => don't fill I-regs } { bit 03 = 0 => load Bus-regs next } { bit 02 = 1 => don't load Cal-regs next } { bit 01 = 1 => select R-Phi } Zero_Fast_Out {need to switch to 'out' to load sub-registers} Zero_Fast_Out INSERT 20 TIMES Zero_Fast_Out ENDINSERT INSERT 25 TIMES Zero_Fast_Out_CVT_Special ENDINSERT { 8. V Temperature: } Zero_Fast Zero_Fast { ...8more bits for VT } Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_SR_S Clock_D_SR_S Clock_D_SR_S { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open } { bit 04 = 1 => don't fill I-regs } { bit 03 = 0 => load Bus-regs next } { bit 02 = 1 => don't load Cal-regs next } { bit 01 = 1 => select R-Phi } Zero_Fast_Out {need to switch to 'out' to load sub-registers} Zero_Fast_Out INSERT 20 TIMES Zero_Fast_Out ENDINSERT INSERT 25 TIMES Zero_Fast_Out_CVT_Special ENDINSERT { 8b. all Bus regs to zero: } Zero_Fast Zero_Fast { ... 8 more bits for reset } Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_D_SR_S Clock_SR_S Clock_D_SR_S Clock_D_SR_S { bit 08 = 1 => R12 open } { bit 07 = 1 => SR open } { bit 06 = 1 => IS open } { bit 05 = 1 => Reset open } { bit 04 = 1 => don't fill I-regs } { bit 03 = 0 => load Bus-regs next } { bit 02 = 1 => don't load Cal-regs next } { bit 01 = 1 => select R-Phi } Zero_Fast_Out {need to switch to 'out' to load sub-registers} Zero_Fast_Out {end, wait for PE: Reset closed to prevent DMILL charge-up} Zero_Fast Zero_Fast { Decoder bit 16-1: Reset closed } SR_IN 1 1111 011 0000 0000 ENDSR_IN { bit 16 = 1 (not used) } { bit 15 = 1 => 'late' RBE off } { bit 14 = 1 (not used) } { bit 13 = 1 (not used) } { bit 12 = 1 => 'early' RBE off } { bit 11 = 0 => LE = high } { bit 10 = 1 => SEB low => connect buffers for reset } { bit 09 = 1 => CS open } { bit 08 = 0 => R12 closed } { bit 07 = 0 => SR closed } { bit 06 = 0 => IS closed } { bit 05 = 0 => Reset closed } { bit 04 = 1 => don't fill Current source regs next } { bit 03 = 1 => don't fill Bus regs next } { bit 02 = 1 => don't fill Calibrate regs next } { bit 01 = 0 => select S-Phi } Zero_Fast_Out {need to switch to 'out' to load sub-registers} Zero_Fast_Out { signal end-of-readout USE SLOW CLOCK (18.7.1996 HN) otherwise L3K timeout: } Zero_Slow_Out Zero_Slow_Out RO_End_Slow { SLOW !!! } RO_End_Slow Zero_Fast Zero_Fast LOOP Zero_Fast ENDLOOP END