Tboard Project Status (11/28/2011 - 13:53:38)
Project File: Tboard.ise Implementation State: Programming File Generated
Module Name: tboard
  • Errors:
No Errors
Target Device: xc3s500e-4fg320
  • Warnings:
400 Warnings
Product Version:ISE 11.3
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
0 (Setup: 0, Hold: 0) (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 772 9,312 8%  
Number of 4 input LUTs 814 9,312 8%  
Number of occupied Slices 896 4,656 19%  
    Number of Slices containing only related logic 896 896 100%  
    Number of Slices containing unrelated logic 0 896 0%  
Total Number of 4 input LUTs 1,064 9,312 11%  
    Number used as logic 814      
    Number used as a route-thru 250      
Number of bonded IOBs 149 232 64%  
    IOB Flip Flops 5      
Number of RAMB16s 2 20 10%  
Number of BUFGMUXs 12 24 50%  
Average Fanout of Non-Clock Nets 2.68      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Nov 28 13:51:51 20110134 Warnings44 Infos
Translation ReportCurrentMon Nov 28 13:52:07 20110167 Warnings0
Map ReportCurrentMon Nov 28 13:52:25 2011032 Warnings1 Info
Place and Route ReportCurrentMon Nov 28 13:53:03 2011039 Warnings4 Infos
Power Report     
Post-PAR Static Timing ReportCurrentMon Nov 28 13:53:10 2011003 Infos
Bitgen ReportCurrentMon Nov 28 13:53:35 2011028 Warnings0
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 11/28/2011 - 13:53:38