Aboard Project Status (04/01/2012 - 16:38:47)
Project File: Aboard.ise Implementation State: Programming File Generated
Module Name: aboard
  • Errors:
 No Errors
Target Device: xc3s500e-4fg320
  • Warnings:
 530 Warnings
Product Version:ISE 11.3
  • Routing Results:
 All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
 All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
 0 (Setup: 0, Hold: 0) (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 653 9,312 7%  
Number of 4 input LUTs 656 9,312 7%  
Number of occupied Slices 695 4,656 14%  
    Number of Slices containing only related logic 695 695 100%  
    Number of Slices containing unrelated logic 0 695 0%  
Total Number of 4 input LUTs 722 9,312 7%  
    Number used as logic 656      
    Number used as a route-thru 66      
Number of bonded IOBs 130 232 56%  
Number of BUFGMUXs 8 24 33%  
Number of DCMs 1 4 25%  
Average Fanout of Non-Clock Nets 2.91      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSun Apr 1 17:17:31 20120202 Warnings16 Infos
Translation ReportCurrentSun Apr 1 17:17:47 20120226 Warnings0
Map ReportCurrentSun Apr 1 17:18:03 2012039 Warnings1 Info
Place and Route ReportCurrentSun Apr 1 17:18:36 2012035 Warnings4 Infos
Power Report     
Post-PAR Static Timing ReportCurrentSun Apr 1 17:18:42 2012003 Infos
Bitgen ReportCurrentSun Apr 1 18:04:27 2012028 Warnings0
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 11/12/2012 - 13:43:29