Aboard Project Status (04/01/2012 - 16:38:47) | |||
Project File: | Aboard.ise | Implementation State: | Programming File Generated |
Module Name: | aboard |
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No Errors |
Target Device: | xc3s500e-4fg320 |
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530 Warnings |
Product Version: | ISE 11.3 |
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All Signals Completely Routed |
Design Goal: | Balanced |
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All Constraints Met |
Design Strategy: | Xilinx Default (unlocked) |
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0 (Setup: 0, Hold: 0) (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 653 | 9,312 | 7% | ||
Number of 4 input LUTs | 656 | 9,312 | 7% | ||
Number of occupied Slices | 695 | 4,656 | 14% | ||
Number of Slices containing only related logic | 695 | 695 | 100% | ||
Number of Slices containing unrelated logic | 0 | 695 | 0% | ||
Total Number of 4 input LUTs | 722 | 9,312 | 7% | ||
Number used as logic | 656 | ||||
Number used as a route-thru | 66 | ||||
Number of bonded IOBs | 130 | 232 | 56% | ||
Number of BUFGMUXs | 8 | 24 | 33% | ||
Number of DCMs | 1 | 4 | 25% | ||
Average Fanout of Non-Clock Nets | 2.91 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Sun Apr 1 17:17:31 2012 | 0 | 202 Warnings | 16 Infos | |
Translation Report | Current | Sun Apr 1 17:17:47 2012 | 0 | 226 Warnings | 0 | |
Map Report | Current | Sun Apr 1 17:18:03 2012 | 0 | 39 Warnings | 1 Info | |
Place and Route Report | Current | Sun Apr 1 17:18:36 2012 | 0 | 35 Warnings | 4 Infos | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | Sun Apr 1 17:18:42 2012 | 0 | 0 | 3 Infos | |
Bitgen Report | Current | Sun Apr 1 18:04:27 2012 | 0 | 28 Warnings | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated |