Device Usage Page (device_usage_statistics.html)

This HTML page displays the device usage statistics that will be sent to Xilinx. The file also contains predefined XML tags used to simplify processing.
 
Please verify the contents are okay to send to Xilinx!
 

 
Software Version and Target Device
Product Version: ISE:11.3 (WebPack) Target Family: spartan3e
OS Platform: LIN Target Device: xc3s500e
Project ID (random number) dce2c8b5ef864f57bdd45a4afaea26cd.f1e6fb51eda0441dbc0bfb7c9c26d52c.26 Target Package: fg320
Registration ID e Target Speed: -4
Date Generated Sun Apr 1 18:04:28 2012
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Registers=555
  • Flip-Flops=555
Counters=7
  • 11-bit up counter=1
  • 26-bit up counter=1
  • 31-bit up counter=1
  • 4-bit up counter=1
  • 6-bit up counter=2
  • 7-bit up counter=1
Xors=2
  • 32-bit xor2=1
  • 8-bit xor2=1
Comparators=2
  • 7-bit comparator greatequal=1
  • 7-bit comparator lessequal=1
MiscellaneousStatistics
  • AGG_BONDED_IO=130
  • AGG_IO=130
  • AGG_SLICE=695
  • NUM_4_INPUT_LUT=722
  • NUM_BONDED_IBUF=37
  • NUM_BONDED_IOB=93
  • NUM_BUFGMUX=8
  • NUM_CYMUX=118
  • NUM_DCM=1
  • NUM_LUT_RT=66
  • NUM_SLICEL=695
  • NUM_SLICE_FF=653
  • NUM_XOR=68
  • Xilinx Core c_compare_v8_0, Xilinx CORE Generator 11.3=2
  • Xilinx Core dist_mem_gen_v4_2, Xilinx CORE Generator 11.3=1
NetStatistics
  • NumNets_Active=1337
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=368
  • NumNodesOfType_Active_CNTRLPIN=287
  • NumNodesOfType_Active_DOUBLE=2957
  • NumNodesOfType_Active_DUMMY=2339
  • NumNodesOfType_Active_DUMMYBANK=2
  • NumNodesOfType_Active_DUMMYESC=9
  • NumNodesOfType_Active_GLOBAL=140
  • NumNodesOfType_Active_HFULLHEX=27
  • NumNodesOfType_Active_HLONG=5
  • NumNodesOfType_Active_HUNIHEX=110
  • NumNodesOfType_Active_INPUT=3008
  • NumNodesOfType_Active_IOBOUTPUT=9
  • NumNodesOfType_Active_OMUX=1164
  • NumNodesOfType_Active_OUTPUT=1173
  • NumNodesOfType_Active_PREBXBY=1255
  • NumNodesOfType_Active_VFULLHEX=135
  • NumNodesOfType_Active_VLONG=28
  • NumNodesOfType_Active_VUNIHEX=237
  • NumNodesOfType_Gnd_CLKPIN=1
  • NumNodesOfType_Gnd_CNTRLPIN=3
  • NumNodesOfType_Gnd_DOUBLE=8
  • NumNodesOfType_Gnd_DUMMYBANK=4
  • NumNodesOfType_Gnd_INPUT=66
  • NumNodesOfType_Gnd_OMUX=66
  • NumNodesOfType_Gnd_OUTPUT=42
  • NumNodesOfType_Gnd_PREBXBY=8
SiteStatistics
  • IBUF-DIFFM=6
  • IBUF-DIFFMI=5
  • IBUF-DIFFS=4
  • IBUF-DIFFSI=7
  • IBUF-IOB=4
  • IOB-DIFFM=44
  • IOB-DIFFS=41
  • SLICEL-SLICEM=341
SiteSummary
  • BUFGMUX=8
  • BUFGMUX_GCLKMUX=8
  • BUFGMUX_GCLK_BUFFER=8
  • DCM=1
  • DCM_DCM=1
  • IBUF=37
  • IBUF_INBUF=37
  • IBUF_PAD=37
  • IOB=93
  • IOB_OUTBUF=93
  • IOB_PAD=93
  • SLICEL=695
  • SLICEL_C1VDD=11
  • SLICEL_C2VDD=7
  • SLICEL_CYMUXF=60
  • SLICEL_CYMUXG=58
  • SLICEL_F=407
  • SLICEL_F5MUX=89
  • SLICEL_FFX=315
  • SLICEL_FFY=338
  • SLICEL_G=315
  • SLICEL_GNDF=35
  • SLICEL_GNDG=37
  • SLICEL_XORF=35
  • SLICEL_XORG=33
 
Configuration Data
BUFGMUX
  • S=[S_INV:8] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:8]
  • S=[S_INV:8] [S:0]
DCM
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:1]
  • RST=[RST:1] [RST_INV:0]
DCM_DCM
  • CLKDV_DIVIDE=[2:1]
  • CLKOUT_PHASE_SHIFT=[FIXED:1]
  • CLK_FEEDBACK=[1X:1]
  • DESKEW_ADJUST=[6:1]
  • DFS_FREQUENCY_MODE=[LOW:1]
  • DLL_FREQUENCY_MODE=[LOW:1]
  • DUTY_CYCLE_CORRECTION=[TRUE:1]
  • FACTORY_JF1=[0XC0:1]
  • FACTORY_JF2=[0X80:1]
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:1]
  • RST=[RST:1] [RST_INV:0]
IBUF_PAD
  • IOATTRBOX=[SSTL2_I:2] [LVTTL:12] [LVCMOS25:1] [LVCMOS33:22]
  • PULL=[PULLUP:4] [PULLDOWN:5]
IOB
  • O1=[O1_INV:0] [O1:93]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:93]
IOB_PAD
  • DRIVEATTRBOX=[4:28] [6:6] [8:22] [12:13]
  • IOATTRBOX=[SSTL2_I:24] [LVTTL:7] [LVCMOS33:62]
  • SLEW=[SLOW:48] [FAST:21]
SLICEL
  • BX=[BX_INV:15] [BX:318]
  • BY=[BY:259] [BY_INV:20]
  • CE=[CE:235] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:55]
  • CLK=[CLK:178] [CLK_INV:188]
  • SR=[SR:31] [SR_INV:21]
SLICEL_CYMUXF
  • 0=[0:60] [0_INV:0]
  • 1=[1_INV:0] [1:60]
SLICEL_CYMUXG
  • 0=[0:58] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:89] [S0_INV:0]
SLICEL_FFX
  • CE=[CE:201] [CE_INV:0]
  • CK=[CK:134] [CK_INV:181]
  • D=[D:300] [D_INV:15]
  • FFX_INIT_ATTR=[INIT0:298] [INIT1:17]
  • FFX_SR_ATTR=[SRLOW:298] [SRHIGH:17]
  • LATCH_OR_FF=[FF:315]
  • SR=[SR:23] [SR_INV:15]
  • SYNC_ATTR=[ASYNC:277] [SYNC:38]
SLICEL_FFY
  • CE=[CE:234] [CE_INV:0]
  • CK=[CK:158] [CK_INV:180]
  • D=[D:318] [D_INV:20]
  • FFY_INIT_ATTR=[INIT0:322] [INIT1:16]
  • FFY_SR_ATTR=[SRLOW:322] [SRHIGH:16]
  • LATCH_OR_FF=[FF:338]
  • SR=[SR:27] [SR_INV:18]
  • SYNC_ATTR=[ASYNC:293] [SYNC:45]
SLICEL_XORF
  • 1=[1_INV:0] [1:35]
 
Pin Data
BUFGMUX
  • I0=8
  • O=8
  • S=8
BUFGMUX_GCLKMUX
  • I0=8
  • OUT=8
  • S=8
BUFGMUX_GCLK_BUFFER
  • IN=8
  • OUT=8
DCM
  • CLK0=1
  • CLK2X=1
  • CLKFB=1
  • CLKIN=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
DCM_DCM
  • CLK0=1
  • CLK2X=1
  • CLKFB=1
  • CLKIN=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
IBUF
  • I=37
  • PAD=37
IBUF_INBUF
  • IN=37
  • OUT=37
IBUF_PAD
  • PAD=37
IOB
  • O1=93
  • PAD=93
IOB_OUTBUF
  • IN=93
  • OUT=93
IOB_PAD
  • PAD=93
SLICEL
  • BX=333
  • BY=279
  • CE=235
  • CIN=55
  • CLK=366
  • COUT=58
  • F1=407
  • F2=369
  • F3=332
  • F4=215
  • G1=313
  • G2=278
  • G3=234
  • G4=174
  • SR=52
  • X=304
  • XB=1
  • XQ=315
  • Y=144
  • YQ=338
SLICEL_C1VDD
  • 1=11
SLICEL_C2VDD
  • 1=7
SLICEL_CYMUXF
  • 0=60
  • 1=60
  • OUT=60
  • S0=60
SLICEL_CYMUXG
  • 0=58
  • 1=58
  • OUT=58
  • S0=58
SLICEL_F
  • A1=407
  • A2=369
  • A3=332
  • A4=215
  • D=407
SLICEL_F5MUX
  • F=89
  • G=89
  • OUT=89
  • S0=89
SLICEL_FFX
  • CE=201
  • CK=315
  • D=315
  • Q=315
  • SR=38
SLICEL_FFY
  • CE=234
  • CK=338
  • D=338
  • Q=338
  • SR=45
SLICEL_G
  • A1=313
  • A2=278
  • A3=234
  • A4=174
  • D=315
SLICEL_GNDF
  • 0=35
SLICEL_GNDG
  • 0=37
SLICEL_XORF
  • 0=35
  • 1=35
  • O=35
SLICEL_XORG
  • 0=33
  • 1=33
  • O=33
 
Tool Usage
Command Line History
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -i -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 4 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -i -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 4 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -i -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 4 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -i -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 4 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -i -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 4 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -i -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 4 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
XSLTProcess 1 1 0 0 0 0 0
_impact 288 274 0 0 0 0 0
arwz 37 37 0 0 0 0 0
bitgen 381 380 0 0 0 0 0
cpldfit 1 1 0 0 0 0 0
edif2ngd 38 38 0 0 0 0 0
hprep6 2 2 0 0 0 0 0
map 468 428 0 0 0 0 0
netgen 4 4 0 0 0 0 0
ngc2edif 10 10 0 0 0 0 0
ngcbuild 38 38 0 0 0 0 0
ngdbuild 501 501 0 0 0 0 0
par 425 417 5 0 0 0 0
taengine 1 1 0 0 0 0 0
trce 420 420 0 0 0 0 0
tsim 1 1 0 0 0 0 0
xawinfo 1 1 0 0 0 0 0
xst 766 761 0 0 0 0 0
 
Help Statistics
Search words with results
add core ( 1 ) bit file generation ( 1 )
compile core ( 1 ) core generator ( 1 )
fonts ( 1 ) global file ( 1 )
open core ( 1 )
Help files
/doc/usenglish/isehelp/ ( 1 ) /doc/usenglish/isehelp/cgn_c_df_compile_lib.htm ( 1 )
/doc/usenglish/isehelp/cgn_c_df_vhdl_instantiation_example.htm ( 1 ) /doc/usenglish/isehelp/cgn_p_add_ip_projnav_design.htm ( 1 )
/doc/usenglish/isehelp/cgn_p_adding_generated_ip_design_vhdl_flow.htm ( 1 ) /doc/usenglish/isehelp/cgn_p_starting_core_generator.htm ( 1 )
/doc/usenglish/isehelp/ise_c_overview.htm ( 2 ) /doc/usenglish/isehelp/ise_c_using_the_design_views.htm ( 1 )
/doc/usenglish/isehelp/ise_p_generate_cpld_programming_file.htm ( 1 ) /doc/usenglish/isehelp/ise_p_generate_fpga_programming_file.htm ( 1 )
/doc/usenglish/isehelp/ite_c_overview.htm ( 1 ) /doc/usenglish/isehelp/pim_p_loading_project_files.htm ( 1 )
/doc/usenglish/isehelp/pim_r_impactfiles.htm ( 1 ) /doc/usenglish/isehelp/pn_db_design_view_properties.htm ( 1 )
/doc/usenglish/isehelp/pn_db_npw_create_new_project.htm ( 1 ) /doc/usenglish/isehelp/pn_db_nsw_select_ip.htm ( 1 )
/doc/usenglish/isehelp/pn_db_nsw_select_source_type.htm ( 1 ) /doc/usenglish/isehelp/pn_r_design_panel.htm ( 1 )
/doc/usenglish/isehelp/pp_db_general_options.htm ( 1 ) /doc/usenglish/isehelp/pp_n_process_generate_programming_file.htm ( 1 )
/doc/usenglish/isehelp/pp_p_process_configure_target_device.htm ( 1 ) /doc/usenglish/isehelp/pp_p_process_update_bitstream_processor_data_xps.htm ( 1 )
/doc/usenglish/isehelp/pta_db_ttc-report-preferences-page.htm ( 1 ) /doc/usenglish/isehelp/rtv_c_rtl_files.htm ( 1 )
/doc/usenglish/isehelp/rtv_c_tech_files.htm ( 1 ) /doc/usenglish/isehelp/sse_db_obj_prop_figure_traits.htm ( 1 )
/doc/usenglish/isehelp/sse_p_creating_symbol_from_ngc.htm ( 1 ) /doc/usenglish/wizards/arwz/awz_db_dcmclkfreq.htm ( 1 )
/doc/usenglish/wizards/arwz/awz_db_dcmgen.htm ( 1 ) /doc/usenglish/wizards/arwz/awz_db_dcmviewbuf.htm ( 1 )
 
Project Statistics
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_Simulator=ISim (VHDL/Verilog)
PROP_Top_Level_Module_Type=HDL PROP_PreferredLanguage=VHDL
PROP_Enable_Message_Filtering=false PROP_Enable_Incremental_Messaging=false
PROP_UseSmartGuide=false Partitions count=1
FILE_COREGEN=2 FILE_COREGENISE=2
FILE_UCF=1 FILE_VHDL=2
FILE_XAW=1 PROP_DevDevice=xc3s500e
PROP_DevFamily=Spartan3E PROP_DevPackage=fg320
PROP_DevSpeed=-4 PROP_FitterReportFormat=HTML
PROP_netgenPostMapSimModelName=tboard_map.vhd PROP_netgenPostParSimModelName=tboard_timesim.vhd
PROP_netgenPostSynthesisSimModelName=tboard_synthesis.vhd PROP_netgenPostXlateSimModelName=tboard_translate.vhd
PROP_PreferredLanguage=VHDL PROP_SDKExportDir=changed
PROP_netgenRenameTopLevEntTo=tboard PROP_UserConstraintEditorPreference=Constraints Editor
PROP_ibiswriterOutputFile=tboard PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_lockPinsUcfFile=changed
PROP_xstWorkDir=changed Project duration(days)=27
 
Core Statistics
Core Type=dist_mem_gen_v4_2
c_addr_width=8 c_default_data=0 c_depth=256 c_has_clk=0
c_has_d=0 c_has_dpo=0 c_has_dpra=0 c_has_i_ce=0
c_has_qdpo=0 c_has_qdpo_ce=0 c_has_qdpo_clk=0 c_has_qdpo_rst=0
c_has_qdpo_srst=0 c_has_qspo=0 c_has_qspo_ce=0 c_has_qspo_rst=0
c_has_qspo_srst=0 c_has_spo=1 c_has_spra=0 c_has_we=0
c_mem_init_file=ROM.mif c_mem_type=0 c_pipeline_stages=0 c_qce_joined=0
c_qualify_we=0 c_read_mif=1 c_reg_a_d_inputs=0 c_reg_dpra_input=0
c_sync_enable=1 c_width=32
Core Type=c_compare_v8_0
c_ainit_val=0 c_b_constant=0 c_b_value=0000000000000000 c_data_type=1
c_has_a_eq_b=0 c_has_a_ge_b=0 c_has_a_gt_b=1 c_has_a_le_b=0
c_has_a_lt_b=0 c_has_a_ne_b=0 c_has_aclr=0 c_has_aset=0
c_has_ce=0 c_has_qa_eq_b=0 c_has_qa_ge_b=0 c_has_qa_gt_b=0
c_has_qa_le_b=0 c_has_qa_lt_b=0 c_has_qa_ne_b=0 c_has_sclr=0
c_has_sset=0 c_pipe_stages=0 c_sync_enable=0 c_sync_priority=1
c_width=16