-- Signal splitter for the collinear fission -- fragments registered by the position-sensistive -- avalanche counters. The discriminator thresholds -- are steered through the CAMAC dataway. Version 1. -- Started 28.12.05. Copyright I.Tsurin, FLNR JINR. -- Module functions: -------------------------------------------- -- NA(I)F(1) - read thresholds; -- NA(I)F(11) - init thresholds; -- NA(I)F(17) - assign thresholds; -- NA(I)F(24) - disable channels; -- NA(I)F(26) - enable channels; -- NA(I)F(27) - test channels; -------------------------------------------- -- Group #1 (I) threshold registers: -------------------------------------------- -- THRES_T1 (RW) NA(0)F(1)/F(17) - threshold for T1 -- THRES_T2 (RW) NA(1)F(1)/F(17) - threshold for T2 -- THRES_X1 (RW) NA(2)F(1)/F(17) - threshold for X1 -- THRES_X2 (RW) NA(3)F(1)/F(17) - threshold for X2 -- THRES_Y1 (RW) NA(4)F(1)/F(17) - threshold for Y1 -- THRES_Y2 (RW) NA(5)F(1)/F(17) - threshold for Y2 -------------------------------------------- -- Control (I) registers: -------------------------------------------- -- ENA_T1 (X) A(0)F(24)/F(26)/F(27) - T1 channel OFF/ON/Test; -- ENA_T2 (X) A(1)F(24)/F(26)/F(27) - T2 channel OFF/ON/Test; -- ENA_X1 (X) A(2)F(24)/F(26)/F(27) - X1 channel OFF/ON/Test; -- ENA_X2 (X) A(3)F(24)/F(26)/F(27) - X2 channel OFF/ON/Test; -- ENA_Y1 (X) A(4)F(24)/F(26)/F(27) - Y1 channel OFF/ON/Test; -- ENA_Y2 (X) A(5)F(24)/F(26)/F(27) - Y2 channel OFF/ON/Test; -------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.numeric_std.all; -- OK. Here the entity starts... -------------------------------------------- entity Splitter is port( -- CAMAC signals -------------------------------------------- N_COM: in std_logic; B_COM: in std_logic; Z_COM: in std_logic; C_COM: in std_logic; I_COM: in std_logic; Strobe1: in std_logic; Strobe2: in std_logic; X_RES: out std_logic; Q_RES: out std_logic; L_RES: out std_logic; WRI_DAT: in std_logic_vector(23 downto 0); RDA_DAT: out std_logic_vector(23 downto 0); F_BUS: in std_logic_vector(4 downto 0); A_BUS: in std_logic_vector(3 downto 0); -------------------------------------------- -- Detector signals -------------------------------------------- SYS_RES: in std_logic; T1_IN: in std_logic; T2_IN: in std_logic; X1_IN: in std_logic; X2_IN: in std_logic; Y1_IN: in std_logic; Y2_IN: in std_logic; T1E_OUT: out std_logic; -- T1 early T1L_OUT: out std_logic; -- T1 late T2E_OUT: out std_logic; -- T2 early T2L_OUT: out std_logic; -- T2 late X1E_OUT: out std_logic; -- X1 early X1L_OUT: out std_logic; -- X1 late X2E_OUT: out std_logic; -- X2 early X2L_OUT: out std_logic; -- X2 late Y1E_OUT: out std_logic; -- Y1 early Y1L_OUT: out std_logic; -- Y1 late Y2E_OUT: out std_logic; -- Y2 early Y2L_OUT: out std_logic; -- Y2 late -------------------------------------------- -- DAC data -------------------------------------------- DAC_data: out std_logic_vector(7 downto 0); DAC_addr: out std_logic_vector(2 downto 0); DAC_strobe: out std_logic; -------------------------------------------- -- Clock frequency -------------------------------------------- Clock: in std_logic ); attribute pinnum: string; attribute pinnum of N_COM: signal is "18"; attribute pinnum of B_COM: signal is "7"; attribute pinnum of Z_COM: signal is "27"; attribute pinnum of C_COM: signal is "16"; attribute pinnum of I_COM: signal is "14"; attribute pinnum of Strobe1: signal is "26"; attribute pinnum of Strobe2: signal is "28"; attribute pinnum of X_RES: signal is "12"; attribute pinnum of Q_RES: signal is "29"; attribute pinnum of L_RES: signal is "24"; attribute pinnum of WRI_DAT: signal is "30,31,36,37,38,39,40,41,44,45,46,47,53,54,55,56,57,58,60,61,62,63,64,65"; attribute pinnum of RDA_DAT: signal is "67,68,69,70,71,73,74,75,83,85,86,87,88,89,90,92,93,94,95,96,97,99,100,101"; attribute pinnum of F_BUS: signal is "8,9,10,11,13"; attribute pinnum of A_BUS: signal is "15,17,19,25"; attribute pinnum of T1_IN: signal is ""; attribute pinnum of T2_IN: signal is ""; attribute pinnum of X1_IN: signal is ""; attribute pinnum of X2_IN: signal is ""; attribute pinnum of Y1_IN: signal is ""; attribute pinnum of Y2_IN: signal is ""; attribute pinnum of T1E_OUT: signal is ""; attribute pinnum of T1L_OUT: signal is ""; attribute pinnum of T2E_OUT: signal is ""; attribute pinnum of T2L_OUT: signal is ""; attribute pinnum of X1E_OUT: signal is ""; attribute pinnum of X1L_OUT: signal is ""; attribute pinnum of X2E_OUT: signal is ""; attribute pinnum of X2L_OUT: signal is ""; attribute pinnum of Y1E_OUT: signal is ""; attribute pinnum of Y1L_OUT: signal is ""; attribute pinnum of Y2E_OUT: signal is ""; attribute pinnum of Y2L_OUT: signal is ""; attribute pinnum of DAC_data: signal is ""; attribute pinnum of SYS_RES: signal is ""; attribute pinnum of Clock: signal is "208"; end; architecture behavior of Splitter is -- Start-up variables -------------------------------------------- signal INI_CNT: natural range 0 to 524287; signal DUM_RES: std_logic; signal PWR_ON: std_logic; -------------------------------------------- -- CAMAC variables -------------------------------------------- signal COM_SET: std_logic; signal SEL_SET: std_logic; signal THRES_T1: natural range 0 to 255; signal THRES_T2: natural range 0 to 255; signal THRES_X1: natural range 0 to 255; signal THRES_X2: natural range 0 to 255; signal THRES_Y1: natural range 0 to 255; signal THRES_Y2: natural range 0 to 255; signal ENA_T1: std_logic; signal ENA_T2: std_logic; signal ENA_X1: std_logic; signal ENA_X2: std_logic; signal ENA_Y1: std_logic; signal ENA_Y2: std_logic; signal FST_T1: std_logic; signal SEC_T1: std_logic; signal FST_T2: std_logic; signal SEC_T2: std_logic; signal FST_X1: std_logic; signal SEC_X1: std_logic; signal FST_X2: std_logic; signal SEC_X2: std_logic; signal FST_Y1: std_logic; signal SEC_Y1: std_logic; signal FST_Y2: std_logic; signal SEC_Y2: std_logic; signal T1E_PUL: std_logic; signal T1L_PUL: std_logic; signal T2E_PUL: std_logic; signal T2L_PUL: std_logic; signal X1E_PUL: std_logic; signal X1L_PUL: std_logic; signal X2E_PUL: std_logic; signal X2L_PUL: std_logic; signal Y1E_PUL: std_logic; signal Y1L_PUL: std_logic; signal Y2E_PUL: std_logic; signal Y2L_PUL: std_logic; signal T1E_CNT: natural range 0 to 1; signal T1L_CNT: natural range 0 to 1; signal T2E_CNT: natural range 0 to 1; signal T2L_CNT: natural range 0 to 1; signal X1E_CNT: natural range 0 to 1; signal X1L_CNT: natural range 0 to 1; signal X2E_CNT: natural range 0 to 1; signal X2L_CNT: natural range 0 to 1; signal Y1E_CNT: natural range 0 to 1; signal Y1L_CNT: natural range 0 to 1; signal Y2E_CNT: natural range 0 to 1; signal Y2L_CNT: natural range 0 to 1; signal T1E_CLR: std_logic; signal T1L_CLR: std_logic; signal T2E_CLR: std_logic; signal T2L_CLR: std_logic; signal X1E_CLR: std_logic; signal X1L_CLR: std_logic; signal X2E_CLR: std_logic; signal X2L_CLR: std_logic; signal Y1E_CLR: std_logic; signal Y1L_CLR: std_logic; signal Y2E_CLR: std_logic; signal Y2L_CLR: std_logic; -------------------------------------------- -- Data type conversion: -- binary#8 -> natural -------------------------------------------- function BIT8_inv_to_NUM(BIT_ARR: std_logic_vector(7 downto 0)) return natural is variable TEMP: natural range 0 to 255; begin TEMP:=0; for I in BIT_ARR'range loop TEMP:= TEMP * 2; if (BIT_ARR(I) = '0') then TEMP:= TEMP + 1; else null; end if; end loop; return TEMP; end BIT8_inv_to_NUM; -------------------------------------------- begin -- Permanent statements -------------------------------------------- DUM_RES <= '0'; L_RES <= '1'; ------------------------- DAC_data(7) <= not WRI_DAT(7); DAC_data(6) <= not WRI_DAT(6); DAC_data(5) <= not WRI_DAT(5); DAC_data(4) <= not WRI_DAT(4); DAC_data(3) <= not WRI_DAT(3); DAC_data(2) <= not WRI_DAT(2); DAC_data(1) <= not WRI_DAT(1); DAC_data(0) <= not WRI_DAT(0); ------------------------- DAC_addr <= A_BUS(2 downto 0); ------------------------- T1E_OUT <= T1E_PUL; T1L_OUT <= T1L_PUL; ------------------------- T2E_OUT <= T2E_PUL; T2L_OUT <= T2L_PUL; ------------------------- X1E_OUT <= X1E_PUL; X1L_OUT <= X1L_PUL; ------------------------- X2E_OUT <= X2E_PUL; X2L_OUT <= X2L_PUL; ------------------------- Y1E_OUT <= Y1E_PUL; Y1L_OUT <= Y1L_PUL; ------------------------- Y2E_OUT <= Y2E_PUL; Y2L_OUT <= Y2L_PUL; -------------------------------------------- -- Start-up reset -------------------------------------------- process(DUM_RES, Clock, PWR_ON) begin if (DUM_RES = '1') then INI_CNT <= 0; elsif (Clock'event and Clock = '1') then if (PWR_ON = '1') then INI_CNT <= INI_CNT + 1; else null; end if; end if; end process; ------------------------- process(DUM_RES, Clock, INI_CNT) begin if (DUM_RES = '1') then PWR_ON <= '1'; elsif (Clock'event and Clock = '0') then if (INI_CNT = 524287) then PWR_ON <= '0'; else PWR_ON <= '1'; end if; end if; end process; -------------------------------------------- -- Common CAMAC reset -- (init registers group #1) -------------------------------------------- process(PWR_ON, Z_COM, Strobe2) begin if (PWR_ON = '1' or Z_COM = '1') then COM_SET <= '0'; elsif (Strobe2'event and Strobe2 = '0') then COM_SET <= '1'; end if; end process; -------------------------------------------- -- Selective CAMAC reset -- (init registers group #1) -------------------------------------------- process(PWR_ON, C_COM, Strobe2) begin if (PWR_ON = '1' or C_COM = '1') then SEL_SET <= '0'; elsif (Strobe2'event and Strobe2 = '0') then SEL_SET <= '1'; end if; end process; -------------------------------------------- -- Write group #1 registers (thresholds) -- All registers are set to maximum values -- after the power-up. Each register is set -- to maximum value by a command NA(I)F(11) -- or overwritten by a command NA(I)F(17)S(1); -------------------------------------------- process(PWR_ON, COM_SET, SEL_SET, Strobe1, N_COM, F_BUS, A_BUS, WRI_DAT) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1') then THRES_T1 <= 255; THRES_T2 <= 255; THRES_X1 <= 255; THRES_X2 <= 255; THRES_Y1 <= 255; THRES_Y2 <= 255; elsif (Strobe1'event and Strobe1 = '0') then if (N_COM = '0' and F_BUS = "10100") then if (A_BUS = "1111") then THRES_T1 <= 255; elsif (A_BUS = "1110") then THRES_T2 <= 255; elsif (A_BUS = "1101") then THRES_X1 <= 255; elsif (A_BUS = "1100") then THRES_X2 <= 255; elsif (A_BUS = "1011") then THRES_Y1 <= 255; elsif (A_BUS = "1010") then THRES_Y2 <= 255; else null; end if; elsif (N_COM = '0' and F_BUS = "01110") then if (A_BUS = "1111") then THRES_T1 <= BIT8_inv_to_NUM(WRI_DAT(7 downto 0)); elsif (A_BUS = "1110") then THRES_T2 <= BIT8_inv_to_NUM(WRI_DAT(7 downto 0)); elsif (A_BUS = "1101") then THRES_X1 <= BIT8_inv_to_NUM(WRI_DAT(7 downto 0)); elsif (A_BUS = "1100") then THRES_X2 <= BIT8_inv_to_NUM(WRI_DAT(7 downto 0)); elsif (A_BUS = "1011") then THRES_Y1 <= BIT8_inv_to_NUM(WRI_DAT(7 downto 0)); elsif (A_BUS = "1010") then THRES_Y2 <= BIT8_inv_to_NUM(WRI_DAT(7 downto 0)); else null; end if; else null; end if; end if; end process; -------------------------------------------- -- Write group #3 registers (channel control) -- All channels are enabled after the power-up. -- Each register is overwritten by commands -- NA(I)F(24)S(1) and NA(I)F(26)S(1) -------------------------------------------- process(PWR_ON, COM_SET, SEL_SET, Strobe1, N_COM, F_BUS, A_BUS) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1') then ENA_T1 <= '1'; ENA_T2 <= '1'; ENA_X1 <= '1'; ENA_X2 <= '1'; ENA_Y1 <= '1'; ENA_Y2 <= '1'; elsif (Strobe1'event and Strobe1 = '0') then if (N_COM = '0' and F_BUS = "00111") then if (A_BUS = "1111") then ENA_T1 <= '0'; elsif (A_BUS = "1110") then ENA_T2 <= '0'; elsif (A_BUS = "1101") then ENA_X1 <= '0'; elsif (A_BUS = "1100") then ENA_X2 <= '0'; elsif (A_BUS = "1011") then ENA_Y1 <= '0'; elsif (A_BUS = "1010") then ENA_Y2 <= '0'; else null; end if; elsif (N_COM = '0' and F_BUS = "00101") then if (A_BUS = "1111") then ENA_T1 <= '1'; elsif (A_BUS = "1110") then ENA_T2 <= '1'; elsif (A_BUS = "1101") then ENA_X1 <= '1'; elsif (A_BUS = "1100") then ENA_X2 <= '1'; elsif (A_BUS = "1011") then ENA_Y1 <= '1'; elsif (A_BUS = "1010") then ENA_Y2 <= '1'; else null; end if; else null; end if; end if; end process; -------------------------------------------- -- Read group #1 registers -------------------------------------------- process(PWR_ON, Z_COM, N_COM, F_BUS, A_BUS, THRES_T1, THRES_T2, THRES_X1, THRES_X2, THRES_Y1, THRES_Y2) begin if (PWR_ON = '1' or Z_COM = '0' or N_COM = '1') then RDA_DAT <= (others => 'Z'); elsif (F_BUS = "11110") then if (A_BUS = "1111") then RDA_DAT(23 downto 8) <= "1111111111111111"; RDA_DAT(7 downto 0) <= conv_std_logic_vector((255 - THRES_T1), 8); elsif (A_BUS = "1110") then RDA_DAT(23 downto 8) <= "1111111111111111"; RDA_DAT(7 downto 0) <= conv_std_logic_vector((255 - THRES_T2), 8); elsif (A_BUS = "1110") then RDA_DAT(23 downto 8) <= "1111111111111111"; RDA_DAT(7 downto 0) <= conv_std_logic_vector((255 - THRES_X1), 8); elsif (A_BUS = "1110") then RDA_DAT(23 downto 8) <= "1111111111111111"; RDA_DAT(7 downto 0) <= conv_std_logic_vector((255 - THRES_X2), 8); elsif (A_BUS = "1110") then RDA_DAT(23 downto 8) <= "1111111111111111"; RDA_DAT(7 downto 0) <= conv_std_logic_vector((255 - THRES_Y1), 8); elsif (A_BUS = "1110") then RDA_DAT(23 downto 8) <= "1111111111111111"; RDA_DAT(7 downto 0) <= conv_std_logic_vector((255 - THRES_Y2), 8); else RDA_DAT <= (others => 'Z'); end if; else RDA_DAT <= (others => 'Z'); end if; end process; -------------------------------------------- -- Genarating X - command response -- NA(I)F(1) - read thresholds; -- NA(I)F(11) - overwrite thresholds; -- NA(I)F(17) - overwrite thresholds; -- NA(K)F(24) - disable channels; -- NA(K)F(26) - enable channels; -- NA(K)F(27) - test channels; -------------------------------------------- process(PWR_ON, Z_COM, N_COM, F_BUS, A_BUS) begin if (PWR_ON = '0' and Z_COM = '1' and N_COM = '0') then -- overwrite, set or read group #1 registers -------------------------------------------- if (F_BUS = "11110" or F_BUS = "10100" or F_BUS = "01110") then if (A_BUS = "1111") then X_RES <= '0'; elsif (A_BUS = "1110") then X_RES <= '0'; elsif (A_BUS = "1101") then X_RES <= '0'; elsif (A_BUS = "1100") then X_RES <= '0'; elsif (A_BUS = "1011") then X_RES <= '0'; elsif (A_BUS = "1010") then X_RES <= '0'; else X_RES <= 'Z'; end if; -- enable, disable or test group #3 registers -------------------------------------------- elsif (F_BUS = "00111" or F_BUS = "00101" or F_BUS = "00100") then if (A_BUS = "1111") then X_RES <= '0'; elsif (A_BUS = "1110") then X_RES <= '0'; elsif (A_BUS = "1101") then X_RES <= '0'; elsif (A_BUS = "1100") then X_RES <= '0'; elsif (A_BUS = "1011") then X_RES <= '0'; elsif (A_BUS = "1010") then X_RES <= '0'; else X_RES <= 'Z'; end if; else X_RES <= 'Z'; end if; else X_RES <= 'Z'; end if; end process; -------------------------------------------- -- Genarating Q - status response -------------------------------------------- process(PWR_ON, Z_COM, N_COM, F_BUS, A_BUS, ENA_T1, ENA_T2, ENA_X1, ENA_X2, ENA_Y1, ENA_Y2) begin if (PWR_ON = '0' and Z_COM = '1' and N_COM = '0') then if (F_BUS = "00100") then if (A_BUS = "1111") then Q_RES <= not ENA_T1; elsif (A_BUS = "1110") then Q_RES <= not ENA_T2; elsif (A_BUS = "1101") then Q_RES <= not ENA_X1; elsif (A_BUS = "1100") then Q_RES <= not ENA_X2; elsif (A_BUS = "1011") then Q_RES <= not ENA_Y1; elsif (A_BUS = "1010") then Q_RES <= not ENA_Y2; else Q_RES <= 'Z'; end if; else Q_RES <= 'Z'; end if; else Q_RES <= 'Z'; end if; end process; -------------------------------------------- -- DAC write enable strobe -------------------------------------------- process(PWR_ON, Z_COM, N_COM, F_BUS, A_BUS, Strobe1) begin if (PWR_ON = '0' and Z_COM = '1' and N_COM = '0') then if (F_BUS = "01110") then if (A_BUS = "1111") then DAC_strobe <= not Strobe1; elsif (A_BUS = "1110") then DAC_strobe <= not Strobe1; elsif (A_BUS = "1101") then DAC_strobe <= not Strobe1; elsif (A_BUS = "1100") then DAC_strobe <= not Strobe1; elsif (A_BUS = "1011") then DAC_strobe <= not Strobe1; elsif (A_BUS = "1010") then DAC_strobe <= not Strobe1; else DAC_strobe <= '0'; end if; else DAC_strobe <= '0'; end if; else DAC_strobe <= '0'; end if; end process; -------------------------------------------- -------------------------------------------- -- Signal splitting in the T1 channel -------------------------------------------- process(PWR_ON, COM_SET, SEL_SET, ENA_T1, SYS_RES, T1_IN, SEC_T1) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or ENA_T1 = '0' or SYS_RES = '0') then FST_T1 <= '0'; elsif (T1_IN'event and T1_IN = '0') then if (SEC_T1 = '0') then FST_T1 <= '1'; else FST_T1 <= '0'; end if; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, ENA_T1, SYS_RES, T1_IN, FST_T1) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or ENA_T1 = '0' or SYS_RES = '0') then SEC_T1 <= '0'; elsif (T1_IN'event and T1_IN = '1') then if (FST_T1 = '1') then SEC_T1 <= '1'; else SEC_T1 <='0'; end if; end if; end process; -------------------------------------------- -- Signal splitting in the T2 channel -------------------------------------------- process(PWR_ON, COM_SET, SEL_SET, ENA_T2, SYS_RES, T2_IN, SEC_T2) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or ENA_T2 = '0' or SYS_RES = '0') then FST_T2 <= '0'; elsif (T2_IN'event and T2_IN = '0') then if (SEC_T2 = '0') then FST_T2 <= '1'; else FST_T2 <= '0'; end if; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, ENA_T2, SYS_RES, T2_IN, FST_T2) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or ENA_T2 = '0' or SYS_RES = '0') then SEC_T2 <= '0'; elsif (T2_IN'event and T2_IN = '1') then if (FST_T2 = '1') then SEC_T2 <= '1'; else SEC_T2 <='0'; end if; end if; end process; -------------------------------------------- -- Signal splitting in the X1 channel -------------------------------------------- process(PWR_ON, COM_SET, SEL_SET, ENA_X1, SYS_RES, X1_IN, SEC_X1) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or ENA_X1 = '0' or SYS_RES = '0') then FST_X1 <= '0'; elsif (X1_IN'event and X1_IN = '0') then if (SEC_X1 = '0') then FST_X1 <= '1'; else FST_X1 <= '0'; end if; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, ENA_X1, SYS_RES, X1_IN, FST_X1) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or ENA_X1 = '0' or SYS_RES = '0') then SEC_X1 <= '0'; elsif (X1_IN'event and X1_IN = '1') then if (FST_X1 = '1') then SEC_X1 <= '1'; else SEC_X1 <='0'; end if; end if; end process; -------------------------------------------- -- Signal splitting in the X2 channel -------------------------------------------- process(PWR_ON, COM_SET, SEL_SET, ENA_X2, SYS_RES, X2_IN, SEC_X2) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or ENA_X2 = '0' or SYS_RES = '0') then FST_X2 <= '0'; elsif (X2_IN'event and X2_IN = '0') then if (SEC_X2 = '0') then FST_X2 <= '1'; else FST_X2 <= '0'; end if; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, ENA_X2, SYS_RES, X2_IN, FST_X2) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or ENA_X2 = '0' or SYS_RES = '0') then SEC_X2 <= '0'; elsif (X2_IN'event and X2_IN = '1') then if (FST_X2 = '1') then SEC_X2 <= '1'; else SEC_X2 <='0'; end if; end if; end process; -------------------------------------------- -- Signal splitting in the Y1 channel -------------------------------------------- process(PWR_ON, COM_SET, SEL_SET, ENA_Y1, SYS_RES, Y1_IN, SEC_Y1) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or ENA_Y1 = '0' or SYS_RES = '0') then FST_Y1 <= '0'; elsif (Y1_IN'event and Y1_IN = '0') then if (SEC_Y1 = '0') then FST_Y1 <= '1'; else FST_Y1 <= '0'; end if; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, ENA_Y1, SYS_RES, Y1_IN, FST_Y1) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or ENA_Y1 = '0' or SYS_RES = '0') then SEC_Y1 <= '0'; elsif (Y1_IN'event and Y1_IN = '1') then if (FST_Y1 = '1') then SEC_Y1 <= '1'; else SEC_Y1 <='0'; end if; end if; end process; -------------------------------------------- -- Signal splitting in the Y2 channel -------------------------------------------- process(PWR_ON, COM_SET, SEL_SET, ENA_Y2, SYS_RES, Y2_IN, SEC_Y2) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or ENA_Y2 = '0' or SYS_RES = '0') then FST_Y2 <= '0'; elsif (Y2_IN'event and Y2_IN = '0') then if (SEC_Y2 = '0') then FST_Y2 <= '1'; else FST_Y2 <= '0'; end if; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, ENA_Y2, SYS_RES, Y2_IN, FST_Y2) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or ENA_Y2 = '0' or SYS_RES = '0') then SEC_Y2 <= '0'; elsif (Y2_IN'event and Y2_IN = '1') then if (FST_Y2 = '1') then SEC_Y2 <= '1'; else SEC_Y2 <='0'; end if; end if; end process; -------------------------------------------- -- Forming a short pulse for the earlier T1 -------------------------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, T1E_CLR, FST_T1) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0' or T1E_CLR = '1') then T1E_PUL <= '0'; elsif (FST_T1'event and FST_T1 = '1') then T1E_PUL <= '1'; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, T1E_PUL) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then T1E_CNT <= 0; elsif (Clock'event and Clock = '1') then if (T1E_PUL = '1') then T1E_CNT <= T1E_CNT + 1; else T1E_CNT <= 0; end if; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, T1E_CNT) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then T1E_CLR <= '0'; elsif (Clock'event and Clock = '0') then if (T1E_CNT = 1) then T1E_CLR <= '1'; else T1E_CLR <= '0'; end if; end if; end process; -------------------------------------------- -- Forming a short pulse for the later T1 -------------------------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, T1L_CLR, SEC_T1) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0' or T1L_CLR = '1') then T1L_PUL <= '0'; elsif (SEC_T1'event and SEC_T1 = '1') then T1L_PUL <= '1'; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, T1L_PUL) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then T1L_CNT <= 0; elsif (Clock'event and Clock = '1') then if (T1L_PUL = '1') then T1L_CNT <= T1L_CNT + 1; else T1L_CNT <= 0; end if; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, T1L_CNT) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then T1L_CLR <= '0'; elsif (Clock'event and Clock = '0') then if (T1L_CNT = 1) then T1L_CLR <= '1'; else T1L_CLR <= '0'; end if; end if; end process; -------------------------------------------- -- Forming a short pulse for the earlier T2 -------------------------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, T2E_CLR, FST_T2) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0' or T2E_CLR = '1') then T2E_PUL <= '0'; elsif (FST_T2'event and FST_T2 = '1') then T2E_PUL <= '1'; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, T2E_PUL) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then T2E_CNT <= 0; elsif (Clock'event and Clock = '1') then if (T2E_PUL = '1') then T2E_CNT <= T2E_CNT + 1; else T2E_CNT <= 0; end if; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, T2E_CNT) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then T2E_CLR <= '0'; elsif (Clock'event and Clock = '0') then if (T2E_CNT = 1) then T2E_CLR <= '1'; else T2E_CLR <= '0'; end if; end if; end process; -------------------------------------------- -- Forming a short pulse for the later T2 -------------------------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, T2L_CLR, SEC_T2) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0' or T2L_CLR = '1') then T2L_PUL <= '0'; elsif (SEC_T2'event and SEC_T2 = '1') then T2L_PUL <= '1'; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, T2L_PUL) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then T2L_CNT <= 0; elsif (Clock'event and Clock = '1') then if (T2L_PUL = '1') then T2L_CNT <= T2L_CNT + 1; else T2L_CNT <= 0; end if; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, T2L_CNT) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then T2L_CLR <= '0'; elsif (Clock'event and Clock = '0') then if (T2L_CNT = 1) then T2L_CLR <= '1'; else T2L_CLR <= '0'; end if; end if; end process; -------------------------------------------- -- Forming a short pulse for the earlier X1 -------------------------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, X1E_CLR, FST_X1) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0' or X1E_CLR = '1') then X1E_PUL <= '0'; elsif (FST_X1'event and FST_X1 = '1') then X1E_PUL <= '1'; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, X1E_PUL) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then X1E_CNT <= 0; elsif (Clock'event and Clock = '1') then if (X1E_PUL = '1') then X1E_CNT <= X1E_CNT + 1; else X1E_CNT <= 0; end if; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, X1E_CNT) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then X1E_CLR <= '0'; elsif (Clock'event and Clock = '0') then if (X1E_CNT = 1) then X1E_CLR <= '1'; else X1E_CLR <= '0'; end if; end if; end process; -------------------------------------------- -- Forming a short pulse for the later X1 -------------------------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, X1L_CLR, SEC_X1) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0' or X1L_CLR = '1') then X1L_PUL <= '0'; elsif (SEC_X1'event and SEC_X1 = '1') then X1L_PUL <= '1'; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, X1L_PUL) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then X1L_CNT <= 0; elsif (Clock'event and Clock = '1') then if (X1L_PUL = '1') then X1L_CNT <= X1L_CNT + 1; else X1L_CNT <= 0; end if; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, X1L_CNT) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then X1L_CLR <= '0'; elsif (Clock'event and Clock = '0') then if (X1L_CNT = 1) then X1L_CLR <= '1'; else X1L_CLR <= '0'; end if; end if; end process; -------------------------------------------- -- Forming a short pulse for the earlier X2 -------------------------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, X2E_CLR, FST_X2) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0' or X2E_CLR = '1') then X2E_PUL <= '0'; elsif (FST_X2'event and FST_X2 = '1') then X2E_PUL <= '1'; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, X2E_PUL) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then X2E_CNT <= 0; elsif (Clock'event and Clock = '1') then if (X2E_PUL = '1') then X2E_CNT <= X2E_CNT + 1; else X2E_CNT <= 0; end if; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, X2E_CNT) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then X2E_CLR <= '0'; elsif (Clock'event and Clock = '0') then if (X2E_CNT = 1) then X2E_CLR <= '1'; else X2E_CLR <= '0'; end if; end if; end process; -------------------------------------------- -- Forming a short pulse for the later X2 -------------------------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, X2L_CLR, SEC_X2) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0' or X2L_CLR = '1') then X2L_PUL <= '0'; elsif (SEC_X2'event and SEC_X2 = '1') then X2L_PUL <= '1'; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, X2L_PUL) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then X2L_CNT <= 0; elsif (Clock'event and Clock = '1') then if (X2L_PUL = '1') then X2L_CNT <= X2L_CNT + 1; else X2L_CNT <= 0; end if; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, X2L_CNT) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then X2L_CLR <= '0'; elsif (Clock'event and Clock = '0') then if (X2L_CNT = 1) then X2L_CLR <= '1'; else X2L_CLR <= '0'; end if; end if; end process; -------------------------------------------- -- Forming a short pulse for the earlier Y1 -------------------------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Y1E_CLR, FST_Y1) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0' or Y1E_CLR = '1') then Y1E_PUL <= '0'; elsif (FST_Y1'event and FST_Y1 = '1') then Y1E_PUL <= '1'; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, Y1E_PUL) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then Y1E_CNT <= 0; elsif (Clock'event and Clock = '1') then if (Y1E_PUL = '1') then Y1E_CNT <= Y1E_CNT + 1; else Y1E_CNT <= 0; end if; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, Y1E_CNT) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then Y1E_CLR <= '0'; elsif (Clock'event and Clock = '0') then if (Y1E_CNT = 1) then Y1E_CLR <= '1'; else Y1E_CLR <= '0'; end if; end if; end process; -------------------------------------------- -- Forming a short pulse for the later Y1 -------------------------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Y1L_CLR, SEC_Y1) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0' or Y1L_CLR = '1') then Y1L_PUL <= '0'; elsif (SEC_Y1'event and SEC_Y1 = '1') then Y1L_PUL <= '1'; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, Y1L_PUL) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then Y1L_CNT <= 0; elsif (Clock'event and Clock = '1') then if (Y1L_PUL = '1') then Y1L_CNT <= Y1L_CNT + 1; else Y1L_CNT <= 0; end if; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, Y1L_CNT) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then Y1L_CLR <= '0'; elsif (Clock'event and Clock = '0') then if (Y1L_CNT = 1) then Y1L_CLR <= '1'; else Y1L_CLR <= '0'; end if; end if; end process; -------------------------------------------- -- Forming a short pulse for the earlier Y2 -------------------------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Y2E_CLR, FST_Y2) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0' or Y2E_CLR = '1') then Y2E_PUL <= '0'; elsif (FST_Y2'event and FST_Y2 = '1') then Y2E_PUL <= '1'; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, Y2E_PUL) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then Y2E_CNT <= 0; elsif (Clock'event and Clock = '1') then if (Y2E_PUL = '1') then Y2E_CNT <= Y2E_CNT + 1; else Y2E_CNT <= 0; end if; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, Y2E_CNT) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then Y2E_CLR <= '0'; elsif (Clock'event and Clock = '0') then if (Y2E_CNT = 1) then Y2E_CLR <= '1'; else Y2E_CLR <= '0'; end if; end if; end process; -------------------------------------------- -- Forming a short pulse for the later Y2 -------------------------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Y2L_CLR, SEC_Y2) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0' or Y2L_CLR = '1') then Y2L_PUL <= '0'; elsif (SEC_Y2'event and SEC_Y2 = '1') then Y2L_PUL <= '1'; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, Y2L_PUL) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then Y2L_CNT <= 0; elsif (Clock'event and Clock = '1') then if (Y2L_PUL = '1') then Y2L_CNT <= Y2L_CNT + 1; else Y2L_CNT <= 0; end if; end if; end process; ------------------------- process(PWR_ON, COM_SET, SEL_SET, SYS_RES, Clock, Y2L_CNT) begin if (PWR_ON = '1' or COM_SET = '1' or SEL_SET = '1' or SYS_RES = '0') then Y2L_CLR <= '0'; elsif (Clock'event and Clock = '0') then if (Y2L_CNT = 1) then Y2L_CLR <= '1'; else Y2L_CLR <= '0'; end if; end if; end process; -------------------------------------------- end;