-- The FTI_0 and FTI_2 raw data readout.

-- Channel mapping:
--
--	Cable	 Location	Pin 	Signal
-------------------------------------------
--	FTI_0/1   South 	Tinp00	FT0_DAT( 7..0)
--	FTI_0/1   South 	Tinp01	FT0_DAT(15..8)
--
--	FTI_0/2   North 	Tinp20	FT0_DAT(23..16)
--	FTI_0/2   North 	Tinp21	FT0_DAT(31..24)
--
--	FTI_2/1   Outer 	Tinp10	FT2_DAT( 7..0)
--	FTI_2/2   Outer 	Tinp11	FT2_DAT(15..8)
--
--	FTI_2/3   Inner 	Tinp30	FT2_DAT(16..23)
--	FTI_2/4   Inner 	Tinp31	FT2_DAT(24..31)
-------------------------------------------

-- Trigger pulses of the last 24 bunch crossings
-- are kept in the internal pipeline, the content
-- of which around T0 is transmitted to the ACEX
-- chip and read out into FTI0 data bank whose
-- structure is similar to the SITR bank of the
-- pad system.

-- Copyright I.Tsurin, University of Antwerpen,
-- on behalf of DESY.
--------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;

library LPM;
use LPM.LPM_components.all;

--	OK. Here the entity starts...
--------------------------------------------
entity L1trigger is
port(
	MSTB_SW: in std_logic_vector(3 downto 0);	-- spare (for use without VME access);

	DLY_OUT: out std_logic;						-- HERA clock routing to the delay line;
	DLY_TAP: in  std_logic_vector(9 downto 0);	-- Delayed HERA clock frequency;
	
	Rdata: out std_logic_vector(7 downto 0);	-- Raw data bus to the ACEX;
	RDstb: out std_logic;						-- Strobe for the raw data;

	TXD: out std_logic;							-- Serial interface output;
	RXD: in  std_logic;							-- Serial interface input;
	
	Enable: in std_logic;						-- "Pipeline enable" in the test mode;
	Clear: in std_logic;						-- "Fast clear" in the test mode;

	Tinp00: in std_logic_vector(7 downto 0);	-- |	
	Tinp01: in std_logic_vector(7 downto 0);	-- |
	Tinp10: in std_logic_vector(7 downto 0);	-- |
	Tinp11: in std_logic_vector(7 downto 0);	-- |
	Tinp20: in std_logic_vector(7 downto 0);	-- |
	Tinp21: in std_logic_vector(7 downto 0);	-- | Input trigger data from 6 repeaters;
	Tinp30: in std_logic_vector(7 downto 0);	-- |
	Tinp31: in std_logic_vector(7 downto 0);	-- |
	Tinp40: in std_logic_vector(7 downto 0);	-- |
	Tinp41: in std_logic_vector(7 downto 0);	-- |
	Tinp50: in std_logic_vector(7 downto 0);	-- |
	Tinp51: in std_logic_vector(7 downto 0);	-- |

	TSTB0: in std_logic;	-- Strobe for the trigger data from the 1st repeater;
	TSTB1: in std_logic;	-- Strobe for the trigger data from the 2nd repeater;
	TSTB2: in std_logic;	-- |
	TSTB3: in std_logic;	-- | ...
	TSTB4: in std_logic;	-- |
	TSTB5: in std_logic;	-- Strobe for the trigger data from the 6th repeater;
	
	Mout: out std_logic_vector(7 downto 0);		-- L1 output word;	
	MSTB: out std_logic;						-- L1 data strobe;
	
	HCLK: in std_logic;			-- HERA synchronization frequency;
	GEN: in std_logic;			-- Synchronization frequency in the test mode;
	
	BCK_PAN: in std_logic;		-- Jumper for the external controls;
	
	EVT_LED: out std_logic;		-- LED indicating the successful event;
	VTO_LED: out std_logic;		-- LED indicating the veto event;
	
	FCLR: in std_logic;			-- "Fast clear" signal from the H1 central trigger;
	PEN: in std_logic;			-- "Pipeline enable" from the H1 central triger;
	
	LAM0: in std_logic_vector(2 downto 0); 	-- Frontend Alteras download status;
	LAM1: in std_logic_vector(2 downto 0)	-- Frontend Alteras download status;
	);

	attribute pinnum: string;

	attribute pinnum of MSTB_SW: signal is "7,4,3,2";		
	attribute pinnum of DLY_OUT: signal is "8";
	attribute pinnum of DLY_TAP: signal is "41,40,20,18,17,16,13,11,10,9";
	
	attribute pinnum of Rdata: signal is "43,44,46,47,53,54,55,57";
	attribute pinnum of RDstb: signal is "49";

	attribute pinnum of RXD: signal is "48";
	attribute pinnum of TXD: signal is "50";
	
	attribute pinnum of Enable: signal is "58";
	attribute pinnum of Clear: signal is "59";

	attribute pinnum of Tinp00: signal is "184,183,182,181,180,178,174,173";
	attribute pinnum of Tinp01: signal is "195,192,191,190,189,187,186,185";
	attribute pinnum of Tinp10: signal is "204,203,202,201,200,198,197,196";
	attribute pinnum of Tinp11: signal is "220,219,217,216,215,207,206,205";
	attribute pinnum of Tinp20: signal is "231,230,226,225,224,223,222,221";
	attribute pinnum of Tinp21: signal is "239,238,237,236,235,234,233,232";
	attribute pinnum of Tinp30: signal is "69,68,66,65,64,63,62,61";
	attribute pinnum of Tinp31: signal is "80,79,77,76,75,74,71,70";
	attribute pinnum of Tinp40: signal is "96,95,94,85,84,83,82,81";
	attribute pinnum of Tinp41: signal is "105,104,103,102,101,100,99,98";
	attribute pinnum of Tinp50: signal is "116,115,114,113,112,111,110,109";
	attribute pinnum of Tinp51: signal is "126,125,124,123,121,119,118,117";

	attribute pinnum of TSTB0: signal is "209";
	attribute pinnum of TSTB1: signal is "212";
	attribute pinnum of TSTB2: signal is "31";
	attribute pinnum of TSTB3: signal is "34";
	attribute pinnum of TSTB4: signal is "88";
	attribute pinnum of TSTB5: signal is "91";
	
	attribute pinnum of Mout: signal is "129,130,131,133,134,135,136,138";
	attribute pinnum of MSTB: signal is "143";
	
	attribute pinnum of HCLK: signal is "151";
	attribute pinnum of GEN: signal is "154";
	
	attribute pinnum of BCK_PAN: signal is "156";
	
	attribute pinnum of EVT_LED: signal is "157";
	attribute pinnum of VTO_LED: signal is "161";
	
	attribute pinnum of FCLR: signal is "160";
	attribute pinnum of PEN: signal is "163";
	
	attribute pinnum of LAM0: signal is "169,166,164";
	attribute pinnum of LAM1: signal is "172,171,170";

	end;

architecture behavior of L1trigger is

-- Auxiliary signals
--------------------------------------------
	signal PEN_TL0: std_logic;
	signal PEN_TL1: std_logic;
	signal PEN_TL2: std_logic;
	signal PEN_TL3: std_logic;
	signal PEN_TL4: std_logic;
	signal PEN_TL5: std_logic;
	signal PEN_TL6: std_logic;
	signal PEN_TL7: std_logic;
	signal PEN_TL8: std_logic;
	signal PEN_TL9: std_logic;

	signal CLR_TL0: std_logic;
	signal CLR_TL1: std_logic;
	signal CLR_TL2: std_logic;
	signal CLR_TL3: std_logic;
	signal CLR_TL4: std_logic;
	signal CLR_TL5: std_logic;
	signal CLR_TL6: std_logic;
	signal CLR_TL7: std_logic;
	signal CLR_TL8: std_logic;
	signal CLR_TL9: std_logic;
	
	signal TRHF_SYN: std_logic;
	signal TRHR_SYN: std_logic;
--------------------------------------------

-- H1 CT controls
--------------------------------------------
	signal Clock: std_logic;
	signal Sync: std_logic;

	signal L1Keep: std_logic;
	signal Gate: std_logic;
--------------------------------------------

-- Synchronization scheme
--------------------------------------------
	signal Eve_FT0: std_logic_vector(31 downto 0);
	signal Odd_FT0: std_logic_vector(31 downto 0);

	signal Eve_FT2: std_logic_vector(31 downto 0);
	signal Odd_FT2: std_logic_vector(31 downto 0);

	signal Basket: std_logic_vector(31 downto 0);
	signal Bucket: std_logic_vector(31 downto 0);

	signal TMP_CN0: natural range 0 to 1;
	signal TMP_DL0: natural range 0 to 1;

	signal TMP_CN2: natural range 0 to 1;
	signal TMP_DL2: natural range 0 to 1;

	signal CLR_Ev0: std_logic;
	signal CLR_Od0: std_logic;

	signal CLR_Ev2: std_logic;
	signal CLR_Od2: std_logic;
--------------------------------------------

-- Pipeline
--------------------------------------------

-- Data registers
--------------------------
	signal D00: std_logic_vector(31 downto 0);
	signal D01: std_logic_vector(31 downto 0);
	signal D02: std_logic_vector(31 downto 0);
	signal D03: std_logic_vector(31 downto 0);
	signal D04: std_logic_vector(31 downto 0);
	signal D05: std_logic_vector(31 downto 0);
	signal D06: std_logic_vector(31 downto 0);
	signal D07: std_logic_vector(31 downto 0);
	signal D08: std_logic_vector(31 downto 0);
	signal D09: std_logic_vector(31 downto 0);
	signal D10: std_logic_vector(31 downto 0);
	signal D11: std_logic_vector(31 downto 0);
	signal D12: std_logic_vector(31 downto 0);
	signal D13: std_logic_vector(31 downto 0);
	signal D14: std_logic_vector(31 downto 0);
	signal D15: std_logic_vector(31 downto 0);
	signal D16: std_logic_vector(31 downto 0);
	signal D17: std_logic_vector(31 downto 0);
	signal D18: std_logic_vector(31 downto 0);
	signal D19: std_logic_vector(31 downto 0);
	signal D20: std_logic_vector(31 downto 0);
	signal D21: std_logic_vector(31 downto 0);
	signal D22: std_logic_vector(31 downto 0);
	signal D23: std_logic_vector(31 downto 0);
	signal D24: std_logic_vector(31 downto 0);
	signal D25: std_logic_vector(31 downto 0);
--------------------------
	signal P00: std_logic_vector(31 downto 0);
	signal P01: std_logic_vector(31 downto 0);
	signal P02: std_logic_vector(31 downto 0);
	signal P03: std_logic_vector(31 downto 0);
	signal P04: std_logic_vector(31 downto 0);
	signal P05: std_logic_vector(31 downto 0);
	signal P06: std_logic_vector(31 downto 0);
	signal P07: std_logic_vector(31 downto 0);
	signal P08: std_logic_vector(31 downto 0);
	signal P09: std_logic_vector(31 downto 0);
	signal P10: std_logic_vector(31 downto 0);
	signal P11: std_logic_vector(31 downto 0);
	signal P12: std_logic_vector(31 downto 0);
	signal P13: std_logic_vector(31 downto 0);
	signal P14: std_logic_vector(31 downto 0);
	signal P15: std_logic_vector(31 downto 0);
	signal P16: std_logic_vector(31 downto 0);
	signal P17: std_logic_vector(31 downto 0);
	signal P18: std_logic_vector(31 downto 0);
	signal P19: std_logic_vector(31 downto 0);
	signal P20: std_logic_vector(31 downto 0);
	signal P21: std_logic_vector(31 downto 0);
	signal P22: std_logic_vector(31 downto 0);
	signal P23: std_logic_vector(31 downto 0);

-- Data buffers
--------------------------
	signal B00: std_logic_vector(31 downto 0);
	signal B01: std_logic_vector(31 downto 0);
	signal B02: std_logic_vector(31 downto 0);
	signal B03: std_logic_vector(31 downto 0);
	signal B04: std_logic_vector(31 downto 0);
	signal B05: std_logic_vector(31 downto 0);
	signal B06: std_logic_vector(31 downto 0);
	signal B07: std_logic_vector(31 downto 0);
	signal B08: std_logic_vector(31 downto 0);
	signal B09: std_logic_vector(31 downto 0);
	signal B10: std_logic_vector(31 downto 0);
	signal B11: std_logic_vector(31 downto 0);
	signal B12: std_logic_vector(31 downto 0);
	signal B13: std_logic_vector(31 downto 0);
	signal B14: std_logic_vector(31 downto 0);
	signal B15: std_logic_vector(31 downto 0);
	signal B16: std_logic_vector(31 downto 0);
	signal B17: std_logic_vector(31 downto 0);
	signal B18: std_logic_vector(31 downto 0);
	signal B19: std_logic_vector(31 downto 0);
	signal B20: std_logic_vector(31 downto 0);
	signal B21: std_logic_vector(31 downto 0);
	signal B22: std_logic_vector(31 downto 0);
	signal B23: std_logic_vector(31 downto 0);
	signal B24: std_logic_vector(31 downto 0);
--------------------------
	signal R00: std_logic_vector(31 downto 0);
	signal R01: std_logic_vector(31 downto 0);
	signal R02: std_logic_vector(31 downto 0);
	signal R03: std_logic_vector(31 downto 0);
	signal R04: std_logic_vector(31 downto 0);
	signal R05: std_logic_vector(31 downto 0);
	signal R06: std_logic_vector(31 downto 0);
	signal R07: std_logic_vector(31 downto 0);
	signal R08: std_logic_vector(31 downto 0);
	signal R09: std_logic_vector(31 downto 0);
	signal R10: std_logic_vector(31 downto 0);
	signal R11: std_logic_vector(31 downto 0);
	signal R12: std_logic_vector(31 downto 0);
	signal R13: std_logic_vector(31 downto 0);
	signal R14: std_logic_vector(31 downto 0);
	signal R15: std_logic_vector(31 downto 0);
	signal R16: std_logic_vector(31 downto 0);
	signal R17: std_logic_vector(31 downto 0);
	signal R18: std_logic_vector(31 downto 0);
	signal R19: std_logic_vector(31 downto 0);
	signal R20: std_logic_vector(31 downto 0);
	signal R21: std_logic_vector(31 downto 0);
	signal R22: std_logic_vector(31 downto 0);
--------------------------------------------

-- Data transmission
--------------------------------------------
	signal RDY_CNT: natural range 0 to 63;
	signal RDY_GTE: std_logic;

	signal RDS_CLR: std_logic_vector(0 downto 0);
	signal STB_EVE: std_logic;
	signal STB_ODD: std_logic;
--------------------------------------------

begin

-- Permanent statements
--------------------------------------------
	DLY_OUT <= HCLK;
--------------------------
	Mout <= (others => '0');
	MSTB <= '0';
--------------------------
	EVT_LED <= '0';
	VTO_LED <= '0';
	TXD <= '0';
--------------------------------------------

-- Reset telescope
--------------------------------------------
	process(DLY_TAP(0), FCLR)
	begin
		if (DLY_TAP(0)'event and DLY_TAP(0) = '1') then
			CLR_TL0 <= FCLR;
		end if;
	end process;
--------------------------
	process(DLY_TAP(1), CLR_TL0)
	begin
		if (DLY_TAP(1)'event and DLY_TAP(1) = '1') then
			CLR_TL1 <= CLR_TL0;
		end if;
	end process;
--------------------------
	process(DLY_TAP(2), CLR_TL1)
	begin
		if (DLY_TAP(2)'event and DLY_TAP(2) = '1') then
			CLR_TL2 <= CLR_TL1;
		end if;
	end process;
--------------------------
	process(DLY_TAP(3), CLR_TL2)
	begin
		if (DLY_TAP(3)'event and DLY_TAP(3) = '1') then
			CLR_TL3 <= CLR_TL2;
		end if;
	end process;
--------------------------
	process(DLY_TAP(4), CLR_TL3)
	begin
		if (DLY_TAP(4)'event and DLY_TAP(4) = '1') then
			CLR_TL4 <= CLR_TL3;
		end if;
	end process;
--------------------------
	process(DLY_TAP(5), CLR_TL4)
	begin
		if (DLY_TAP(5)'event and DLY_TAP(5) = '1') then
			CLR_TL5 <= CLR_TL4;
		end if;
	end process;
--------------------------
	process(DLY_TAP(6), CLR_TL5)
	begin
		if (DLY_TAP(6)'event and DLY_TAP(6) = '1') then
			CLR_TL6 <= CLR_TL5;
		end if;
	end process;
--------------------------
	process(DLY_TAP(7), CLR_TL6)
	begin
		if (DLY_TAP(7)'event and DLY_TAP(7) = '1') then
			CLR_TL7 <= CLR_TL6;
		end if;
	end process;
--------------------------
	process(DLY_TAP(8), CLR_TL7)
	begin
		if (DLY_TAP(8)'event and DLY_TAP(8) = '1') then
			CLR_TL8 <= CLR_TL7;
		end if;
	end process;
--------------------------
	process(DLY_TAP(9), CLR_TL8)
	begin
		if (DLY_TAP(9)'event and DLY_TAP(9) = '1') then
			CLR_TL9 <= CLR_TL8;
		end if;
	end process;
--------------------------------------------

-- "Pipeline enable" telescope
--------------------------------------------
	process(DLY_TAP(0), PEN)
	begin
		if (DLY_TAP(0)'event and DLY_TAP(0) = '1') then
			PEN_TL0 <= PEN;
		end if;
	end process;
--------------------------
	process(DLY_TAP(1), PEN_TL0)
	begin
		if (DLY_TAP(1)'event and DLY_TAP(1) = '1') then
			PEN_TL1 <= PEN_TL0;
		end if;
	end process;
--------------------------
	process(DLY_TAP(2), PEN_TL1)
	begin
		if (DLY_TAP(2)'event and DLY_TAP(2) = '1') then
			PEN_TL2 <= PEN_TL1;
		end if;
	end process;
--------------------------
	process(DLY_TAP(3), PEN_TL2)
	begin
		if (DLY_TAP(3)'event and DLY_TAP(3) = '1') then
			PEN_TL3 <= PEN_TL2;
		end if;
	end process;
--------------------------
	process(DLY_TAP(4), PEN_TL3)
	begin
		if (DLY_TAP(4)'event and DLY_TAP(4) = '1') then
			PEN_TL4 <= PEN_TL3;
		end if;
	end process;
--------------------------
	process(DLY_TAP(5), PEN_TL4)
	begin
		if (DLY_TAP(5)'event and DLY_TAP(5) = '1') then
			PEN_TL5 <= PEN_TL4;
		end if;
	end process;
--------------------------
	process(DLY_TAP(6), PEN_TL5)
	begin
		if (DLY_TAP(6)'event and DLY_TAP(6) = '1') then
			PEN_TL6 <= PEN_TL5;
		end if;
	end process;
--------------------------
	process(DLY_TAP(7), PEN_TL6)
	begin
		if (DLY_TAP(7)'event and DLY_TAP(7) = '1') then
			PEN_TL7 <= PEN_TL6;
		end if;
	end process;
--------------------------
	process(DLY_TAP(8), PEN_TL7)
	begin
		if (DLY_TAP(8)'event and DLY_TAP(8) = '1') then
			PEN_TL8 <= PEN_TL7;
		end if;
	end process;
--------------------------
	process(DLY_TAP(9), PEN_TL8)
	begin
		if (DLY_TAP(9)'event and DLY_TAP(9) = '1') then
			PEN_TL9 <= PEN_TL8;
		end if;
	end process;
--------------------------------------------

-- Phase adjustment for the H1 CT signal
--------------------------------------------
	process(MSTB_SW, DLY_TAP, HCLK,
			PEN_TL9, PEN_TL8, PEN_TL7, PEN_TL6,
			PEN_TL5, PEN_TL4, PEN_TL3, PEN_TL2,
			PEN_TL1, PEN_TL0, PEN,
			CLR_TL9, CLR_TL8, CLR_TL7, CLR_TL6,
			CLR_TL5, CLR_TL4, CLR_TL3, CLR_TL2,
			CLR_TL1, CLR_TL0, FCLR)
	begin
		case MSTB_SW is
			when "0110" =>
				Clock <= DLY_TAP(9);
				Sync <= DLY_TAP(0);
				TRHF_SYN <= PEN_TL9;
				TRHR_SYN <= CLR_TL9;
			when "0111" =>
				Clock <= DLY_TAP(8);
				Sync <= DLY_TAP(9);
				TRHF_SYN <= PEN_TL8;
				TRHR_SYN <= CLR_TL8;
			when "1000" =>
				Clock <= DLY_TAP(7);
				Sync <= DLY_TAP(8);
				TRHF_SYN <= PEN_TL7;
				TRHR_SYN <= CLR_TL7;
			when "1001" =>
				Clock <= DLY_TAP(6);
				Sync <= DLY_TAP(7);
				TRHF_SYN <= PEN_TL6;
				TRHR_SYN <= CLR_TL6;
			when "1010" =>
				Clock <= DLY_TAP(5);
				Sync <= DLY_TAP(6);
				TRHF_SYN <= PEN_TL5;
				TRHR_SYN <= CLR_TL5;
			when "1011" =>
				Clock <= DLY_TAP(4);
				Sync <= DLY_TAP(5);
				TRHF_SYN <= PEN_TL4;
				TRHR_SYN <= CLR_TL4;
			when "1100" =>
				Clock <= DLY_TAP(3);
				Sync <= DLY_TAP(4);
				TRHF_SYN <= PEN_TL3;
				TRHR_SYN <= CLR_TL3;
			when "1101" =>
				Clock <= DLY_TAP(2);
				Sync <= DLY_TAP(3);
				TRHF_SYN <= PEN_TL2;
				TRHR_SYN <= CLR_TL2;
			when "1110" =>
				Clock <= DLY_TAP(1);
				Sync <= DLY_TAP(2);
				TRHF_SYN <= PEN_TL1;
				TRHR_SYN <= CLR_TL1;
			when "1111" =>
				Clock <= DLY_TAP(0);
				Sync <= DLY_TAP(1);
				TRHF_SYN <= PEN_TL0;
				TRHR_SYN <= CLR_TL0;
			when others =>
				Clock <= HCLK;
				Sync <= HCLK;
				TRHF_SYN <= PEN;
				TRHR_SYN <= FCLR;
		end case;
	end process;
--------------------------------------------

-- Starting the "L1Keep" signal
--------------------------------------------
	process(TRHR_SYN, TRHF_SYN)
	begin
		if (TRHR_SYN = '1') then
			Gate <= '0';
		elsif (TRHF_SYN'event and TRHF_SYN = '0') then
			Gate <= '1';
		end if;
	end process;
--------------------------------------------

-- Finishing the "L1Keep" signal
--------------------------------------------
	process(Gate, TRHR_SYN)
	begin
		if (Gate = '1') then
			L1Keep <= '1';
		elsif (TRHR_SYN'event and TRHR_SYN = '0') then
			L1Keep <= '0';
		end if;
	end process;
--------------------------------------------

-- 32 latches for the FTI_0 input signals
-- (this idea doesn't work as a subroutine
-- and has to be written for every process
-- separately)
--------------------------

-- bit "0", even timeslice
--------------------------
	process(CLR_Ev0, Tinp00(0))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(0) <= '0';
		elsif (Tinp00(0)'event and Tinp00(0) = '0') then
			Eve_FT0(0) <= '1';
		end if;
	end process;
--------------------------

-- bit "0", odd timeslice
--------------------------
	process(CLR_Od0, Tinp00(0))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(0) <= '0';
		elsif (Tinp00(0)'event and Tinp00(0) = '0') then
			Odd_FT0(0) <= '1';
		end if;
	end process;
--------------------------

-- bit "1", even timeslice
--------------------------
	process(CLR_Ev0, Tinp00(1))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(1) <= '0';
		elsif (Tinp00(1)'event and Tinp00(1) = '0') then
			Eve_FT0(1) <= '1';
		end if;
	end process;
--------------------------

-- bit "1", odd timeslice
--------------------------
	process(CLR_Od0, Tinp00(1))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(1) <= '0';
		elsif (Tinp00(1)'event and Tinp00(1) = '0') then
			Odd_FT0(1) <= '1';
		end if;
	end process;
--------------------------

-- bit "2", even timeslice
--------------------------
	process(CLR_Ev0, Tinp00(2))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(2) <= '0';
		elsif (Tinp00(2)'event and Tinp00(2) = '0') then
			Eve_FT0(2) <= '1';
		end if;
	end process;
--------------------------

-- bit "2", odd timeslice
--------------------------
	process(CLR_Od0, Tinp00(2))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(2) <= '0';
		elsif (Tinp00(2)'event and Tinp00(2) = '0') then
			Odd_FT0(2) <= '1';
		end if;
	end process;
--------------------------

-- bit "3", even timeslice
--------------------------
	process(CLR_Ev0, Tinp00(3))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(3) <= '0';
		elsif (Tinp00(3)'event and Tinp00(3) = '0') then
			Eve_FT0(3) <= '1';
		end if;
	end process;
--------------------------

-- bit "3", odd timeslice
--------------------------
	process(CLR_Od0, Tinp00(3))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(3) <= '0';
		elsif (Tinp00(3)'event and Tinp00(3) = '0') then
			Odd_FT0(3) <= '1';
		end if;
	end process;
--------------------------

-- bit "4", even timeslice
--------------------------
	process(CLR_Ev0, Tinp00(4))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(4) <= '0';
		elsif (Tinp00(4)'event and Tinp00(4) = '0') then
			Eve_FT0(4) <= '1';
		end if;
	end process;
--------------------------

-- bit "4", odd timeslice
--------------------------
	process(CLR_Od0, Tinp00(4))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(4) <= '0';
		elsif (Tinp00(4)'event and Tinp00(4) = '0') then
			Odd_FT0(4) <= '1';
		end if;
	end process;
--------------------------

-- bit "5", even timeslice
--------------------------
	process(CLR_Ev0, Tinp00(5))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(5) <= '0';
		elsif (Tinp00(5)'event and Tinp00(5) = '0') then
			Eve_FT0(5) <= '1';
		end if;
	end process;
--------------------------

-- bit "5", odd timeslice
--------------------------
	process(CLR_Od0, Tinp00(5))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(5) <= '0';
		elsif (Tinp00(5)'event and Tinp00(5) = '0') then
			Odd_FT0(5) <= '1';
		end if;
	end process;
--------------------------

-- bit "6", even timeslice
--------------------------
	process(CLR_Ev0, Tinp00(6))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(6) <= '0';
		elsif (Tinp00(6)'event and Tinp00(6) = '0') then
			Eve_FT0(6) <= '1';
		end if;
	end process;
--------------------------

-- bit "6", odd timeslice
--------------------------
	process(CLR_Od0, Tinp00(6))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(6) <= '0';
		elsif (Tinp00(6)'event and Tinp00(6) = '0') then
			Odd_FT0(6) <= '1';
		end if;
	end process;
--------------------------

-- bit "7", even timeslice
--------------------------
	process(CLR_Ev0, Tinp00(7))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(7) <= '0';
		elsif (Tinp00(7)'event and Tinp00(7) = '0') then
			Eve_FT0(7) <= '1';
		end if;
	end process;
--------------------------

-- bit "7", odd timeslice
--------------------------
	process(CLR_Od0, Tinp00(7))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(7) <= '0';
		elsif (Tinp00(7)'event and Tinp00(7) = '0') then
			Odd_FT0(7) <= '1';
		end if;
	end process;
--------------------------

-- bit "8", even timeslice
--------------------------
	process(CLR_Ev0, Tinp01(0))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(8) <= '0';
		elsif (Tinp01(0)'event and Tinp01(0) = '0') then
			Eve_FT0(8) <= '1';
		end if;
	end process;
--------------------------

-- bit "8", odd timeslice
--------------------------
	process(CLR_Od0, Tinp01(0))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(8) <= '0';
		elsif (Tinp01(0)'event and Tinp01(0) = '0') then
			Odd_FT0(8) <= '1';
		end if;
	end process;
--------------------------

-- bit "9", even timeslice
--------------------------
	process(CLR_Ev0, Tinp01(1))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(9) <= '0';
		elsif (Tinp01(1)'event and Tinp01(1) = '0') then
			Eve_FT0(9) <= '1';
		end if;
	end process;
--------------------------

-- bit "9", odd timeslice
--------------------------
	process(CLR_Od0, Tinp01(1))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(9) <= '0';
		elsif (Tinp01(1)'event and Tinp01(1) = '0') then
			Odd_FT0(9) <= '1';
		end if;
	end process;
--------------------------

-- bit "10", even timeslice
--------------------------
	process(CLR_Ev0, Tinp01(2))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(10) <= '0';
		elsif (Tinp01(2)'event and Tinp01(2) = '0') then
			Eve_FT0(10) <= '1';
		end if;
	end process;
--------------------------

-- bit "10", odd timeslice
--------------------------
	process(CLR_Od0, Tinp01(2))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(10) <= '0';
		elsif (Tinp01(2)'event and Tinp01(2) = '0') then
			Odd_FT0(10) <= '1';
		end if;
	end process;
--------------------------

-- bit "11", even timeslice
--------------------------
	process(CLR_Ev0, Tinp01(3))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(11) <= '0';
		elsif (Tinp01(3)'event and Tinp01(3) = '0') then
			Eve_FT0(11) <= '1';
		end if;
	end process;
--------------------------

-- bit "11", odd timeslice
--------------------------
	process(CLR_Od0, Tinp01(3))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(11) <= '0';
		elsif (Tinp01(3)'event and Tinp01(3) = '0') then
			Odd_FT0(11) <= '1';
		end if;
	end process;
--------------------------

-- bit "12", even timeslice
--------------------------
	process(CLR_Ev0, Tinp01(4))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(12) <= '0';
		elsif (Tinp01(4)'event and Tinp01(4) = '0') then
			Eve_FT0(12) <= '1';
		end if;
	end process;
--------------------------

-- bit "12", odd timeslice
--------------------------
	process(CLR_Od0, Tinp01(4))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(12) <= '0';
		elsif (Tinp01(4)'event and Tinp01(4) = '0') then
			Odd_FT0(12) <= '1';
		end if;
	end process;
--------------------------

-- bit "13", even timeslice
--------------------------
	process(CLR_Ev0, Tinp01(5))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(13) <= '0';
		elsif (Tinp01(5)'event and Tinp01(5) = '0') then
			Eve_FT0(13) <= '1';
		end if;
	end process;
--------------------------

-- bit "13", odd timeslice
--------------------------
	process(CLR_Od0, Tinp01(5))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(13) <= '0';
		elsif (Tinp01(5)'event and Tinp01(5) = '0') then
			Odd_FT0(13) <= '1';
		end if;
	end process;
--------------------------

-- bit "14", even timeslice
--------------------------
	process(CLR_Ev0, Tinp01(6))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(14) <= '0';
		elsif (Tinp01(6)'event and Tinp01(6) = '0') then
			Eve_FT0(14) <= '1';
		end if;
	end process;
--------------------------

-- bit "14", odd timeslice
--------------------------
	process(CLR_Od0, Tinp01(6))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(14) <= '0';
		elsif (Tinp01(6)'event and Tinp01(6) = '0') then
			Odd_FT0(14) <= '1';
		end if;
	end process;
--------------------------

-- bit "15", even timeslice
--------------------------
	process(CLR_Ev0, Tinp01(7))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(15) <= '0';
		elsif (Tinp01(7)'event and Tinp01(7) = '0') then
			Eve_FT0(15) <= '1';
		end if;
	end process;
--------------------------

-- bit "15", odd timeslice
--------------------------
	process(CLR_Od0, Tinp01(7))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(15) <= '0';
		elsif (Tinp01(7)'event and Tinp01(7) = '0') then
			Odd_FT0(15) <= '1';
		end if;
	end process;
--------------------------

-- bit "16", even timeslice
--------------------------
	process(CLR_Ev0, Tinp20(0))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(16) <= '0';
		elsif (Tinp20(0)'event and Tinp20(0) = '0') then
			Eve_FT0(16) <= '1';
		end if;
	end process;
--------------------------

-- bit "16", odd timeslice
--------------------------
	process(CLR_Od0, Tinp20(0))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(16) <= '0';
		elsif (Tinp20(0)'event and Tinp20(0) = '0') then
			Odd_FT0(16) <= '1';
		end if;
	end process;
--------------------------

-- bit "17", even timeslice
--------------------------
	process(CLR_Ev0, Tinp20(1))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(17) <= '0';
		elsif (Tinp20(1)'event and Tinp20(1) = '0') then
			Eve_FT0(17) <= '1';
		end if;
	end process;
--------------------------

-- bit "17", odd timeslice
--------------------------
	process(CLR_Od0, Tinp20(1))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(17) <= '0';
		elsif (Tinp20(1)'event and Tinp20(1) = '0') then
			Odd_FT0(17) <= '1';
		end if;
	end process;
--------------------------

-- bit "18", even timeslice
--------------------------
	process(CLR_Ev0, Tinp20(2))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(18) <= '0';
		elsif (Tinp20(2)'event and Tinp20(2) = '0') then
			Eve_FT0(18) <= '1';
		end if;
	end process;
--------------------------

-- bit "18", odd timeslice
--------------------------
	process(CLR_Od0, Tinp20(2))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(18) <= '0';
		elsif (Tinp20(2)'event and Tinp20(2) = '0') then
			Odd_FT0(18) <= '1';
		end if;
	end process;
--------------------------

-- bit "19", even timeslice
--------------------------
	process(CLR_Ev0, Tinp20(3))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(19) <= '0';
		elsif (Tinp20(3)'event and Tinp20(3) = '0') then
			Eve_FT0(19) <= '1';
		end if;
	end process;
--------------------------

-- bit "19", odd timeslice
--------------------------
	process(CLR_Od0, Tinp20(3))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(19) <= '0';
		elsif (Tinp20(3)'event and Tinp20(3) = '0') then
			Odd_FT0(19) <= '1';
		end if;
	end process;
--------------------------

-- bit "20", even timeslice
--------------------------
	process(CLR_Ev0, Tinp20(4))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(20) <= '0';
		elsif (Tinp20(4)'event and Tinp20(4) = '0') then
			Eve_FT0(20) <= '1';
		end if;
	end process;
--------------------------

-- bit "20", odd timeslice
--------------------------
	process(CLR_Od0, Tinp20(4))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(20) <= '0';
		elsif (Tinp20(4)'event and Tinp20(4) = '0') then
			Odd_FT0(20) <= '1';
		end if;
	end process;
--------------------------

-- bit "21", even timeslice
--------------------------
	process(CLR_Ev0, Tinp20(5))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(21) <= '0';
		elsif (Tinp20(5)'event and Tinp20(5) = '0') then
			Eve_FT0(21) <= '1';
		end if;
	end process;
--------------------------

-- bit "21", odd timeslice
--------------------------
	process(CLR_Od0, Tinp20(5))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(21) <= '0';
		elsif (Tinp20(5)'event and Tinp20(5) = '0') then
			Odd_FT0(21) <= '1';
		end if;
	end process;
--------------------------

-- bit "22", even timeslice
--------------------------
	process(CLR_Ev0, Tinp20(6))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(22) <= '0';
		elsif (Tinp20(6)'event and Tinp20(6) = '0') then
			Eve_FT0(22) <= '1';
		end if;
	end process;
--------------------------

-- bit "22", odd timeslice
--------------------------
	process(CLR_Od0, Tinp20(6))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(22) <= '0';
		elsif (Tinp20(6)'event and Tinp20(6) = '0') then
			Odd_FT0(22) <= '1';
		end if;
	end process;
--------------------------

-- bit "23", even timeslice
--------------------------
	process(CLR_Ev0, Tinp20(7))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(23) <= '0';
		elsif (Tinp20(7)'event and Tinp20(7) = '0') then
			Eve_FT0(23) <= '1';
		end if;
	end process;
--------------------------

-- bit "23", odd timeslice
--------------------------
	process(CLR_Od0, Tinp20(7))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(23) <= '0';
		elsif (Tinp20(7)'event and Tinp20(7) = '0') then
			Odd_FT0(23) <= '1';
		end if;
	end process;
--------------------------

-- bit "24", even timeslice
--------------------------
	process(CLR_Ev0, Tinp21(0))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(24) <= '0';
		elsif (Tinp21(0)'event and Tinp21(0) = '0') then
			Eve_FT0(24) <= '1';
		end if;
	end process;
--------------------------

-- bit "24", odd timeslice
--------------------------
	process(CLR_Od0, Tinp21(0))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(24) <= '0';
		elsif (Tinp21(0)'event and Tinp21(0) = '0') then
			Odd_FT0(24) <= '1';
		end if;
	end process;
--------------------------

-- bit "25", even timeslice
--------------------------
	process(CLR_Ev0, Tinp21(1))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(25) <= '0';
		elsif (Tinp21(1)'event and Tinp21(1) = '0') then
			Eve_FT0(25) <= '1';
		end if;
	end process;
--------------------------

-- bit "25", odd timeslice
--------------------------
	process(CLR_Od0, Tinp21(1))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(25) <= '0';
		elsif (Tinp21(1)'event and Tinp21(1) = '0') then
			Odd_FT0(25) <= '1';
		end if;
	end process;
--------------------------

-- bit "26", even timeslice
--------------------------
	process(CLR_Ev0, Tinp21(2))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(26) <= '0';
		elsif (Tinp21(2)'event and Tinp21(2) = '0') then
			Eve_FT0(26) <= '1';
		end if;
	end process;
--------------------------

-- bit "26", odd timeslice
--------------------------
	process(CLR_Od0, Tinp21(2))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(26) <= '0';
		elsif (Tinp21(2)'event and Tinp21(2) = '0') then
			Odd_FT0(26) <= '1';
		end if;
	end process;
--------------------------

-- bit "27", even timeslice
--------------------------
	process(CLR_Ev0, Tinp21(3))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(27) <= '0';
		elsif (Tinp21(3)'event and Tinp21(3) = '0') then
			Eve_FT0(27) <= '1';
		end if;
	end process;
--------------------------

-- bit "27", odd timeslice
--------------------------
	process(CLR_Od0, Tinp21(3))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(27) <= '0';
		elsif (Tinp21(3)'event and Tinp21(3) = '0') then
			Odd_FT0(27) <= '1';
		end if;
	end process;
--------------------------

-- bit "28", even timeslice
--------------------------
	process(CLR_Ev0, Tinp21(4))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(28) <= '0';
		elsif (Tinp21(4)'event and Tinp21(4) = '0') then
			Eve_FT0(28) <= '1';
		end if;
	end process;
--------------------------

-- bit "28", odd timeslice
--------------------------
	process(CLR_Od0, Tinp21(4))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(28) <= '0';
		elsif (Tinp21(4)'event and Tinp21(4) = '0') then
			Odd_FT0(28) <= '1';
		end if;
	end process;
--------------------------

-- bit "29", even timeslice
--------------------------
	process(CLR_Ev0, Tinp21(5))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(29) <= '0';
		elsif (Tinp21(5)'event and Tinp21(5) = '0') then
			Eve_FT0(29) <= '1';
		end if;
	end process;
--------------------------

-- bit "29", odd timeslice
--------------------------
	process(CLR_Od0, Tinp21(5))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(29) <= '0';
		elsif (Tinp21(5)'event and Tinp21(5) = '0') then
			Odd_FT0(29) <= '1';
		end if;
	end process;
--------------------------

-- bit "30", even timeslice
--------------------------
	process(CLR_Ev0, Tinp21(6))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(30) <= '0';
		elsif (Tinp21(6)'event and Tinp21(6) = '0') then
			Eve_FT0(30) <= '1';
		end if;
	end process;
--------------------------

-- bit "30", odd timeslice
--------------------------
	process(CLR_Od0, Tinp21(6))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(30) <= '0';
		elsif (Tinp21(6)'event and Tinp21(6) = '0') then
			Odd_FT0(30) <= '1';
		end if;
	end process;
--------------------------

-- bit "31", even timeslice
--------------------------
	process(CLR_Ev0, Tinp21(7))
	begin
		if (CLR_Ev0 = '1') then
			Eve_FT0(31) <= '0';
		elsif (Tinp21(7)'event and Tinp21(7) = '0') then
			Eve_FT0(31) <= '1';
		end if;
	end process;
--------------------------

-- bit "31", odd timeslice
--------------------------
	process(CLR_Od0, Tinp21(7))
	begin
		if (CLR_Od0 = '1') then
			Odd_FT0(31) <= '0';
		elsif (Tinp21(7)'event and Tinp21(7) = '0') then
			Odd_FT0(31) <= '1';
		end if;
	end process;
--------------------------------------------

-- 32 latches for the FTI_2 input signals
--------------------------

-- bit "0", even timeslice
--------------------------
	process(CLR_EV2, Tinp10(0))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(0) <= '0';
		elsif (Tinp10(0)'event and Tinp10(0) = '0') then
			Eve_FT2(0) <= '1';
		end if;
	end process;
--------------------------

-- bit "0", odd timeslice
--------------------------
	process(CLR_OD2, Tinp10(0))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(0) <= '0';
		elsif (Tinp10(0)'event and Tinp10(0) = '0') then
			Odd_FT2(0) <= '1';
		end if;
	end process;
--------------------------

-- bit "1", even timeslice
--------------------------
	process(CLR_EV2, Tinp10(1))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(1) <= '0';
		elsif (Tinp10(1)'event and Tinp10(1) = '0') then
			Eve_FT2(1) <= '1';
		end if;
	end process;
--------------------------

-- bit "1", odd timeslice
--------------------------
	process(CLR_OD2, Tinp10(1))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(1) <= '0';
		elsif (Tinp10(1)'event and Tinp10(1) = '0') then
			Odd_FT2(1) <= '1';
		end if;
	end process;
--------------------------

-- bit "2", even timeslice
--------------------------
	process(CLR_EV2, Tinp10(2))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(2) <= '0';
		elsif (Tinp10(2)'event and Tinp10(2) = '0') then
			Eve_FT2(2) <= '1';
		end if;
	end process;
--------------------------

-- bit "2", odd timeslice
--------------------------
	process(CLR_OD2, Tinp10(2))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(2) <= '0';
		elsif (Tinp10(2)'event and Tinp10(2) = '0') then
			Odd_FT2(2) <= '1';
		end if;
	end process;
--------------------------

-- bit "3", even timeslice
--------------------------
	process(CLR_EV2, Tinp10(3))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(3) <= '0';
		elsif (Tinp10(3)'event and Tinp10(3) = '0') then
			Eve_FT2(3) <= '1';
		end if;
	end process;
--------------------------

-- bit "3", odd timeslice
--------------------------
	process(CLR_OD2, Tinp10(3))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(3) <= '0';
		elsif (Tinp10(3)'event and Tinp10(3) = '0') then
			Odd_FT2(3) <= '1';
		end if;
	end process;
--------------------------

-- bit "4", even timeslice
--------------------------
	process(CLR_EV2, Tinp10(4))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(4) <= '0';
		elsif (Tinp10(4)'event and Tinp10(4) = '0') then
			Eve_FT2(4) <= '1';
		end if;
	end process;
--------------------------

-- bit "4", odd timeslice
--------------------------
	process(CLR_OD2, Tinp10(4))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(4) <= '0';
		elsif (Tinp10(4)'event and Tinp10(4) = '0') then
			Odd_FT2(4) <= '1';
		end if;
	end process;
--------------------------

-- bit "5", even timeslice
--------------------------
	process(CLR_EV2, Tinp10(5))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(5) <= '0';
		elsif (Tinp10(5)'event and Tinp10(5) = '0') then
			Eve_FT2(5) <= '1';
		end if;
	end process;
--------------------------

-- bit "5", odd timeslice
--------------------------
	process(CLR_OD2, Tinp10(5))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(5) <= '0';
		elsif (Tinp10(5)'event and Tinp10(5) = '0') then
			Odd_FT2(5) <= '1';
		end if;
	end process;
--------------------------

-- bit "6", even timeslice
--------------------------
	process(CLR_EV2, Tinp10(6))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(6) <= '0';
		elsif (Tinp10(6)'event and Tinp10(6) = '0') then
			Eve_FT2(6) <= '1';
		end if;
	end process;
--------------------------

-- bit "6", odd timeslice
--------------------------
	process(CLR_OD2, Tinp10(6))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(6) <= '0';
		elsif (Tinp10(6)'event and Tinp10(6) = '0') then
			Odd_FT2(6) <= '1';
		end if;
	end process;
--------------------------

-- bit "7", even timeslice
--------------------------
	process(CLR_EV2, Tinp10(7))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(7) <= '0';
		elsif (Tinp10(7)'event and Tinp10(7) = '0') then
			Eve_FT2(7) <= '1';
		end if;
	end process;
--------------------------

-- bit "7", odd timeslice
--------------------------
	process(CLR_OD2, Tinp10(7))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(7) <= '0';
		elsif (Tinp10(7)'event and Tinp10(7) = '0') then
			Odd_FT2(7) <= '1';
		end if;
	end process;
--------------------------

-- bit "8", even timeslice
--------------------------
	process(CLR_EV2, Tinp11(0))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(8) <= '0';
		elsif (Tinp11(0)'event and Tinp11(0) = '0') then
			Eve_FT2(8) <= '1';
		end if;
	end process;
--------------------------

-- bit "8", odd timeslice
--------------------------
	process(CLR_OD2, Tinp11(0))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(8) <= '0';
		elsif (Tinp11(0)'event and Tinp11(0) = '0') then
			Odd_FT2(8) <= '1';
		end if;
	end process;
--------------------------

-- bit "9", even timeslice
--------------------------
	process(CLR_EV2, Tinp11(1))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(9) <= '0';
		elsif (Tinp11(1)'event and Tinp11(1) = '0') then
			Eve_FT2(9) <= '1';
		end if;
	end process;
--------------------------

-- bit "9", odd timeslice
--------------------------
	process(CLR_OD2, Tinp11(1))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(9) <= '0';
		elsif (Tinp11(1)'event and Tinp11(1) = '0') then
			Odd_FT2(9) <= '1';
		end if;
	end process;
--------------------------

-- bit "10", even timeslice
--------------------------
	process(CLR_EV2, Tinp11(2))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(10) <= '0';
		elsif (Tinp11(2)'event and Tinp11(2) = '0') then
			Eve_FT2(10) <= '1';
		end if;
	end process;
--------------------------

-- bit "10", odd timeslice
--------------------------
	process(CLR_OD2, Tinp11(2))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(10) <= '0';
		elsif (Tinp11(2)'event and Tinp11(2) = '0') then
			Odd_FT2(10) <= '1';
		end if;
	end process;
--------------------------

-- bit "11", even timeslice
--------------------------
	process(CLR_EV2, Tinp11(3))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(11) <= '0';
		elsif (Tinp11(3)'event and Tinp11(3) = '0') then
			Eve_FT2(11) <= '1';
		end if;
	end process;
--------------------------

-- bit "11", odd timeslice
--------------------------
	process(CLR_OD2, Tinp11(3))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(11) <= '0';
		elsif (Tinp11(3)'event and Tinp11(3) = '0') then
			Odd_FT2(11) <= '1';
		end if;
	end process;
--------------------------

-- bit "12", even timeslice
--------------------------
	process(CLR_EV2, Tinp11(4))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(12) <= '0';
		elsif (Tinp11(4)'event and Tinp11(4) = '0') then
			Eve_FT2(12) <= '1';
		end if;
	end process;
--------------------------

-- bit "12", odd timeslice
--------------------------
	process(CLR_OD2, Tinp11(4))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(12) <= '0';
		elsif (Tinp11(4)'event and Tinp11(4) = '0') then
			Odd_FT2(12) <= '1';
		end if;
	end process;
--------------------------

-- bit "13", even timeslice
--------------------------
	process(CLR_EV2, Tinp11(5))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(13) <= '0';
		elsif (Tinp11(5)'event and Tinp11(5) = '0') then
			Eve_FT2(13) <= '1';
		end if;
	end process;
--------------------------

-- bit "13", odd timeslice
--------------------------
	process(CLR_OD2, Tinp11(5))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(13) <= '0';
		elsif (Tinp11(5)'event and Tinp11(5) = '0') then
			Odd_FT2(13) <= '1';
		end if;
	end process;
--------------------------

-- bit "14", even timeslice
--------------------------
	process(CLR_EV2, Tinp11(6))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(14) <= '0';
		elsif (Tinp11(6)'event and Tinp11(6) = '0') then
			Eve_FT2(14) <= '1';
		end if;
	end process;
--------------------------

-- bit "14", odd timeslice
--------------------------
	process(CLR_OD2, Tinp11(6))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(14) <= '0';
		elsif (Tinp11(6)'event and Tinp11(6) = '0') then
			Odd_FT2(14) <= '1';
		end if;
	end process;
--------------------------

-- bit "15", even timeslice
--------------------------
	process(CLR_EV2, Tinp11(7))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(15) <= '0';
		elsif (Tinp11(7)'event and Tinp11(7) = '0') then
			Eve_FT2(15) <= '1';
		end if;
	end process;
--------------------------

-- bit "15", odd timeslice
--------------------------
	process(CLR_OD2, Tinp11(7))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(15) <= '0';
		elsif (Tinp11(7)'event and Tinp11(7) = '0') then
			Odd_FT2(15) <= '1';
		end if;
	end process;
--------------------------

-- bit "16", even timeslice
--------------------------
	process(CLR_EV2, Tinp30(0))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(16) <= '0';
		elsif (Tinp30(0)'event and Tinp30(0) = '0') then
			Eve_FT2(16) <= '1';
		end if;
	end process;
--------------------------

-- bit "16", odd timeslice
--------------------------
	process(CLR_OD2, Tinp30(0))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(16) <= '0';
		elsif (Tinp30(0)'event and Tinp30(0) = '0') then
			Odd_FT2(16) <= '1';
		end if;
	end process;
--------------------------

-- bit "17", even timeslice
--------------------------
	process(CLR_EV2, Tinp30(1))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(17) <= '0';
		elsif (Tinp30(1)'event and Tinp30(1) = '0') then
			Eve_FT2(17) <= '1';
		end if;
	end process;
--------------------------

-- bit "17", odd timeslice
--------------------------
	process(CLR_OD2, Tinp30(1))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(17) <= '0';
		elsif (Tinp30(1)'event and Tinp30(1) = '0') then
			Odd_FT2(17) <= '1';
		end if;
	end process;
--------------------------

-- bit "18", even timeslice
--------------------------
	process(CLR_EV2, Tinp30(2))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(18) <= '0';
		elsif (Tinp30(2)'event and Tinp30(2) = '0') then
			Eve_FT2(18) <= '1';
		end if;
	end process;
--------------------------

-- bit "18", odd timeslice
--------------------------
	process(CLR_OD2, Tinp30(2))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(18) <= '0';
		elsif (Tinp30(2)'event and Tinp30(2) = '0') then
			Odd_FT2(18) <= '1';
		end if;
	end process;
--------------------------

-- bit "19", even timeslice
--------------------------
	process(CLR_EV2, Tinp30(3))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(19) <= '0';
		elsif (Tinp30(3)'event and Tinp30(3) = '0') then
			Eve_FT2(19) <= '1';
		end if;
	end process;
--------------------------

-- bit "19", odd timeslice
--------------------------
	process(CLR_OD2, Tinp30(3))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(19) <= '0';
		elsif (Tinp30(3)'event and Tinp30(3) = '0') then
			Odd_FT2(19) <= '1';
		end if;
	end process;
--------------------------

-- bit "20", even timeslice
--------------------------
	process(CLR_EV2, Tinp30(4))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(20) <= '0';
		elsif (Tinp30(4)'event and Tinp30(4) = '0') then
			Eve_FT2(20) <= '1';
		end if;
	end process;
--------------------------

-- bit "20", odd timeslice
--------------------------
	process(CLR_OD2, Tinp30(4))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(20) <= '0';
		elsif (Tinp30(4)'event and Tinp30(4) = '0') then
			Odd_FT2(20) <= '1';
		end if;
	end process;
--------------------------

-- bit "21", even timeslice
--------------------------
	process(CLR_EV2, Tinp30(5))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(21) <= '0';
		elsif (Tinp30(5)'event and Tinp30(5) = '0') then
			Eve_FT2(21) <= '1';
		end if;
	end process;
--------------------------

-- bit "21", odd timeslice
--------------------------
	process(CLR_OD2, Tinp30(5))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(21) <= '0';
		elsif (Tinp30(5)'event and Tinp30(5) = '0') then
			Odd_FT2(21) <= '1';
		end if;
	end process;
--------------------------

-- bit "22", even timeslice
--------------------------
	process(CLR_EV2, Tinp30(6))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(22) <= '0';
		elsif (Tinp30(6)'event and Tinp30(6) = '0') then
			Eve_FT2(22) <= '1';
		end if;
	end process;
--------------------------

-- bit "22", odd timeslice
--------------------------
	process(CLR_OD2, Tinp30(6))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(22) <= '0';
		elsif (Tinp30(6)'event and Tinp30(6) = '0') then
			Odd_FT2(22) <= '1';
		end if;
	end process;
--------------------------

-- bit "23", even timeslice
--------------------------
	process(CLR_EV2, Tinp30(7))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(23) <= '0';
		elsif (Tinp30(7)'event and Tinp30(7) = '0') then
			Eve_FT2(23) <= '1';
		end if;
	end process;
--------------------------

-- bit "23", odd timeslice
--------------------------
	process(CLR_OD2, Tinp30(7))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(23) <= '0';
		elsif (Tinp30(7)'event and Tinp30(7) = '0') then
			Odd_FT2(23) <= '1';
		end if;
	end process;
--------------------------

-- bit "24", even timeslice
--------------------------
	process(CLR_EV2, Tinp31(0))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(24) <= '0';
		elsif (Tinp31(0)'event and Tinp31(0) = '0') then
			Eve_FT2(24) <= '1';
		end if;
	end process;
--------------------------

-- bit "24", odd timeslice
--------------------------
	process(CLR_OD2, Tinp31(0))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(24) <= '0';
		elsif (Tinp31(0)'event and Tinp31(0) = '0') then
			Odd_FT2(24) <= '1';
		end if;
	end process;
--------------------------

-- bit "25", even timeslice
--------------------------
	process(CLR_EV2, Tinp31(1))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(25) <= '0';
		elsif (Tinp31(1)'event and Tinp31(1) = '0') then
			Eve_FT2(25) <= '1';
		end if;
	end process;
--------------------------

-- bit "25", odd timeslice
--------------------------
	process(CLR_OD2, Tinp31(1))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(25) <= '0';
		elsif (Tinp31(1)'event and Tinp31(1) = '0') then
			Odd_FT2(25) <= '1';
		end if;
	end process;
--------------------------

-- bit "26", even timeslice
--------------------------
	process(CLR_EV2, Tinp31(2))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(26) <= '0';
		elsif (Tinp31(2)'event and Tinp31(2) = '0') then
			Eve_FT2(26) <= '1';
		end if;
	end process;
--------------------------

-- bit "26", odd timeslice
--------------------------
	process(CLR_OD2, Tinp31(2))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(26) <= '0';
		elsif (Tinp31(2)'event and Tinp31(2) = '0') then
			Odd_FT2(26) <= '1';
		end if;
	end process;
--------------------------

-- bit "27", even timeslice
--------------------------
	process(CLR_EV2, Tinp31(3))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(27) <= '0';
		elsif (Tinp31(3)'event and Tinp31(3) = '0') then
			Eve_FT2(27) <= '1';
		end if;
	end process;
--------------------------

-- bit "27", odd timeslice
--------------------------
	process(CLR_OD2, Tinp31(3))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(27) <= '0';
		elsif (Tinp31(3)'event and Tinp31(3) = '0') then
			Odd_FT2(27) <= '1';
		end if;
	end process;
--------------------------

-- bit "28", even timeslice
--------------------------
	process(CLR_EV2, Tinp31(4))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(28) <= '0';
		elsif (Tinp31(4)'event and Tinp31(4) = '0') then
			Eve_FT2(28) <= '1';
		end if;
	end process;
--------------------------

-- bit "28", odd timeslice
--------------------------
	process(CLR_OD2, Tinp31(4))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(28) <= '0';
		elsif (Tinp31(4)'event and Tinp31(4) = '0') then
			Odd_FT2(28) <= '1';
		end if;
	end process;
--------------------------

-- bit "29", even timeslice
--------------------------
	process(CLR_EV2, Tinp31(5))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(29) <= '0';
		elsif (Tinp31(5)'event and Tinp31(5) = '0') then
			Eve_FT2(29) <= '1';
		end if;
	end process;
--------------------------

-- bit "29", odd timeslice
--------------------------
	process(CLR_OD2, Tinp31(5))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(29) <= '0';
		elsif (Tinp31(5)'event and Tinp31(5) = '0') then
			Odd_FT2(29) <= '1';
		end if;
	end process;
--------------------------

-- bit "30", even timeslice
--------------------------
	process(CLR_EV2, Tinp31(6))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(30) <= '0';
		elsif (Tinp31(6)'event and Tinp31(6) = '0') then
			Eve_FT2(30) <= '1';
		end if;
	end process;
--------------------------

-- bit "30", odd timeslice
--------------------------
	process(CLR_OD2, Tinp31(6))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(30) <= '0';
		elsif (Tinp31(6)'event and Tinp31(6) = '0') then
			Odd_FT2(30) <= '1';
		end if;
	end process;
--------------------------

-- bit "31", even timeslice
--------------------------
	process(CLR_EV2, Tinp31(7))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(31) <= '0';
		elsif (Tinp31(7)'event and Tinp31(7) = '0') then
			Eve_FT2(31) <= '1';
		end if;
	end process;
--------------------------

-- bit "31", odd timeslice
--------------------------
	process(CLR_OD2, Tinp31(7))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(31) <= '0';
		elsif (Tinp31(7)'event and Tinp31(7) = '0') then
			Odd_FT2(31) <= '1';
		end if;
	end process;
--------------------------------------------

-- Time slice counter (Clock <-)
--------------------------------------------
	process(Clock)
	begin
		if (Clock'event and Clock = '0') then
			TMP_CN0 <= TMP_CN0 + 1;
		end if;
	end process;
--------------------------
	process(Clock, TMP_CN0)
	begin
		if (Clock'event and Clock ='1') then
			TMP_DL0 <= TMP_CN0;
		end if;
	end process;
--------------------------
--------------------------
	process(Sync)
	begin
		if (Sync'event and Sync = '0') then
			TMP_CN2 <= TMP_CN2 + 1;
		end if;
	end process;
--------------------------
	process(Sync, TMP_CN2)
	begin
		if (Sync'event and Sync ='1') then
			TMP_DL2 <= TMP_CN2;
		end if;
	end process;
--------------------------------------------

-- Merge FTI_0 data from the even
-- and odd clock periods (Clock ->)
--------------------------------------------
	process(Clock, TMP_CN0, Eve_FT0, Odd_FT0)
	begin
		if (Clock'event and Clock = '1') then
			if (TMP_CN0 = 1) then
				Basket <= Eve_FT0;
			else
				Basket <= Odd_FT0;
			end if;
		end if;
	end process;
--------------------------------------------

-- Merge FTI_2 data from the even
-- and odd clock periods (Sync ->)
--------------------------------------------
	process(Sync, TMP_CN2, Eve_FT2, Odd_FT2)
	begin
		if (Sync'event and Sync = '1') then
			if (TMP_CN2 = 1) then
				Bucket <= Eve_FT2;
			else
				Bucket <= Odd_FT2;
			end if;
		end if;
	end process;
--------------------------------------------

-- Clear even time slice (Clock <-)
--------------------------------------------
	process(TMP_DL0, Clock)
	begin
		if (TMP_DL0 = 0) then
			CLR_Ev0 <= '0';
		elsif (Clock'event and Clock = '0') then
			CLR_Ev0 <= '1';
		end if;
	end process;
--------------------------------------------

-- Clear odd time slice (Clock <-)
--------------------------------------------
	process(TMP_DL0, Clock)
	begin
		if (TMP_DL0 = 1) then
			CLR_Od0 <= '0';
		elsif (Clock'event and Clock = '0') then
			CLR_Od0 <= '1';
		end if;
	end process;
--------------------------------------------

-- Clear even time slice (Sync <-)
--------------------------------------------
	process(TMP_DL2, Sync)
	begin
		if (TMP_DL2 = 0) then
			CLR_Ev2 <= '0';
		elsif (Sync'event and Sync = '0') then
			CLR_Ev2 <= '1';
		end if;
	end process;
--------------------------------------------

-- Clear odd time slice (Sync <-)
--------------------------------------------
	process(TMP_DL2, Sync)
	begin
		if (TMP_DL2 = 1) then
			CLR_Od2 <= '0';
		elsif (Sync'event and Sync = '0') then
			CLR_Od2 <= '1';
		end if;
	end process;
--------------------------------------------

-- Latch the raw data (Clock <-)
--------------------------------------------
	process(Clock, L1Keep,
			Basket,
			B00, B01, B02, B03, B04, B05,
			B06, B07, B08, B09, B10, B11,
			B12, B13, B14, B15, B16, B17,
			B18, B19, B20, B21, B22, B23,
			B24, Bucket,
			R00, R01, R02, R03, R04, R05,
			R06, R07, R08, R09, R10, R11,
			R12, R13, R14, R15, R16, R17,
			R18, R19, R20, R21, R22)
	begin
		if (Clock'event and Clock = '0') then
			if (L1Keep = '0') then
				D00 <= Basket;
				D01 <= B00;
				D02 <= B01;
				D03 <= B02;
				D04 <= B03;
				D05 <= B04;
				D06 <= B05;
				D07 <= B06;
				D08 <= B07;
				D09 <= B08;
				D10 <= B09;
				D11 <= B10;
				D12 <= B11;
				D13 <= B12;
				D14 <= B13;
				D15 <= B14;
				D16 <= B15;
				D17 <= B16;
				D18 <= B17;
				D19 <= B18;
				D20 <= B19;
				D21 <= B20;
				D22 <= B21;
				D23 <= B22;
				D24 <= B23;
				D25 <= B24;

				P00 <= Bucket;
				P01 <= R00;
				P02 <= R01;
				P03 <= R02;
				P04 <= R03;
				P05 <= R04;
				P06 <= R05;
				P07 <= R06;
				P08 <= R07;
				P09 <= R08;
				P10 <= R09;
				P11 <= R10;
				P12 <= R11;
				P13 <= R12;
				P14 <= R13;
				P15 <= R14;
				P16 <= R15;
				P17 <= R16;
				P18 <= R17;
				P19 <= R18;
				P20 <= R19;
				P21 <= R20;
				P22 <= R21;
				P23 <= R22;
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Buffer the raw data (Clock ->)
--------------------------------------------
	process(Clock,
			D00, D01, D02, D03, D04, D05,
			D06, D07, D08, D09, D10, D11,
			D12, D13, D14, D15, D16, D17,
			D18, D19, D20, D21, D22, D23,
			D24,
			P00, P01, P02, P03, P04, P05,
			P06, P07, P08, P09, P10, P11,
			P12, P13, P14, P15, P16, P17,
			P18, P19, P20, P21, P22)
	begin
		if (Clock'event and Clock = '1') then
			B00 <= D00;
			B01 <= D01;
			B02 <= D02;
			B03 <= D03;
			B04 <= D04;
			B05 <= D05;
			B06 <= D06;
			B07 <= D07;
			B08 <= D08;
			B09 <= D09;
			B10 <= D10;
			B11 <= D11;
			B12 <= D12;
			B13 <= D13;
			B14 <= D14;
			B15 <= D15;
			B16 <= D16;
			B17 <= D17;
			B18 <= D18;
			B19 <= D19;
			B20 <= D20;
			B21 <= D21;
			B22 <= D22;
			B23 <= D23;
			B24 <= D24;

			R00 <= P00;
			R01 <= P01;
			R02 <= P02;
			R03 <= P03;
			R04 <= P04;
			R05 <= P05;
			R06 <= P06;
			R07 <= P07;
			R08 <= P08;
			R09 <= P09;
			R10 <= P10;
			R11 <= P11;
			R12 <= P12;
			R13 <= P13;
			R14 <= P14;
			R15 <= P15;
			R16 <= P16;
			R17 <= P17;
			R18 <= P18;
			R19 <= P19;
			R20 <= P20;
			R21 <= P21;
			R22 <= P22;
		end if;
	end process;
--------------------------------------------

-- Gate for the readout counter (Clock ->)
--------------------------------------------
	process(Clock, RDY_CNT)
	begin
		if (Clock'event and Clock = '1') then
			if (RDY_CNT = 41) then
				RDY_GTE <= '0';
			else
				RDY_GTE <= '1';
			end if;
		end if;
	end process;
--------------------------------------------

-- Readout counter (Clock <-)
--------------------------------------------
	process(Clock, L1Keep, RDY_GTE)
	begin
		if (Clock'event and Clock = '0') then
			if (L1Keep = '0') then
				RDY_CNT <= 0;
         	elsif (RDY_GTE = '1') then
				RDY_CNT <= RDY_CNT + 1;
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Transmit the raw data to ACEX
--------------------------------------------
	process(RDY_CNT, D25, D24, D23, D22, D21,
					 P23, P22, P21, P20, P19)
	begin
		case RDY_CNT is
			when 1 =>
				Rdata <= D25(31 downto 24);
			when 2 =>
				Rdata <= D25(23 downto 16);
			when 3 =>
				Rdata <= D25(15 downto 8);
			when 4 =>
				Rdata <= D25(7 downto 0);
			when 5 =>
				Rdata <= D24(31 downto 24);
			when 6 =>
				Rdata <= D24(23 downto 16);
			when 7 =>
				Rdata <= D24(15 downto 8);
			when 8 =>
				Rdata <= D24(7 downto 0);
			when 9 =>
				Rdata <= D23(31 downto 24);
			when 10 =>
				Rdata <= D23(23 downto 16);
			when 11 =>
				Rdata <= D23(15 downto 8);
			when 12 =>
				Rdata <= D23(7 downto 0);
			when 13 =>
				Rdata <= D22(31 downto 24);
			when 14 =>
				Rdata <= D22(23 downto 16);
			when 15 =>
				Rdata <= D22(15 downto 8);
			when 16 =>
				Rdata <= D22(7 downto 0);
			when 17 =>
				Rdata <= D21(31 downto 24);
			when 18 =>
				Rdata <= D21(23 downto 16);
			when 19 =>
				Rdata <= D21(15 downto 8);
			when 20 =>
				Rdata <= D21(7 downto 0);

			when 21 =>
				Rdata <= P23(31 downto 24);
			when 22 =>
				Rdata <= P23(23 downto 16);
			when 23 =>
				Rdata <= P23(15 downto 8);
			when 24 =>
				Rdata <= P23(7 downto 0);
			when 25 =>
				Rdata <= P22(31 downto 24);
			when 26 =>
				Rdata <= P22(23 downto 16);
			when 27 =>
				Rdata <= P22(15 downto 8);
			when 28 =>
				Rdata <= P22(7 downto 0);
			when 29 =>
				Rdata <= P21(31 downto 24);
			when 30 =>
				Rdata <= P21(23 downto 16);
			when 31 =>
				Rdata <= P21(15 downto 8);
			when 32 =>
				Rdata <= P21(7 downto 0);
			when 33 =>
				Rdata <= P20(31 downto 24);
			when 34 =>
				Rdata <= P20(23 downto 16);
			when 35 =>
				Rdata <= P20(15 downto 8);
			when 36 =>
				Rdata <= P20(7 downto 0);
			when 37 =>
				Rdata <= P19(31 downto 24);
			when 38 =>
				Rdata <= P19(23 downto 16);
			when 39 =>
				Rdata <= P19(15 downto 8);
			when 40 =>
				Rdata <= P19(7 downto 0);
			when others =>
				Rdata <= (others => '0');
		end case;
	end process;
--------------------------------------------

-- Raw data strobe
--------------------------------------------
	RDS_CLR(0 downto 0) <= conv_std_logic_vector(RDY_CNT, 1);
--------------------------
	process(RDS_CLR, Clock, RDY_CNT)
	begin
		if (RDS_CLR(0) = '0') then
			STB_EVE <= '0';
		elsif(Clock'event and Clock = '1') then
			if (1 <= RDY_CNT and RDY_CNT <= 40) then
				STB_EVE <= '1';
			else
				STB_EVE <= '0';
			end if;
		end if;
	end process;
--------------------------
	process(RDS_CLR, Clock, RDY_CNT)
	begin
		if (RDS_CLR(0) = '1') then
			STB_ODD <= '0';
		elsif(Clock'event and Clock = '1') then
			if (1 <= RDY_CNT and RDY_CNT <= 40) then
				STB_ODD <= '1';
			else
				STB_ODD <= '0';
			end if;
		end if;
	end process;
--------------------------
	RDstb <= STB_EVE or STB_ODD;
--------------------------------------------

end;