-- The H1 radiation monitor and the FST trigger based on the
-- FTI_0 avalanche diodes and the FTI_2 scintillation counters.
-- Trigger elements share one cable with the BST pad detector.

--	BST trigger elements:
--	--------------------
--	Bit_0 - Track(s) with a Phi-granularity = Pi/8;
--	Bit_1 - Calibration track parallel to the beampipe;
--	Bit_2 - Veto on high multiplicity of triggered pads;

--	FST trigger elements:
--	--------------------
--	Bit_3 - Track(s) with a Phi-granularity = Pi/2;
--	Bit_4 - OR(FTI_0(i)) i=0..31 for the T0 studies;
--	Bit_5 - OR(FTI_2(i)) I=0..31 for the T0 studies;

--	Radiation monitors:
--	------------------
--	Bit_6 - FTI_0 radiation monitor;
--	Bit_7 - BST Pad radiation monitor;

-- Channel mapping:
--
--	Cable	 Location	Pin 	Signal
-------------------------------------------
--	FTI_0/1   South 	Tinp00	FT0_DAT( 7..0)
--	FTI_0/1   South 	Tinp01	FT0_DAT(15..8)
--
--	FTI_0/2   North 	Tinp20	FT0_DAT(23..16)
--	FTI_0/2   North 	Tinp21	FT0_DAT(31..24)
--
--	FTI_2/1   Outer 	Tinp10	FT2_DAT( 7..0)
--	FTI_2/2   Outer 	Tinp11	FT2_DAT(15..8)
--
--	FTI_2/3   Inner 	Tinp30	FT2_DAT(16..23)
--	FTI_2/4   Inner 	Tinp31	FT2_DAT(24..31)

--	BST_Pad				Tinp50(7..0)
-------------------------------------------

-- Data strobe for the FTI_0 signals is derived from
-- the HERA clock frequency, its delay is adjusted via
-- the register. The FTI_2 pulses are synchronized to
-- this strobe too. Trigger pulses of either system
-- could be delayed with respect to each other by a
-- number of HERA bunch crossings to put them in
-- coincidence. The L1-data strobe has a fixed
-- delay of 30 ns.

-- Slow control registers:
--------------------------
-- x00 (In0_REG, 4 bits) RM mask for the FTI_0_south, Channels  0..3;
-- x02 (In1_REG, 4 bits) RM mask for the FTI_0_south, Channels  4..7;
-- x04 (In2_REG, 4 bits) RM mask for the FTI_0_south, Channels  8..11;
-- x06 (In3_REG, 4 bits) RM mask for the FTI_0_south, Channels 12..15;

-- x08 (EX0_REG, 4 bits) RM mask for the FTI_0_north, Channels  0..3;
-- x0A (EX1_REG, 4 bits) RM mask for the FTI_0_north, Channels  4..7;
-- x0C (EX2_REG, 4 bits) RM mask for the FTI_0_north, Channels  8..11;
-- x0E (EX3_REG, 4 bits) RM mask for the FTI_0_north, Channels 12..15;

-- x10 (CLK_FT0, 4 bits) HERA clock tuning for the FTI_0 in 10 steps of 10 ns;
-- x12 (CLK_FT2, 4 bits) HERA clock tuning for the FTI_2 in 10 steps of 10 ns;
-- x14 (CLK_PAD, 4 bits) HERA clock tuning for the BSTP in 10 steps of 10 ns;

-- x16 (DEL_FT0, 4 bits) Delay (in HERA b.c.) for the FTI_0 signals
-- x18 (DEL_FT2, 4 bits) Delay (in HERA b.c.) for the FTI_2 signals
-- x1A (PED_REG, 4 bits) Number * 1kHz subtracted from rad. monitor rate;
--
-- x1C (ST_RATE, 1 bit) Bit_0 = '1' stucks the rad. monitor rate;
-- x1E (RAD_LEV, 4 bit) Radiation level control;
--------------------------------------------

-- The radiation monitor has a pedestal subtraction
-- (0...16) kHz in steps of 1 kHz that allows for
-- the lower threshold settings for the trigger.
-- The subtracted value is kept in register 'x1A'.

-- The radiation monitor rate could be stuck at the
-- current level through register 'x1C' (Bit_0 = '1') in
-- order do not make HERA shift crew nervous during the
-- system reset. Be aware you may stuck the high value !

-- The radiation level is controlled through the
-- register x1E. The measurement range is 0...5 MHz
-- with a 250 kHz resolution

-- Copyright I.Tsurin, University of Antwerpen,
-- on behalf of DESY.
--------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;

library LPM;
use LPM.LPM_components.all;

--	OK. Here the entity starts...
--------------------------------------------
entity L1trigger is
port(
	MSTB_SW: in std_logic_vector(3 downto 0);	-- spare (for use without VME access);

	DLY_OUT: out std_logic;						-- HERA clock routing to the delay line;
	DLY_TAP: in  std_logic_vector(9 downto 0);	-- Delayed HERA clock frequency;
	
	Rdata: inout std_logic_vector(3 downto 0);	-- The lower 4 bits of Rdata
	Raddr: in std_logic_vector(3 downto 0);		-- The upper 4 bits of Rdata
	Write: in  std_logic;						-- Former TXD (output);
	RDstb: in std_logic;
	
	Enable: in std_logic;						-- "Pipeline enable" in the test mode;
	Clear: in std_logic;						-- "Fast clear" in the test mode;

	Tinp00: in std_logic_vector(7 downto 0);	-- |	
	Tinp01: in std_logic_vector(7 downto 0);	-- |
	Tinp10: in std_logic_vector(7 downto 0);	-- |
	Tinp11: in std_logic_vector(7 downto 0);	-- |
	Tinp20: in std_logic_vector(7 downto 0);	-- |
	Tinp21: in std_logic_vector(7 downto 0);	-- | Input trigger data from 6 repeaters;
	Tinp30: in std_logic_vector(7 downto 0);	-- |
	Tinp31: in std_logic_vector(7 downto 0);	-- |
	Tinp40: in std_logic_vector(7 downto 0);	-- |
	Tinp41: in std_logic_vector(7 downto 0);	-- |
	Tinp50: in std_logic_vector(7 downto 0);	-- |
	Tinp51: in std_logic_vector(7 downto 0);	-- |

	TSTB0: in std_logic;	-- Strobe for the trigger data from the 1st repeater;
	TSTB1: in std_logic;	-- Strobe for the trigger data from the 2nd repeater;
	TSTB2: in std_logic;	-- |
	TSTB3: in std_logic;	-- | ...
	TSTB4: in std_logic;	-- |
	TSTB5: in std_logic;	-- Strobe for the trigger data from the 6th repeater;
	
	Mout: out std_logic_vector(7 downto 0);		-- L1 output word;	
	MSTB: out std_logic;						-- L1 data strobe;
	
	HCLK: in std_logic;			-- HERA synchronization frequency;
	GEN: in std_logic;			-- Synchronization frequency in the test mode;
	
	BCK_PAN: in std_logic;		-- Jumper for the external controls;
	
	EVT_LED: out std_logic;		-- LED indicating the FST trigger;
	VTO_LED: out std_logic;		-- LED indicating the radiation alarm;
	
	FCLR: in std_logic;			-- "Fast clear" signal from the H1 central trigger;
	PEN: in std_logic;			-- "Pipeline enable" from the H1 central triger;
	
	LAM0: in std_logic_vector(2 downto 0); 	-- Frontend Alteras download status;
	LAM1: in std_logic_vector(2 downto 0);	-- Frontend Alteras download status;

	Spare: in std_logic -- Former RXD (input);
	);

	attribute pinnum: string;

	attribute pinnum of MSTB_SW: signal is "7,4,3,2";		
	attribute pinnum of DLY_OUT: signal is "8";
	attribute pinnum of DLY_TAP: signal is "41,40,20,18,17,16,13,11,10,9";
	
	attribute pinnum of Rdata: signal is "53,54,55,57";
	attribute pinnum of Raddr: signal is "43,44,46,47";
	attribute pinnum of Write: signal is "50";
	attribute pinnum of RDstb: signal is "49";
	
	attribute pinnum of Enable: signal is "58";
	attribute pinnum of Clear: signal is "59";

	attribute pinnum of Tinp00: signal is "184,183,182,181,180,178,174,173";
	attribute pinnum of Tinp01: signal is "195,192,191,190,189,187,186,185";
	attribute pinnum of Tinp10: signal is "204,203,202,201,200,198,197,196";
	attribute pinnum of Tinp11: signal is "220,219,217,216,215,207,206,205";
	attribute pinnum of Tinp20: signal is "231,230,226,225,224,223,222,221";
	attribute pinnum of Tinp21: signal is "239,238,237,236,235,234,233,232";
	attribute pinnum of Tinp30: signal is "69,68,66,65,64,63,62,61";
	attribute pinnum of Tinp31: signal is "80,79,77,76,75,74,71,70";
	attribute pinnum of Tinp40: signal is "96,95,94,85,84,83,82,81";
	attribute pinnum of Tinp41: signal is "105,104,103,102,101,100,99,98";
	attribute pinnum of Tinp50: signal is "116,115,114,113,112,111,110,109";
	attribute pinnum of Tinp51: signal is "126,125,124,123,121,119,118,117";

	attribute pinnum of TSTB0: signal is "209";
	attribute pinnum of TSTB1: signal is "212";
	attribute pinnum of TSTB2: signal is "31";
	attribute pinnum of TSTB3: signal is "34";
	attribute pinnum of TSTB4: signal is "88";
	attribute pinnum of TSTB5: signal is "91";
	
	attribute pinnum of Mout: signal is "129,130,131,133,134,135,136,138";
	attribute pinnum of MSTB: signal is "143";
	
	attribute pinnum of HCLK: signal is "151";
	attribute pinnum of GEN: signal is "154";
	
	attribute pinnum of BCK_PAN: signal is "156";
	
	attribute pinnum of EVT_LED: signal is "157";
	attribute pinnum of VTO_LED: signal is "161";
	
	attribute pinnum of FCLR: signal is "160";
	attribute pinnum of PEN: signal is "163";
	
	attribute pinnum of LAM0: signal is "169,166,164";
	attribute pinnum of LAM1: signal is "172,171,170";

	attribute pinnum of Spare: signal is "48";
	end;

architecture behavior of L1trigger is

-- Initialization
--------------------------------------------
	signal DUM_RES: std_logic;
	signal RES_PUL: std_logic;
	signal RES_DEL: std_logic;
	signal INI_CNT: natural range 0 to 524287;
--------------------------------------------

-- Slow control variables
--------------------------------------------
	signal DataIn: std_logic_vector(3 downto 0);
	signal DataOut: std_logic_vector(3 downto 0);

	signal In0_REG: std_logic_vector(3 downto 0);
	signal In1_REG: std_logic_vector(3 downto 0);
	signal In2_REG: std_logic_vector(3 downto 0);
	signal In3_REG: std_logic_vector(3 downto 0);

	signal EX0_REG: std_logic_vector(3 downto 0);
	signal EX1_REG: std_logic_vector(3 downto 0);
	signal EX2_REG: std_logic_vector(3 downto 0);
	signal EX3_REG: std_logic_vector(3 downto 0);

	signal CLK_FT0: std_logic_vector(3 downto 0);
	signal CLK_FT2: std_logic_vector(3 downto 0);
	signal CLK_PAD: std_logic_vector(3 downto 0);

	signal DEL_FT0: std_logic_vector(3 downto 0);
	signal DEL_FT2: std_logic_vector(3 downto 0);

	signal PED_REG: std_logic_vector(3 downto 0);
	signal ST_RATE: std_logic;
--------------------------------------------

-- Synchronization scheme
--------------------------------------------
	signal Oscillator: std_logic;
	signal SYN_SEL: std_logic;
	signal Clock: std_logic;
	signal Sync: std_logic;
	signal Keep: std_logic;

	signal TCLK_CNT: natural range 0 to 15;
	signal MSTB_CNT: natural range 0 to 15;
	signal MSTB_VAL: natural range 0 to 15;

	signal Eve_FT0: std_logic_vector(31 downto 0);
	signal Odd_FT0: std_logic_vector(31 downto 0);

	signal Eve_FT2: std_logic_vector(31 downto 0);
	signal Odd_FT2: std_logic_vector(31 downto 0);

	signal TMP_CN0: natural range 0 to 1;
	signal TMP_DL0: natural range 0 to 1;

	signal TMP_CN2: natural range 0 to 1;
	signal TMP_DL2: natural range 0 to 1;

	signal CLR_Ev0: std_logic;
	signal CLR_Od0: std_logic;

	signal CLR_Ev2: std_logic;
	signal CLR_Od2: std_logic;
--------------------------------------------

-- Trigger elements
--------------------------------------------
	signal Basket: std_logic_vector(31 downto 0);
	signal Bucket: std_logic_vector(31 downto 0);

	signal FT0_DAT: std_logic_vector(31 downto 0);
	signal FT2_DAT: std_logic_vector(31 downto 0);

	signal FT0_SEG: std_logic_vector(3 downto 0);
	signal FT2_SEG: std_logic_vector(3 downto 0);

	signal FST_TRG: std_logic;
	signal FT0_GLB: std_logic;
	signal FT2_GLB: std_logic;
--------------------------------------------

-- pipeline
--------------------------------------------
	signal PIP_CNT: natural range 0 to 15;
	signal FT0_CNT: natural range 0 to 15;
	signal FT2_CNT: natural range 0 to 15;

	signal PIP_000: std_logic_vector(31 downto 0);
	signal PIP_001: std_logic_vector(31 downto 0);
	signal PIP_002: std_logic_vector(31 downto 0);
	signal PIP_003: std_logic_vector(31 downto 0);
	signal PIP_004: std_logic_vector(31 downto 0);
	signal PIP_005: std_logic_vector(31 downto 0);
	signal PIP_006: std_logic_vector(31 downto 0);
	signal PIP_007: std_logic_vector(31 downto 0);
	signal PIP_008: std_logic_vector(31 downto 0);
	signal PIP_009: std_logic_vector(31 downto 0);
	signal PIP_010: std_logic_vector(31 downto 0);
	signal PIP_011: std_logic_vector(31 downto 0);
	signal PIP_012: std_logic_vector(31 downto 0);
	signal PIP_013: std_logic_vector(31 downto 0);
	signal PIP_014: std_logic_vector(31 downto 0);
	signal PIP_015: std_logic_vector(31 downto 0);

	signal PIP_200: std_logic_vector(31 downto 0);
	signal PIP_201: std_logic_vector(31 downto 0);
	signal PIP_202: std_logic_vector(31 downto 0);
	signal PIP_203: std_logic_vector(31 downto 0);
	signal PIP_204: std_logic_vector(31 downto 0);
	signal PIP_205: std_logic_vector(31 downto 0);
	signal PIP_206: std_logic_vector(31 downto 0);
	signal PIP_207: std_logic_vector(31 downto 0);
	signal PIP_208: std_logic_vector(31 downto 0);
	signal PIP_209: std_logic_vector(31 downto 0);
	signal PIP_210: std_logic_vector(31 downto 0);
	signal PIP_211: std_logic_vector(31 downto 0);
	signal PIP_212: std_logic_vector(31 downto 0);
	signal PIP_213: std_logic_vector(31 downto 0);
	signal PIP_214: std_logic_vector(31 downto 0);
	signal PIP_215: std_logic_vector(31 downto 0);
--------------------------------------------

-- Radiation monitor variables
--------------------------------------------
	signal Timer: natural range 0 to 8388607;

	signal Collect: std_logic;
	signal Rescue: std_logic;
	signal Worker: std_logic;

	signal Frequency: natural range 0 to 8388607;
	signal Firewood: natural range 0 to 8388607;
	signal Pedestal: natural range 0 to 8388607;
	signal Oven: natural range 0 to 8388607;
--------------------------------------------

-- frequency modulation variables
--------------------------------------------
	signal DIV_NUM: std_logic_vector(22 downto 0);
	signal DIV_DEN: std_logic_vector(22 downto 0);
	signal DIV_RES: std_logic_vector(22 downto 0);
	signal DIV_REM: std_logic_vector(22 downto 0);

	signal DEN_LAT: natural range 0 to 8388607;
	signal Result: natural range 0 to 8388607;
	signal FRQ_CNT: natural range 0 to 8388607;

	signal RAD_MON: std_logic;
	signal RAD_RES: std_logic;
	signal RAD_OUT: std_logic;
--------------------------------------------

-- Radiation alarm variables
--------------------------------------------
	signal RAD_LEV: std_logic_vector(3 downto 0);
--------------------------------------------

-- LED mono-flope variables
--------------------------------------------
	signal EVT_GTE: std_logic;	
	signal EVT_CNT: natural range 0 to 1048575;
--------------------------------------------

-- PAD data
--------------------------------------------
	signal Tbuf: std_logic_vector(3 downto 0);

	signal BST_TRG: std_logic;
	signal BST_LNG: std_logic;
	signal BST_VTO: std_logic;
--------------------------------------------

-- Library declaration
--------------------------

-- LPM divider
--------------------------------------------
	component lpm_divide
	generic (
			lpm_widthn: natural;
			lpm_widthd: natural;
			lpm_type: string;
			lpm_nrepresentation: string;
			lpm_hint: string;
			lpm_drepresentation: string
			);
	port (
			Denom: in std_logic_vector (22 downto 0);
			Quotient: out std_logic_vector (22 downto 0);
			Remain: out std_logic_vector (22 downto 0);
			Numer: in std_logic_vector (22 downto 0)
			);
	end component;
--------------------------------------------

-- Function declaration:
--------------------------

-- Data type conversion:
-- binary#16 -> natural
--------------------------------------------
	function BIT23_to_NUM(BIT_ARR: std_logic_vector(22 downto 0)) return natural is
		variable TEMP: natural range 0 to 8388607;
	begin
			TEMP:=0;
		for I in BIT_ARR'range loop
			TEMP:= TEMP * 2;
			if (BIT_ARR(I) = '1') then
				TEMP:= TEMP + 1;
			else
				null;
			end if;
		end loop;
	return TEMP;
	end BIT23_to_NUM;
--------------------------------------------

-- Data type conversion:
-- binary#4 -> natural
--------------------------------------------
	function BIT4_to_NUM(BIT_ARR: std_logic_vector(3 downto 0)) return natural is
		variable TEMP: natural range 0 to 15;
	begin
			TEMP:=0;
		for I in BIT_ARR'range loop
			TEMP:= TEMP * 2;
			if (BIT_ARR(I) = '1') then
				TEMP:= TEMP + 1;
			else
				null;
			end if;
		end loop;
	return TEMP;
	end BIT4_to_NUM;
--------------------------------------------

-- SUM_of_ONES_32 is used to count a number
-- of avalanche diodes triggered in one HERA
-- bunch crossing
--------------------------------------------
	function SUM_of_ONES_32(TRIG_PAT: std_logic_vector(31 downto 0)) return natural is
		variable TEMP: natural range 0 to 8388607;
	begin
		TEMP:= 0;
		for Index in TRIG_PAT'range loop
			if (TRIG_PAT(Index) = '1') then
				TEMP:= TEMP + 1;
			end if;
		end loop;
		return TEMP;
	end SUM_of_ONES_32;
--------------------------------------------

begin

-- Permanent statements
--------------------------------------------
	DUM_RES <= '0';
--------------------------
	DLY_OUT <= SYN_SEL;
--------------------------------------------

-- Start-up counter
--------------------------------------------
	process(DUM_RES, Clock, RES_PUL)
	begin
		if (DUM_RES = '1') then
			INI_CNT <= 0;
		elsif (Clock'event and Clock = '1') then
			if (RES_PUL = '1') then
				INI_CNT <= INI_CNT + 1;
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Start-up reset pulse (Clock <-)
--------------------------------------------
	process(DUM_RES, Clock, INI_CNT)
	begin
		if (DUM_RES = '1') then
			RES_PUL <= '1';
		elsif (Clock'event and Clock = '0') then
			if (INI_CNT = 524287) then
				RES_PUL <= '0';
			else
				RES_PUL <= '1';
			end if;
		end if;
	end process;
--------------------------
	process(Clock, RES_PUL)
	begin
		if (Clock'event and Clock = '1') then
			RES_DEL <= RES_PUL;
		end if;
	end process;
--------------------------------------------

-- Bidirectional port
--------------------------------------------
	process(Write, DataOut)
	begin
		if (Write = '1') then
			Rdata <= (others => 'Z');
		else
			Rdata <= DataOut;
		end if;
	end process;
--------------------------
	DataIn <= Rdata;
--------------------------------------------

-- Assign registers
--------------------------------------------
	process(RES_PUL, RDstb, Write, Raddr, DataIn)
	begin
		if (RES_PUL = '1') then
			In0_REG <= "1111";
			In1_REG <= "1111";
			In2_REG <= "1111";
			In3_REG <= "1111";

			EX0_REG <= "1111";
			EX1_REG <= "1111";
			EX2_REG <= "1111";
			EX3_REG <= "1111";

			CLK_FT0 <= "0100";
			CLK_FT2 <= "0101";
			CLK_PAD <= "0111";

			DEL_FT0 <= "0101";
			DEL_FT2 <= "0011";

			PED_REG <= "0000";
			ST_RATE <= '0';
		elsif (RDstb'event and RDstb = '1') then
			if (Write = '1') then
				if (Raddr = "0000") then
					In0_REG <= DataIn;
				elsif (Raddr = "0001") then
					In1_REG <= DataIn;
				elsif (Raddr = "0010") then
					In2_REG <= DataIn;
				elsif (Raddr = "0011") then
					In3_REG <= DataIn;
				elsif (Raddr = "0100") then
					EX0_REG <= DataIn;
				elsif (Raddr = "0101") then
					EX1_REG <= DataIn;
				elsif (Raddr = "0110") then
					EX2_REG <= DataIn;
				elsif (Raddr = "0111") then
					EX3_REG <= DataIn;
				elsif (Raddr = "1000") then
					CLK_FT0 <= DataIn;
				elsif (Raddr = "1001") then
					CLK_FT2 <= DataIn;
				elsif (Raddr = "1010") then
					CLK_PAD <= DataIn;
				elsif (Raddr = "1011") then
					DEL_FT0 <= DataIn;
				elsif (Raddr = "1100") then
					DEL_FT2 <= DataIn;
				elsif (Raddr = "1101") then
					PED_REG <= DataIn;
				elsif (Raddr = "1110") then
					ST_RATE <= DataIn(0);
				else
					null;
				end if;
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Read registers
--------------------------------------------
	process(Raddr,
			In0_REG, In1_REG, In2_REG, In3_REG,
			EX0_REG, EX1_REG, EX2_REG, EX3_REG,
			CLK_FT0, CLK_FT2, CLK_PAD, DEL_FT0,
			DEL_FT2, PED_REG, ST_RATE, RAD_LEV)
	begin
		case Raddr is
			when "0000" =>
				DataOut <= In0_REG;
			when "0001" =>
				DataOut <= In1_REG;
			when "0010" =>
				DataOut <= In2_REG;
			when "0011" =>
				DataOut <= In3_REG;
			when "0100" =>
				DataOut <= EX0_REG;
			when "0101" =>
				DataOut <= EX1_REG;
			when "0110" =>
				DataOut <= EX2_REG;
			when "0111" =>
				DataOut <= EX3_REG;
			when "1000" =>
				DataOut <= CLK_FT0;
			when "1001" =>
				DataOut <= CLK_FT2;
			when "1010" =>
				DataOut <= CLK_PAD;
			when "1011" =>
				DataOut <= DEL_FT0;
			when "1100" =>
				DataOut <= DEL_FT2;
			when "1101" =>
				DataOut <= PED_REG;
			when "1110" =>
				DataOut(0) <= ST_RATE;
				DataOut(3 downto 1) <= "000";
			when others =>
				DataOut <= RAD_LEV;
		end case;
	end process;
--------------------------------------------

-- Clock frequency with an external pulser.
-- It is useful when the H1 central trigger
-- is stopped and the default potential of
-- the HCLK signal is not known (thought to
-- be zero). The scheme allows running with
-- the "GEN" connector pluged or unpluged.
--------------------------------------------
	process(HCLK, GEN)
	begin
		case HCLK is
			when '1' =>
				Oscillator <= GEN;
			when others =>
				Oscillator <= not GEN;
			end case;
	end process;
--------------------------------------------

-- Selecting external controls between the
-- backplane and the front panel. The first
-- choice is needed when the card is operated
-- in H1 without control signals from the
-- central trigger, but the backplane signals
-- are well defined. The system will accept
-- external control automatically. The second
-- case is for the pure stand-alone operation
-- with external controls (the levels at the
-- backplane may oscillate).
--------------------------------------------
	process(BCK_PAN, Oscillator, GEN)
	begin
		case BCK_PAN is
			when '1' =>
				SYN_SEL <= Oscillator;	-- Clock from the backpl. / Fr. panel.;
			when others =>
				SYN_SEL <= GEN;			-- "Clock" pulses (positive polarity);
		end case;
	end process;
--------------------------------------------

-- Phase adjustment for the Clock freq.
--------------------------------------------
	process(CLK_FT0, DLY_TAP, SYN_SEL)
	begin
		case CLK_FT0 is
			when "1001" =>
				Clock <= DLY_TAP(9);
				TCLK_CNT <= 10;
			when "1000" =>
				Clock <= DLY_TAP(8);
				TCLK_CNT <= 9;
			when "0111" =>
				Clock <= DLY_TAP(7);
				TCLK_CNT <= 8;
			when "0110" =>
				Clock <= DLY_TAP(6);
				TCLK_CNT <= 7;
			when "0101" =>
				Clock <= DLY_TAP(5);
				TCLK_CNT <= 6;
			when "0100" =>
				Clock <= DLY_TAP(4);
				TCLK_CNT <= 5;
			when "0011" =>
				Clock <= DLY_TAP(3);
				TCLK_CNT <= 4;
			when "0010" =>
				Clock <= DLY_TAP(2);
				TCLK_CNT <= 3;
			when "0001" =>
				Clock <= DLY_TAP(1);
				TCLK_CNT <= 2;
			when "0000" =>
				Clock <= DLY_TAP(0);
				TCLK_CNT <= 1;
			when others =>
				Clock <= SYN_SEL;
				TCLK_CNT <= 0;
		end case;
	end process;
--------------------------------------------

-- Delay for the data strobe
--------------------------------------------
	MSTB_CNT <= TCLK_CNT + 3;
--------------------------------------------

-- Periodic correction (excluding zero)
--------------------------------------------
	process(MSTB_CNT)
	begin
		case MSTB_CNT is
			when 0 to 10 =>
				MSTB_VAL <= MSTB_CNT;
			when others =>
				MSTB_VAL <= MSTB_CNT - 10;
		end case;
	end process;
--------------------------------------------

-- Phase adjustment for the output strobe
--------------------------------------------
	process(MSTB_VAL, DLY_TAP, SYN_SEL)
	begin
		case MSTB_VAL is
			when 10 =>
				MSTB <= DLY_TAP(9);
			when 9 =>
				MSTB <= DLY_TAP(8);
			when 8 =>
				MSTB <= DLY_TAP(7);
			when 7 =>
				MSTB <= DLY_TAP(6);
			when 6 =>
				MSTB <= DLY_TAP(5);
			when 5 =>
				MSTB <= DLY_TAP(4);
			when 4 =>
				MSTB <= DLY_TAP(3);
			when 3 =>
				MSTB <= DLY_TAP(2);
			when 2 =>
				MSTB <= DLY_TAP(1);
			when 1 =>
				MSTB <= DLY_TAP(0);
			when others =>
				MSTB <= SYN_SEL;
		end case;
	end process;
--------------------------------------------

-- Phase adjustment for the Sync freq.
--------------------------------------------
	process(CLK_FT2, DLY_TAP, SYN_SEL)
	begin
		case CLK_FT2 is
			when "1001" =>
				Sync <= DLY_TAP(9);
			when "1000" =>
				Sync <= DLY_TAP(8);
			when "0111" =>
				Sync <= DLY_TAP(7);
			when "0110" =>
				Sync <= DLY_TAP(6);
			when "0101" =>
				Sync <= DLY_TAP(5);
			when "0100" =>
				Sync <= DLY_TAP(4);
			when "0011" =>
				Sync <= DLY_TAP(3);
			when "0010" =>
				Sync <= DLY_TAP(2);
			when "0001" =>
				Sync <= DLY_TAP(1);
			when "0000" =>
				Sync <= DLY_TAP(0);
			when others =>
				Sync <= SYN_SEL;
		end case;
	end process;
--------------------------------------------

-- Phase adjustment for the Latch freq.
--------------------------------------------
	process(CLK_PAD, DLY_TAP, SYN_SEL)
	begin
		case CLK_PAD is
			when "1001" =>
				Keep <= DLY_TAP(9);
			when "1000" =>
				Keep <= DLY_TAP(8);
			when "0111" =>
				Keep <= DLY_TAP(7);
			when "0110" =>
				Keep <= DLY_TAP(6);
			when "0101" =>
				Keep <= DLY_TAP(5);
			when "0100" =>
				Keep <= DLY_TAP(4);
			when "0011" =>
				Keep <= DLY_TAP(3);
			when "0010" =>
				Keep <= DLY_TAP(2);
			when "0001" =>
				Keep <= DLY_TAP(1);
			when "0000" =>
				Keep <= DLY_TAP(0);
			when others =>
				Keep <= SYN_SEL;
		end case;
	end process;
--------------------------------------------

-- 32 latches for the FTI_0 input signals
-- (this idea doesn't work as a subroutine
-- and has to be written for every process
-- separately)
--------------------------

-- bit "0", even timeslice
--------------------------
	process(In0_REG(0), CLR_Ev0, Tinp00(0))
	begin
		if (In0_REG(0) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(0) <= '0';
		elsif (Tinp00(0)'event and Tinp00(0) = '0') then
			Eve_FT0(0) <= '1';
		end if;
	end process;
--------------------------

-- bit "0", odd timeslice
--------------------------
	process(In0_REG(0), CLR_Od0, Tinp00(0))
	begin
		if (In0_REG(0) = '0' or CLR_Od0 = '1') then
			Odd_FT0(0) <= '0';
		elsif (Tinp00(0)'event and Tinp00(0) = '0') then
			Odd_FT0(0) <= '1';
		end if;
	end process;
--------------------------

-- bit "1", even timeslice
--------------------------
	process(In0_REG(1), CLR_Ev0, Tinp00(1))
	begin
		if (In0_REG(1) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(1) <= '0';
		elsif (Tinp00(1)'event and Tinp00(1) = '0') then
			Eve_FT0(1) <= '1';
		end if;
	end process;
--------------------------

-- bit "1", odd timeslice
--------------------------
	process(In0_REG(1), CLR_Od0, Tinp00(1))
	begin
		if (In0_REG(1) = '0' or CLR_Od0 = '1') then
			Odd_FT0(1) <= '0';
		elsif (Tinp00(1)'event and Tinp00(1) = '0') then
			Odd_FT0(1) <= '1';
		end if;
	end process;
--------------------------

-- bit "2", even timeslice
--------------------------
	process(In0_REG(2), CLR_Ev0, Tinp00(2))
	begin
		if (In0_REG(2) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(2) <= '0';
		elsif (Tinp00(2)'event and Tinp00(2) = '0') then
			Eve_FT0(2) <= '1';
		end if;
	end process;
--------------------------

-- bit "2", odd timeslice
--------------------------
	process(In0_REG(2), CLR_Od0, Tinp00(2))
	begin
		if (In0_REG(2) = '0' or CLR_Od0 = '1') then
			Odd_FT0(2) <= '0';
		elsif (Tinp00(2)'event and Tinp00(2) = '0') then
			Odd_FT0(2) <= '1';
		end if;
	end process;
--------------------------

-- bit "3", even timeslice
--------------------------
	process(In0_REG(3), CLR_Ev0, Tinp00(3))
	begin
		if (In0_REG(3) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(3) <= '0';
		elsif (Tinp00(3)'event and Tinp00(3) = '0') then
			Eve_FT0(3) <= '1';
		end if;
	end process;
--------------------------

-- bit "3", odd timeslice
--------------------------
	process(In0_REG(3), CLR_Od0, Tinp00(3))
	begin
		if (In0_REG(3) = '0' or CLR_Od0 = '1') then
			Odd_FT0(3) <= '0';
		elsif (Tinp00(3)'event and Tinp00(3) = '0') then
			Odd_FT0(3) <= '1';
		end if;
	end process;
--------------------------

-- bit "4", even timeslice
--------------------------
	process(In1_REG(0), CLR_Ev0, Tinp00(4))
	begin
		if (In1_REG(0) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(4) <= '0';
		elsif (Tinp00(4)'event and Tinp00(4) = '0') then
			Eve_FT0(4) <= '1';
		end if;
	end process;
--------------------------

-- bit "4", odd timeslice
--------------------------
	process(In1_REG(0), CLR_Od0, Tinp00(4))
	begin
		if (In1_REG(0) = '0' or CLR_Od0 = '1') then
			Odd_FT0(4) <= '0';
		elsif (Tinp00(4)'event and Tinp00(4) = '0') then
			Odd_FT0(4) <= '1';
		end if;
	end process;
--------------------------

-- bit "5", even timeslice
--------------------------
	process(In1_REG(1), CLR_Ev0, Tinp00(5))
	begin
		if (In1_REG(1) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(5) <= '0';
		elsif (Tinp00(5)'event and Tinp00(5) = '0') then
			Eve_FT0(5) <= '1';
		end if;
	end process;
--------------------------

-- bit "5", odd timeslice
--------------------------
	process(In1_REG(1), CLR_Od0, Tinp00(5))
	begin
		if (In1_REG(1) = '0' or CLR_Od0 = '1') then
			Odd_FT0(5) <= '0';
		elsif (Tinp00(5)'event and Tinp00(5) = '0') then
			Odd_FT0(5) <= '1';
		end if;
	end process;
--------------------------

-- bit "6", even timeslice
--------------------------
	process(In1_REG(2), CLR_Ev0, Tinp00(6))
	begin
		if (In1_REG(2) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(6) <= '0';
		elsif (Tinp00(6)'event and Tinp00(6) = '0') then
			Eve_FT0(6) <= '1';
		end if;
	end process;
--------------------------

-- bit "6", odd timeslice
--------------------------
	process(In1_REG(2), CLR_Od0, Tinp00(6))
	begin
		if (In1_REG(2) = '0' or CLR_Od0 = '1') then
			Odd_FT0(6) <= '0';
		elsif (Tinp00(6)'event and Tinp00(6) = '0') then
			Odd_FT0(6) <= '1';
		end if;
	end process;
--------------------------

-- bit "7", even timeslice
--------------------------
	process(In1_REG(3), CLR_Ev0, Tinp00(7))
	begin
		if (In1_REG(3) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(7) <= '0';
		elsif (Tinp00(7)'event and Tinp00(7) = '0') then
			Eve_FT0(7) <= '1';
		end if;
	end process;
--------------------------

-- bit "7", odd timeslice
--------------------------
	process(In1_REG(3), CLR_Od0, Tinp00(7))
	begin
		if (In1_REG(3) = '0' or CLR_Od0 = '1') then
			Odd_FT0(7) <= '0';
		elsif (Tinp00(7)'event and Tinp00(7) = '0') then
			Odd_FT0(7) <= '1';
		end if;
	end process;
--------------------------

-- bit "8", even timeslice
--------------------------
	process(In2_REG(0), CLR_Ev0, Tinp01(0))
	begin
		if (In2_REG(0) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(8) <= '0';
		elsif (Tinp01(0)'event and Tinp01(0) = '0') then
			Eve_FT0(8) <= '1';
		end if;
	end process;
--------------------------

-- bit "8", odd timeslice
--------------------------
	process(In2_REG(0), CLR_Od0, Tinp01(0))
	begin
		if (In2_REG(0) = '0' or CLR_Od0 = '1') then
			Odd_FT0(8) <= '0';
		elsif (Tinp01(0)'event and Tinp01(0) = '0') then
			Odd_FT0(8) <= '1';
		end if;
	end process;
--------------------------

-- bit "9", even timeslice
--------------------------
	process(In2_REG(1), CLR_Ev0, Tinp01(1))
	begin
		if (In2_REG(1) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(9) <= '0';
		elsif (Tinp01(1)'event and Tinp01(1) = '0') then
			Eve_FT0(9) <= '1';
		end if;
	end process;
--------------------------

-- bit "9", odd timeslice
--------------------------
	process(In2_REG(1), CLR_Od0, Tinp01(1))
	begin
		if (In2_REG(1) = '0' or CLR_Od0 = '1') then
			Odd_FT0(9) <= '0';
		elsif (Tinp01(1)'event and Tinp01(1) = '0') then
			Odd_FT0(9) <= '1';
		end if;
	end process;
--------------------------

-- bit "10", even timeslice
--------------------------
	process(In2_REG(2), CLR_Ev0, Tinp01(2))
	begin
		if (In2_REG(2) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(10) <= '0';
		elsif (Tinp01(2)'event and Tinp01(2) = '0') then
			Eve_FT0(10) <= '1';
		end if;
	end process;
--------------------------

-- bit "10", odd timeslice
--------------------------
	process(In2_REG(2), CLR_Od0, Tinp01(2))
	begin
		if (In2_REG(2) = '0' or CLR_Od0 = '1') then
			Odd_FT0(10) <= '0';
		elsif (Tinp01(2)'event and Tinp01(2) = '0') then
			Odd_FT0(10) <= '1';
		end if;
	end process;
--------------------------

-- bit "11", even timeslice
--------------------------
	process(In2_REG(3), CLR_Ev0, Tinp01(3))
	begin
		if (In2_REG(3) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(11) <= '0';
		elsif (Tinp01(3)'event and Tinp01(3) = '0') then
			Eve_FT0(11) <= '1';
		end if;
	end process;
--------------------------

-- bit "11", odd timeslice
--------------------------
	process(In2_REG(3), CLR_Od0, Tinp01(3))
	begin
		if (In2_REG(3) = '0' or CLR_Od0 = '1') then
			Odd_FT0(11) <= '0';
		elsif (Tinp01(3)'event and Tinp01(3) = '0') then
			Odd_FT0(11) <= '1';
		end if;
	end process;
--------------------------

-- bit "12", even timeslice
--------------------------
	process(In3_REG(0), CLR_Ev0, Tinp01(4))
	begin
		if (In3_REG(0) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(12) <= '0';
		elsif (Tinp01(4)'event and Tinp01(4) = '0') then
			Eve_FT0(12) <= '1';
		end if;
	end process;
--------------------------

-- bit "12", odd timeslice
--------------------------
	process(In3_REG(0), CLR_Od0, Tinp01(4))
	begin
		if (In3_REG(0) = '0' or CLR_Od0 = '1') then
			Odd_FT0(12) <= '0';
		elsif (Tinp01(4)'event and Tinp01(4) = '0') then
			Odd_FT0(12) <= '1';
		end if;
	end process;
--------------------------

-- bit "13", even timeslice
--------------------------
	process(In3_REG(1), CLR_Ev0, Tinp01(5))
	begin
		if (In3_REG(1) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(13) <= '0';
		elsif (Tinp01(5)'event and Tinp01(5) = '0') then
			Eve_FT0(13) <= '1';
		end if;
	end process;
--------------------------

-- bit "13", odd timeslice
--------------------------
	process(In3_REG(1), CLR_Od0, Tinp01(5))
	begin
		if (In3_REG(1) = '0' or CLR_Od0 = '1') then
			Odd_FT0(13) <= '0';
		elsif (Tinp01(5)'event and Tinp01(5) = '0') then
			Odd_FT0(13) <= '1';
		end if;
	end process;
--------------------------

-- bit "14", even timeslice
--------------------------
	process(In3_REG(2), CLR_Ev0, Tinp01(6))
	begin
		if (In3_REG(2) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(14) <= '0';
		elsif (Tinp01(6)'event and Tinp01(6) = '0') then
			Eve_FT0(14) <= '1';
		end if;
	end process;
--------------------------

-- bit "14", odd timeslice
--------------------------
	process(In3_REG(2), CLR_Od0, Tinp01(6))
	begin
		if (In3_REG(2) = '0' or CLR_Od0 = '1') then
			Odd_FT0(14) <= '0';
		elsif (Tinp01(6)'event and Tinp01(6) = '0') then
			Odd_FT0(14) <= '1';
		end if;
	end process;
--------------------------

-- bit "15", even timeslice
--------------------------
	process(In3_REG(3), CLR_Ev0, Tinp01(7))
	begin
		if (In3_REG(3) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(15) <= '0';
		elsif (Tinp01(7)'event and Tinp01(7) = '0') then
			Eve_FT0(15) <= '1';
		end if;
	end process;
--------------------------

-- bit "15", odd timeslice
--------------------------
	process(In3_REG(3), CLR_Od0, Tinp01(7))
	begin
		if (In3_REG(3) = '0' or CLR_Od0 = '1') then
			Odd_FT0(15) <= '0';
		elsif (Tinp01(7)'event and Tinp01(7) = '0') then
			Odd_FT0(15) <= '1';
		end if;
	end process;
--------------------------

-- bit "16", even timeslice
--------------------------
	process(EX0_REG(0), CLR_Ev0, Tinp20(0))
	begin
		if (EX0_REG(0) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(16) <= '0';
		elsif (Tinp20(0)'event and Tinp20(0) = '0') then
			Eve_FT0(16) <= '1';
		end if;
	end process;
--------------------------

-- bit "16", odd timeslice
--------------------------
	process(EX0_REG(0), CLR_Od0, Tinp20(0))
	begin
		if (EX0_REG(0) = '0' or CLR_Od0 = '1') then
			Odd_FT0(16) <= '0';
		elsif (Tinp20(0)'event and Tinp20(0) = '0') then
			Odd_FT0(16) <= '1';
		end if;
	end process;
--------------------------

-- bit "17", even timeslice
--------------------------
	process(EX0_REG(1), CLR_Ev0, Tinp20(1))
	begin
		if (EX0_REG(1) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(17) <= '0';
		elsif (Tinp20(1)'event and Tinp20(1) = '0') then
			Eve_FT0(17) <= '1';
		end if;
	end process;
--------------------------

-- bit "17", odd timeslice
--------------------------
	process(EX0_REG(1), CLR_Od0, Tinp20(1))
	begin
		if (EX0_REG(1) = '0' or CLR_Od0 = '1') then
			Odd_FT0(17) <= '0';
		elsif (Tinp20(1)'event and Tinp20(1) = '0') then
			Odd_FT0(17) <= '1';
		end if;
	end process;
--------------------------

-- bit "18", even timeslice
--------------------------
	process(EX0_REG(2), CLR_Ev0, Tinp20(2))
	begin
		if (EX0_REG(2) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(18) <= '0';
		elsif (Tinp20(2)'event and Tinp20(2) = '0') then
			Eve_FT0(18) <= '1';
		end if;
	end process;
--------------------------

-- bit "18", odd timeslice
--------------------------
	process(EX0_REG(2), CLR_Od0, Tinp20(2))
	begin
		if (EX0_REG(2) = '0' or CLR_Od0 = '1') then
			Odd_FT0(18) <= '0';
		elsif (Tinp20(2)'event and Tinp20(2) = '0') then
			Odd_FT0(18) <= '1';
		end if;
	end process;
--------------------------

-- bit "19", even timeslice
--------------------------
	process(EX0_REG(3), CLR_Ev0, Tinp20(3))
	begin
		if (EX0_REG(3) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(19) <= '0';
		elsif (Tinp20(3)'event and Tinp20(3) = '0') then
			Eve_FT0(19) <= '1';
		end if;
	end process;
--------------------------

-- bit "19", odd timeslice
--------------------------
	process(EX0_REG(3), CLR_Od0, Tinp20(3))
	begin
		if (EX0_REG(3) = '0' or CLR_Od0 = '1') then
			Odd_FT0(19) <= '0';
		elsif (Tinp20(3)'event and Tinp20(3) = '0') then
			Odd_FT0(19) <= '1';
		end if;
	end process;
--------------------------

-- bit "20", even timeslice
--------------------------
	process(EX1_REG(0), CLR_Ev0, Tinp20(4))
	begin
		if (EX1_REG(0) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(20) <= '0';
		elsif (Tinp20(4)'event and Tinp20(4) = '0') then
			Eve_FT0(20) <= '1';
		end if;
	end process;
--------------------------

-- bit "20", odd timeslice
--------------------------
	process(EX1_REG(0), CLR_Od0, Tinp20(4))
	begin
		if (EX1_REG(0) = '0' or CLR_Od0 = '1') then
			Odd_FT0(20) <= '0';
		elsif (Tinp20(4)'event and Tinp20(4) = '0') then
			Odd_FT0(20) <= '1';
		end if;
	end process;
--------------------------

-- bit "21", even timeslice
--------------------------
	process(EX1_REG(1), CLR_Ev0, Tinp20(5))
	begin
		if (EX1_REG(1) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(21) <= '0';
		elsif (Tinp20(5)'event and Tinp20(5) = '0') then
			Eve_FT0(21) <= '1';
		end if;
	end process;
--------------------------

-- bit "21", odd timeslice
--------------------------
	process(EX1_REG(1), CLR_Od0, Tinp20(5))
	begin
		if (EX1_REG(1) = '0' or CLR_Od0 = '1') then
			Odd_FT0(21) <= '0';
		elsif (Tinp20(5)'event and Tinp20(5) = '0') then
			Odd_FT0(21) <= '1';
		end if;
	end process;
--------------------------

-- bit "22", even timeslice
--------------------------
	process(EX1_REG(2), CLR_Ev0, Tinp20(6))
	begin
		if (EX1_REG(2) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(22) <= '0';
		elsif (Tinp20(6)'event and Tinp20(6) = '0') then
			Eve_FT0(22) <= '1';
		end if;
	end process;
--------------------------

-- bit "22", odd timeslice
--------------------------
	process(EX1_REG(2), CLR_Od0, Tinp20(6))
	begin
		if (EX1_REG(2) = '0' or CLR_Od0 = '1') then
			Odd_FT0(22) <= '0';
		elsif (Tinp20(6)'event and Tinp20(6) = '0') then
			Odd_FT0(22) <= '1';
		end if;
	end process;
--------------------------

-- bit "23", even timeslice
--------------------------
	process(EX1_REG(3), CLR_Ev0, Tinp20(7))
	begin
		if (EX1_REG(3) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(23) <= '0';
		elsif (Tinp20(7)'event and Tinp20(7) = '0') then
			Eve_FT0(23) <= '1';
		end if;
	end process;
--------------------------

-- bit "23", odd timeslice
--------------------------
	process(EX1_REG(3), CLR_Od0, Tinp20(7))
	begin
		if (EX1_REG(3) = '0' or CLR_Od0 = '1') then
			Odd_FT0(23) <= '0';
		elsif (Tinp20(7)'event and Tinp20(7) = '0') then
			Odd_FT0(23) <= '1';
		end if;
	end process;
--------------------------

-- bit "24", even timeslice
--------------------------
	process(EX2_REG(0), CLR_Ev0, Tinp21(0))
	begin
		if (EX2_REG(0) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(24) <= '0';
		elsif (Tinp21(0)'event and Tinp21(0) = '0') then
			Eve_FT0(24) <= '1';
		end if;
	end process;
--------------------------

-- bit "24", odd timeslice
--------------------------
	process(EX2_REG(0), CLR_Od0, Tinp21(0))
	begin
		if (EX2_REG(0) = '0' or CLR_Od0 = '1') then
			Odd_FT0(24) <= '0';
		elsif (Tinp21(0)'event and Tinp21(0) = '0') then
			Odd_FT0(24) <= '1';
		end if;
	end process;
--------------------------

-- bit "25", even timeslice
--------------------------
	process(EX2_REG(1), CLR_Ev0, Tinp21(1))
	begin
		if (EX2_REG(1) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(25) <= '0';
		elsif (Tinp21(1)'event and Tinp21(1) = '0') then
			Eve_FT0(25) <= '1';
		end if;
	end process;
--------------------------

-- bit "25", odd timeslice
--------------------------
	process(EX2_REG(1), CLR_Od0, Tinp21(1))
	begin
		if (EX2_REG(1) = '0' or CLR_Od0 = '1') then
			Odd_FT0(25) <= '0';
		elsif (Tinp21(1)'event and Tinp21(1) = '0') then
			Odd_FT0(25) <= '1';
		end if;
	end process;
--------------------------

-- bit "26", even timeslice
--------------------------
	process(EX2_REG(2), CLR_Ev0, Tinp21(2))
	begin
		if (EX2_REG(2) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(26) <= '0';
		elsif (Tinp21(2)'event and Tinp21(2) = '0') then
			Eve_FT0(26) <= '1';
		end if;
	end process;
--------------------------

-- bit "26", odd timeslice
--------------------------
	process(EX2_REG(2), CLR_Od0, Tinp21(2))
	begin
		if (EX2_REG(2) = '0' or CLR_Od0 = '1') then
			Odd_FT0(26) <= '0';
		elsif (Tinp21(2)'event and Tinp21(2) = '0') then
			Odd_FT0(26) <= '1';
		end if;
	end process;
--------------------------

-- bit "27", even timeslice
--------------------------
	process(EX2_REG(3), CLR_Ev0, Tinp21(3))
	begin
		if (EX2_REG(3) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(27) <= '0';
		elsif (Tinp21(3)'event and Tinp21(3) = '0') then
			Eve_FT0(27) <= '1';
		end if;
	end process;
--------------------------

-- bit "27", odd timeslice
--------------------------
	process(EX2_REG(3), CLR_Od0, Tinp21(3))
	begin
		if (EX2_REG(3) = '0' or CLR_Od0 = '1') then
			Odd_FT0(27) <= '0';
		elsif (Tinp21(3)'event and Tinp21(3) = '0') then
			Odd_FT0(27) <= '1';
		end if;
	end process;
--------------------------

-- bit "28", even timeslice
--------------------------
	process(EX3_REG(0), CLR_Ev0, Tinp21(4))
	begin
		if (EX3_REG(0) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(28) <= '0';
		elsif (Tinp21(4)'event and Tinp21(4) = '0') then
			Eve_FT0(28) <= '1';
		end if;
	end process;
--------------------------

-- bit "28", odd timeslice
--------------------------
	process(EX3_REG(0), CLR_Od0, Tinp21(4))
	begin
		if (EX3_REG(0) = '0' or CLR_Od0 = '1') then
			Odd_FT0(28) <= '0';
		elsif (Tinp21(4)'event and Tinp21(4) = '0') then
			Odd_FT0(28) <= '1';
		end if;
	end process;
--------------------------

-- bit "29", even timeslice
--------------------------
	process(EX3_REG(1), CLR_Ev0, Tinp21(5))
	begin
		if (EX3_REG(1) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(29) <= '0';
		elsif (Tinp21(5)'event and Tinp21(5) = '0') then
			Eve_FT0(29) <= '1';
		end if;
	end process;
--------------------------

-- bit "29", odd timeslice
--------------------------
	process(EX3_REG(1), CLR_Od0, Tinp21(5))
	begin
		if (EX3_REG(1) = '0' or CLR_Od0 = '1') then
			Odd_FT0(29) <= '0';
		elsif (Tinp21(5)'event and Tinp21(5) = '0') then
			Odd_FT0(29) <= '1';
		end if;
	end process;
--------------------------

-- bit "30", even timeslice
--------------------------
	process(EX3_REG(2), CLR_Ev0, Tinp21(6))
	begin
		if (EX3_REG(2) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(30) <= '0';
		elsif (Tinp21(6)'event and Tinp21(6) = '0') then
			Eve_FT0(30) <= '1';
		end if;
	end process;
--------------------------

-- bit "30", odd timeslice
--------------------------
	process(EX3_REG(2), CLR_Od0, Tinp21(6))
	begin
		if (EX3_REG(2) = '0' or CLR_Od0 = '1') then
			Odd_FT0(30) <= '0';
		elsif (Tinp21(6)'event and Tinp21(6) = '0') then
			Odd_FT0(30) <= '1';
		end if;
	end process;
--------------------------

-- bit "31", even timeslice
--------------------------
	process(EX3_REG(3), CLR_Ev0, Tinp21(7))
	begin
		if (EX3_REG(3) = '0' or CLR_Ev0 = '1') then
			Eve_FT0(31) <= '0';
		elsif (Tinp21(7)'event and Tinp21(7) = '0') then
			Eve_FT0(31) <= '1';
		end if;
	end process;
--------------------------

-- bit "31", odd timeslice
--------------------------
	process(EX3_REG(3), CLR_Od0, Tinp21(7))
	begin
		if (EX3_REG(3) = '0' or CLR_Od0 = '1') then
			Odd_FT0(31) <= '0';
		elsif (Tinp21(7)'event and Tinp21(7) = '0') then
			Odd_FT0(31) <= '1';
		end if;
	end process;
--------------------------------------------

-- 32 latches for the FTI_2 input signals
--------------------------

-- bit "0", even timeslice
--------------------------
	process(CLR_EV2, Tinp10(0))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(0) <= '0';
		elsif (Tinp10(0)'event and Tinp10(0) = '0') then
			Eve_FT2(0) <= '1';
		end if;
	end process;
--------------------------

-- bit "0", odd timeslice
--------------------------
	process(CLR_OD2, Tinp10(0))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(0) <= '0';
		elsif (Tinp10(0)'event and Tinp10(0) = '0') then
			Odd_FT2(0) <= '1';
		end if;
	end process;
--------------------------

-- bit "1", even timeslice
--------------------------
	process(CLR_EV2, Tinp10(1))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(1) <= '0';
		elsif (Tinp10(1)'event and Tinp10(1) = '0') then
			Eve_FT2(1) <= '1';
		end if;
	end process;
--------------------------

-- bit "1", odd timeslice
--------------------------
	process(CLR_OD2, Tinp10(1))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(1) <= '0';
		elsif (Tinp10(1)'event and Tinp10(1) = '0') then
			Odd_FT2(1) <= '1';
		end if;
	end process;
--------------------------

-- bit "2", even timeslice
--------------------------
	process(CLR_EV2, Tinp10(2))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(2) <= '0';
		elsif (Tinp10(2)'event and Tinp10(2) = '0') then
			Eve_FT2(2) <= '1';
		end if;
	end process;
--------------------------

-- bit "2", odd timeslice
--------------------------
	process(CLR_OD2, Tinp10(2))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(2) <= '0';
		elsif (Tinp10(2)'event and Tinp10(2) = '0') then
			Odd_FT2(2) <= '1';
		end if;
	end process;
--------------------------

-- bit "3", even timeslice
--------------------------
	process(CLR_EV2, Tinp10(3))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(3) <= '0';
		elsif (Tinp10(3)'event and Tinp10(3) = '0') then
			Eve_FT2(3) <= '1';
		end if;
	end process;
--------------------------

-- bit "3", odd timeslice
--------------------------
	process(CLR_OD2, Tinp10(3))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(3) <= '0';
		elsif (Tinp10(3)'event and Tinp10(3) = '0') then
			Odd_FT2(3) <= '1';
		end if;
	end process;
--------------------------

-- bit "4", even timeslice
--------------------------
	process(CLR_EV2, Tinp10(4))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(4) <= '0';
		elsif (Tinp10(4)'event and Tinp10(4) = '0') then
			Eve_FT2(4) <= '1';
		end if;
	end process;
--------------------------

-- bit "4", odd timeslice
--------------------------
	process(CLR_OD2, Tinp10(4))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(4) <= '0';
		elsif (Tinp10(4)'event and Tinp10(4) = '0') then
			Odd_FT2(4) <= '1';
		end if;
	end process;
--------------------------

-- bit "5", even timeslice
--------------------------
	process(CLR_EV2, Tinp10(5))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(5) <= '0';
		elsif (Tinp10(5)'event and Tinp10(5) = '0') then
			Eve_FT2(5) <= '1';
		end if;
	end process;
--------------------------

-- bit "5", odd timeslice
--------------------------
	process(CLR_OD2, Tinp10(5))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(5) <= '0';
		elsif (Tinp10(5)'event and Tinp10(5) = '0') then
			Odd_FT2(5) <= '1';
		end if;
	end process;
--------------------------

-- bit "6", even timeslice
--------------------------
	process(CLR_EV2, Tinp10(6))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(6) <= '0';
		elsif (Tinp10(6)'event and Tinp10(6) = '0') then
			Eve_FT2(6) <= '1';
		end if;
	end process;
--------------------------

-- bit "6", odd timeslice
--------------------------
	process(CLR_OD2, Tinp10(6))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(6) <= '0';
		elsif (Tinp10(6)'event and Tinp10(6) = '0') then
			Odd_FT2(6) <= '1';
		end if;
	end process;
--------------------------

-- bit "7", even timeslice
--------------------------
	process(CLR_EV2, Tinp10(7))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(7) <= '0';
		elsif (Tinp10(7)'event and Tinp10(7) = '0') then
			Eve_FT2(7) <= '1';
		end if;
	end process;
--------------------------

-- bit "7", odd timeslice
--------------------------
	process(CLR_OD2, Tinp10(7))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(7) <= '0';
		elsif (Tinp10(7)'event and Tinp10(7) = '0') then
			Odd_FT2(7) <= '1';
		end if;
	end process;
--------------------------

-- bit "8", even timeslice
--------------------------
	process(CLR_EV2, Tinp11(0))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(8) <= '0';
		elsif (Tinp11(0)'event and Tinp11(0) = '0') then
			Eve_FT2(8) <= '1';
		end if;
	end process;
--------------------------

-- bit "8", odd timeslice
--------------------------
	process(CLR_OD2, Tinp11(0))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(8) <= '0';
		elsif (Tinp11(0)'event and Tinp11(0) = '0') then
			Odd_FT2(8) <= '1';
		end if;
	end process;
--------------------------

-- bit "9", even timeslice
--------------------------
	process(CLR_EV2, Tinp11(1))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(9) <= '0';
		elsif (Tinp11(1)'event and Tinp11(1) = '0') then
			Eve_FT2(9) <= '1';
		end if;
	end process;
--------------------------

-- bit "9", odd timeslice
--------------------------
	process(CLR_OD2, Tinp11(1))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(9) <= '0';
		elsif (Tinp11(1)'event and Tinp11(1) = '0') then
			Odd_FT2(9) <= '1';
		end if;
	end process;
--------------------------

-- bit "10", even timeslice
--------------------------
	process(CLR_EV2, Tinp11(2))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(10) <= '0';
		elsif (Tinp11(2)'event and Tinp11(2) = '0') then
			Eve_FT2(10) <= '1';
		end if;
	end process;
--------------------------

-- bit "10", odd timeslice
--------------------------
	process(CLR_OD2, Tinp11(2))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(10) <= '0';
		elsif (Tinp11(2)'event and Tinp11(2) = '0') then
			Odd_FT2(10) <= '1';
		end if;
	end process;
--------------------------

-- bit "11", even timeslice
--------------------------
	process(CLR_EV2, Tinp11(3))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(11) <= '0';
		elsif (Tinp11(3)'event and Tinp11(3) = '0') then
			Eve_FT2(11) <= '1';
		end if;
	end process;
--------------------------

-- bit "11", odd timeslice
--------------------------
	process(CLR_OD2, Tinp11(3))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(11) <= '0';
		elsif (Tinp11(3)'event and Tinp11(3) = '0') then
			Odd_FT2(11) <= '1';
		end if;
	end process;
--------------------------

-- bit "12", even timeslice
--------------------------
	process(CLR_EV2, Tinp11(4))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(12) <= '0';
		elsif (Tinp11(4)'event and Tinp11(4) = '0') then
			Eve_FT2(12) <= '1';
		end if;
	end process;
--------------------------

-- bit "12", odd timeslice
--------------------------
	process(CLR_OD2, Tinp11(4))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(12) <= '0';
		elsif (Tinp11(4)'event and Tinp11(4) = '0') then
			Odd_FT2(12) <= '1';
		end if;
	end process;
--------------------------

-- bit "13", even timeslice
--------------------------
	process(CLR_EV2, Tinp11(5))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(13) <= '0';
		elsif (Tinp11(5)'event and Tinp11(5) = '0') then
			Eve_FT2(13) <= '1';
		end if;
	end process;
--------------------------

-- bit "13", odd timeslice
--------------------------
	process(CLR_OD2, Tinp11(5))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(13) <= '0';
		elsif (Tinp11(5)'event and Tinp11(5) = '0') then
			Odd_FT2(13) <= '1';
		end if;
	end process;
--------------------------

-- bit "14", even timeslice
--------------------------
	process(CLR_EV2, Tinp11(6))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(14) <= '0';
		elsif (Tinp11(6)'event and Tinp11(6) = '0') then
			Eve_FT2(14) <= '1';
		end if;
	end process;
--------------------------

-- bit "14", odd timeslice
--------------------------
	process(CLR_OD2, Tinp11(6))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(14) <= '0';
		elsif (Tinp11(6)'event and Tinp11(6) = '0') then
			Odd_FT2(14) <= '1';
		end if;
	end process;
--------------------------

-- bit "15", even timeslice
--------------------------
	process(CLR_EV2, Tinp11(7))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(15) <= '0';
		elsif (Tinp11(7)'event and Tinp11(7) = '0') then
			Eve_FT2(15) <= '1';
		end if;
	end process;
--------------------------

-- bit "15", odd timeslice
--------------------------
	process(CLR_OD2, Tinp11(7))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(15) <= '0';
		elsif (Tinp11(7)'event and Tinp11(7) = '0') then
			Odd_FT2(15) <= '1';
		end if;
	end process;
--------------------------

-- bit "16", even timeslice
--------------------------
	process(CLR_EV2, Tinp30(0))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(16) <= '0';
		elsif (Tinp30(0)'event and Tinp30(0) = '0') then
			Eve_FT2(16) <= '1';
		end if;
	end process;
--------------------------

-- bit "16", odd timeslice
--------------------------
	process(CLR_OD2, Tinp30(0))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(16) <= '0';
		elsif (Tinp30(0)'event and Tinp30(0) = '0') then
			Odd_FT2(16) <= '1';
		end if;
	end process;
--------------------------

-- bit "17", even timeslice
--------------------------
	process(CLR_EV2, Tinp30(1))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(17) <= '0';
		elsif (Tinp30(1)'event and Tinp30(1) = '0') then
			Eve_FT2(17) <= '1';
		end if;
	end process;
--------------------------

-- bit "17", odd timeslice
--------------------------
	process(CLR_OD2, Tinp30(1))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(17) <= '0';
		elsif (Tinp30(1)'event and Tinp30(1) = '0') then
			Odd_FT2(17) <= '1';
		end if;
	end process;
--------------------------

-- bit "18", even timeslice
--------------------------
	process(CLR_EV2, Tinp30(2))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(18) <= '0';
		elsif (Tinp30(2)'event and Tinp30(2) = '0') then
			Eve_FT2(18) <= '1';
		end if;
	end process;
--------------------------

-- bit "18", odd timeslice
--------------------------
	process(CLR_OD2, Tinp30(2))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(18) <= '0';
		elsif (Tinp30(2)'event and Tinp30(2) = '0') then
			Odd_FT2(18) <= '1';
		end if;
	end process;
--------------------------

-- bit "19", even timeslice
--------------------------
	process(CLR_EV2, Tinp30(3))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(19) <= '0';
		elsif (Tinp30(3)'event and Tinp30(3) = '0') then
			Eve_FT2(19) <= '1';
		end if;
	end process;
--------------------------

-- bit "19", odd timeslice
--------------------------
	process(CLR_OD2, Tinp30(3))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(19) <= '0';
		elsif (Tinp30(3)'event and Tinp30(3) = '0') then
			Odd_FT2(19) <= '1';
		end if;
	end process;
--------------------------

-- bit "20", even timeslice
--------------------------
	process(CLR_EV2, Tinp30(4))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(20) <= '0';
		elsif (Tinp30(4)'event and Tinp30(4) = '0') then
			Eve_FT2(20) <= '1';
		end if;
	end process;
--------------------------

-- bit "20", odd timeslice
--------------------------
	process(CLR_OD2, Tinp30(4))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(20) <= '0';
		elsif (Tinp30(4)'event and Tinp30(4) = '0') then
			Odd_FT2(20) <= '1';
		end if;
	end process;
--------------------------

-- bit "21", even timeslice
--------------------------
	process(CLR_EV2, Tinp30(5))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(21) <= '0';
		elsif (Tinp30(5)'event and Tinp30(5) = '0') then
			Eve_FT2(21) <= '1';
		end if;
	end process;
--------------------------

-- bit "21", odd timeslice
--------------------------
	process(CLR_OD2, Tinp30(5))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(21) <= '0';
		elsif (Tinp30(5)'event and Tinp30(5) = '0') then
			Odd_FT2(21) <= '1';
		end if;
	end process;
--------------------------

-- bit "22", even timeslice
--------------------------
	process(CLR_EV2, Tinp30(6))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(22) <= '0';
		elsif (Tinp30(6)'event and Tinp30(6) = '0') then
			Eve_FT2(22) <= '1';
		end if;
	end process;
--------------------------

-- bit "22", odd timeslice
--------------------------
	process(CLR_OD2, Tinp30(6))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(22) <= '0';
		elsif (Tinp30(6)'event and Tinp30(6) = '0') then
			Odd_FT2(22) <= '1';
		end if;
	end process;
--------------------------

-- bit "23", even timeslice
--------------------------
	process(CLR_EV2, Tinp30(7))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(23) <= '0';
		elsif (Tinp30(7)'event and Tinp30(7) = '0') then
			Eve_FT2(23) <= '1';
		end if;
	end process;
--------------------------

-- bit "23", odd timeslice
--------------------------
	process(CLR_OD2, Tinp30(7))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(23) <= '0';
		elsif (Tinp30(7)'event and Tinp30(7) = '0') then
			Odd_FT2(23) <= '1';
		end if;
	end process;
--------------------------

-- bit "24", even timeslice
--------------------------
	process(CLR_EV2, Tinp31(0))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(24) <= '0';
		elsif (Tinp31(0)'event and Tinp31(0) = '0') then
			Eve_FT2(24) <= '1';
		end if;
	end process;
--------------------------

-- bit "24", odd timeslice
--------------------------
	process(CLR_OD2, Tinp31(0))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(24) <= '0';
		elsif (Tinp31(0)'event and Tinp31(0) = '0') then
			Odd_FT2(24) <= '1';
		end if;
	end process;
--------------------------

-- bit "25", even timeslice
--------------------------
	process(CLR_EV2, Tinp31(1))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(25) <= '0';
		elsif (Tinp31(1)'event and Tinp31(1) = '0') then
			Eve_FT2(25) <= '1';
		end if;
	end process;
--------------------------

-- bit "25", odd timeslice
--------------------------
	process(CLR_OD2, Tinp31(1))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(25) <= '0';
		elsif (Tinp31(1)'event and Tinp31(1) = '0') then
			Odd_FT2(25) <= '1';
		end if;
	end process;
--------------------------

-- bit "26", even timeslice
--------------------------
	process(CLR_EV2, Tinp31(2))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(26) <= '0';
		elsif (Tinp31(2)'event and Tinp31(2) = '0') then
			Eve_FT2(26) <= '1';
		end if;
	end process;
--------------------------

-- bit "26", odd timeslice
--------------------------
	process(CLR_OD2, Tinp31(2))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(26) <= '0';
		elsif (Tinp31(2)'event and Tinp31(2) = '0') then
			Odd_FT2(26) <= '1';
		end if;
	end process;
--------------------------

-- bit "27", even timeslice
--------------------------
	process(CLR_EV2, Tinp31(3))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(27) <= '0';
		elsif (Tinp31(3)'event and Tinp31(3) = '0') then
			Eve_FT2(27) <= '1';
		end if;
	end process;
--------------------------

-- bit "27", odd timeslice
--------------------------
	process(CLR_OD2, Tinp31(3))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(27) <= '0';
		elsif (Tinp31(3)'event and Tinp31(3) = '0') then
			Odd_FT2(27) <= '1';
		end if;
	end process;
--------------------------

-- bit "28", even timeslice
--------------------------
	process(CLR_EV2, Tinp31(4))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(28) <= '0';
		elsif (Tinp31(4)'event and Tinp31(4) = '0') then
			Eve_FT2(28) <= '1';
		end if;
	end process;
--------------------------

-- bit "28", odd timeslice
--------------------------
	process(CLR_OD2, Tinp31(4))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(28) <= '0';
		elsif (Tinp31(4)'event and Tinp31(4) = '0') then
			Odd_FT2(28) <= '1';
		end if;
	end process;
--------------------------

-- bit "29", even timeslice
--------------------------
	process(CLR_EV2, Tinp31(5))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(29) <= '0';
		elsif (Tinp31(5)'event and Tinp31(5) = '0') then
			Eve_FT2(29) <= '1';
		end if;
	end process;
--------------------------

-- bit "29", odd timeslice
--------------------------
	process(CLR_OD2, Tinp31(5))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(29) <= '0';
		elsif (Tinp31(5)'event and Tinp31(5) = '0') then
			Odd_FT2(29) <= '1';
		end if;
	end process;
--------------------------

-- bit "30", even timeslice
--------------------------
	process(CLR_EV2, Tinp31(6))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(30) <= '0';
		elsif (Tinp31(6)'event and Tinp31(6) = '0') then
			Eve_FT2(30) <= '1';
		end if;
	end process;
--------------------------

-- bit "30", odd timeslice
--------------------------
	process(CLR_OD2, Tinp31(6))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(30) <= '0';
		elsif (Tinp31(6)'event and Tinp31(6) = '0') then
			Odd_FT2(30) <= '1';
		end if;
	end process;
--------------------------

-- bit "31", even timeslice
--------------------------
	process(CLR_EV2, Tinp31(7))
	begin
		if (CLR_EV2 = '1') then
			Eve_FT2(31) <= '0';
		elsif (Tinp31(7)'event and Tinp31(7) = '0') then
			Eve_FT2(31) <= '1';
		end if;
	end process;
--------------------------

-- bit "31", odd timeslice
--------------------------
	process(CLR_OD2, Tinp31(7))
	begin
		if (CLR_OD2 = '1') then
			Odd_FT2(31) <= '0';
		elsif (Tinp31(7)'event and Tinp31(7) = '0') then
			Odd_FT2(31) <= '1';
		end if;
	end process;
--------------------------------------------

-- Time slice counter (Clock <-)
--------------------------------------------
	process(Clock)
	begin
		if (Clock'event and Clock = '0') then
			TMP_CN0 <= TMP_CN0 + 1;
		end if;
	end process;
--------------------------
	process(Clock, TMP_CN0)
	begin
		if (Clock'event and Clock ='1') then
			TMP_DL0 <= TMP_CN0;
		end if;
	end process;
--------------------------
--------------------------
	process(Sync)
	begin
		if (Sync'event and Sync = '0') then
			TMP_CN2 <= TMP_CN2 + 1;
		end if;
	end process;
--------------------------
	process(Sync, TMP_CN2)
	begin
		if (Sync'event and Sync ='1') then
			TMP_DL2 <= TMP_CN2;
		end if;
	end process;
--------------------------------------------

-- Merge FTI_0 data from the even
-- and odd clock periods (Clock ->)
--------------------------------------------
	process(Clock, TMP_CN0, Eve_FT0, Odd_FT0)
	begin
		if (Clock'event and Clock = '1') then
			if (TMP_CN0 = 1) then
				Basket <= Eve_FT0;
			else
				Basket <= Odd_FT0;
			end if;
		end if;
	end process;
--------------------------------------------

-- Merge FTI_2 data from the even
-- and odd clock periods (Sync ->)
--------------------------------------------
	process(Sync, TMP_CN2, Eve_FT2, Odd_FT2)
	begin
		if (Sync'event and Sync = '1') then
			if (TMP_CN2 = 1) then
				Bucket <= Eve_FT2;
			else
				Bucket <= Odd_FT2;
			end if;
		end if;
	end process;
--------------------------------------------

-- Clear even time slice (Clock <-)
--------------------------------------------
	process(TMP_DL0, Clock)
	begin
		if (TMP_DL0 = 0) then
			CLR_Ev0 <= '0';
		elsif (Clock'event and Clock = '0') then
			CLR_Ev0 <= '1';
		end if;
	end process;
--------------------------------------------

-- Clear odd time slice (Clock <-)
--------------------------------------------
	process(TMP_DL0, Clock)
	begin
		if (TMP_DL0 = 1) then
			CLR_Od0 <= '0';
		elsif (Clock'event and Clock = '0') then
			CLR_Od0 <= '1';
		end if;
	end process;
--------------------------------------------

-- Clear even time slice (Sync <-)
--------------------------------------------
	process(TMP_DL2, Sync)
	begin
		if (TMP_DL2 = 0) then
			CLR_Ev2 <= '0';
		elsif (Sync'event and Sync = '0') then
			CLR_Ev2 <= '1';
		end if;
	end process;
--------------------------------------------

-- Clear odd time slice (Sync <-)
--------------------------------------------
	process(TMP_DL2, Sync)
	begin
		if (TMP_DL2 = 1) then
			CLR_Od2 <= '0';
		elsif (Sync'event and Sync = '0') then
			CLR_Od2 <= '1';
		end if;
	end process;
--------------------------------------------

-- Pipeline counter (Clock ->)
--------------------------------------------
	process(Clock)
	begin
		if (Clock'event and Clock = '1') then
			PIP_CNT <= PIP_CNT + 1;
		end if;
	end process;
--------------------------------------------

-- Readout counters (Clock <-)
--------------------------------------------
	process(Clock, PIP_CNT, DEL_FT0, DEL_FT2)
	begin
		if (Clock'event and Clock = '0') then
			FT0_CNT <= PIP_CNT - BIT4_to_NUM(DEL_FT0);
			FT2_CNT <= PIP_CNT - BIT4_to_NUM(DEL_FT2);
		end if;
	end process;
--------------------------------------------

-- Data pipelining (Clock <-)
--------------------------------------------
	process(Clock, PIP_CNT, Basket, Bucket)
	begin
		if (Clock'event and Clock = '0') then
			case PIP_CNT is
				when 0 =>
					PIP_000 <= Basket;
					PIP_200 <= Bucket;
				when 1 =>
					PIP_001 <= Basket;
					PIP_201 <= Bucket;
				when 2 =>
					PIP_002 <= Basket;
					PIP_202 <= Bucket;
				when 3 =>
					PIP_003 <= Basket;
					PIP_203 <= Bucket;
				when 4 =>
					PIP_004 <= Basket;
					PIP_204 <= Bucket;
				when 5 =>
					PIP_005 <= Basket;
					PIP_205 <= Bucket;
				when 6 =>
					PIP_006 <= Basket;
					PIP_206 <= Bucket;
				when 7 =>
					PIP_007 <= Basket;
					PIP_207 <= Bucket;
				when 8 =>
					PIP_008 <= Basket;
					PIP_208 <= Bucket;
				when 9 =>
					PIP_009 <= Basket;
					PIP_209 <= Bucket;
				when 10 =>
					PIP_010 <= Basket;
					PIP_210 <= Bucket;
				when 11 =>
					PIP_011 <= Basket;
					PIP_211 <= Bucket;
				when 12 =>
					PIP_012 <= Basket;
					PIP_212 <= Bucket;
				when 13 =>
					PIP_013 <= Basket;
					PIP_213 <= Bucket;
				when 14 =>
					PIP_014 <= Basket;
					PIP_214 <= Bucket;
				when 15 =>
					PIP_015 <= Basket;
					PIP_215 <= Bucket;
				when others =>
					null;
			end case;
		end if;
	end process;
--------------------------------------------

-- Select output data for the FTI_0
--------------------------------------------
	process(Clock, FT0_CNT,
			PIP_000, PIP_001, PIP_002, PIP_003,
			PIP_004, PIP_005, PIP_006, PIP_007,
			PIP_008, PIP_009, PIP_010, PIP_011,
			PIP_012, PIP_013, PIP_014, PIP_015)
	begin
		if (Clock'event and Clock = '1') then
			case FT0_CNT is
				when 0 =>
					FT0_DAT <= PIP_000;
				when 1 =>
					FT0_DAT <= PIP_001;
				when 2 =>
					FT0_DAT <= PIP_002;
				when 3 =>
					FT0_DAT <= PIP_003;
				when 4 =>
					FT0_DAT <= PIP_004;
				when 5 =>
					FT0_DAT <= PIP_005;
				when 6 =>
					FT0_DAT <= PIP_006;
				when 7 =>
					FT0_DAT <= PIP_007;
				when 8 =>
					FT0_DAT <= PIP_008;
				when 9 =>
					FT0_DAT <= PIP_009;
				when 10 =>
					FT0_DAT <= PIP_010;
				when 11 =>
					FT0_DAT <= PIP_011;
				when 12 =>
					FT0_DAT <= PIP_012;
				when 13 =>
					FT0_DAT <= PIP_013;
				when 14 =>
					FT0_DAT <= PIP_014;
				when others =>
					FT0_DAT <= PIP_015;
			end case;
		end if;
	end process;
--------------------------------------------

-- Select output data for the FTI_2
--------------------------------------------
	process(Clock, FT2_CNT,
			PIP_200, PIP_201, PIP_202, PIP_203,
			PIP_204, PIP_205, PIP_206, PIP_207,
			PIP_208, PIP_209, PIP_210, PIP_211,
			PIP_212, PIP_213, PIP_214, PIP_215)
	begin
		if (Clock'event and Clock = '1') then
			case FT2_CNT is
				when 0 =>
					FT2_DAT <= PIP_200;
				when 1 =>
					FT2_DAT <= PIP_201;
				when 2 =>
					FT2_DAT <= PIP_202;
				when 3 =>
					FT2_DAT <= PIP_203;
				when 4 =>
					FT2_DAT <= PIP_204;
				when 5 =>
					FT2_DAT <= PIP_205;
				when 6 =>
					FT2_DAT <= PIP_206;
				when 7 =>
					FT2_DAT <= PIP_207;
				when 8 =>
					FT2_DAT <= PIP_208;
				when 9 =>
					FT2_DAT <= PIP_209;
				when 10 =>
					FT2_DAT <= PIP_210;
				when 11 =>
					FT2_DAT <= PIP_211;
				when 12 =>
					FT2_DAT <= PIP_212;
				when 13 =>
					FT2_DAT <= PIP_213;
				when 14 =>
					FT2_DAT <= PIP_214;
				when others =>
					FT2_DAT <= PIP_215;
			end case;
		end if;
	end process;
--------------------------------------------

-- FTI_0 quadrants - to be checked
--------------------------------------------
	FT0_SEG(0) <= FT0_DAT(5)  or FT0_DAT(4)  or FT0_DAT(3)  or FT0_DAT(2) or  -- inner ring
				  FT0_DAT(12) or FT0_DAT(11) or FT0_DAT(10) or FT0_DAT(9);	  -- outer ring

	FT0_SEG(1) <= FT0_DAT(26) or FT0_DAT(25) or FT0_DAT(24) or FT0_DAT(23) or -- inner ring
				  FT0_DAT(22) or FT0_DAT(21) or FT0_DAT(20) or FT0_DAT(19);   -- outer ring

	FT0_SEG(2) <= FT0_DAT(31) or FT0_DAT(29) or FT0_DAT(28) or FT0_DAT(27) or -- inner ring
				  FT0_DAT(30) or FT0_DAT(18) or FT0_DAT(17) or FT0_DAT(16);	  -- outer ring

	FT0_SEG(3) <= FT0_DAT(8)  or FT0_DAT(7)  or FT0_DAT(6)  or FT0_DAT(0) or  -- inner ring
				  FT0_DAT(15) or FT0_DAT(14) or FT0_DAT(13) or FT0_DAT(1);	  -- outer ring
--------------------------------------------

-- FTI_2 quadrants with respect
-- to the H1 coordinates - OK
--------------------------------------------
	FT2_SEG(0) <= FT2_DAT(31) or FT2_DAT(30) or FT2_DAT(29) or FT2_DAT(28) or -- inner ring
				  FT2_DAT(15) or FT2_DAT(14) or FT2_DAT(13) or FT2_DAT(12);	  -- outer ring

	FT2_SEG(1) <= FT2_DAT(19) or FT2_DAT(18) or FT2_DAT(17) or FT2_DAT(16) or -- inner ring
				  FT2_DAT(3)  or FT2_DAT(2)  or FT2_DAT(1)  or FT2_DAT(0);	  -- outer ring

	FT2_SEG(2) <= FT2_DAT(23) or FT2_DAT(22) or FT2_DAT(21) or FT2_DAT(20) or -- inner ring
				  FT2_DAT(7)  or FT2_DAT(6)  or FT2_DAT(5)  or FT2_DAT(4);	  -- outer ring

	FT2_SEG(3) <= FT2_DAT(27) or FT2_DAT(26) or FT2_DAT(25) or FT2_DAT(24) or -- inner ring
				  FT2_DAT(11) or FT2_DAT(10) or FT2_DAT(9)  or FT2_DAT(8);	  -- outer ring
--------------------------------------------

-- FST trigger matching the
-- FTI_0 and FTI_2 quadrants
--------------------------------------------
	FST_TRG <= (FT0_SEG(0) and FT2_SEG(0)) or (FT0_SEG(1) and FT2_SEG(1)) or
			   (FT0_SEG(2) and FT2_SEG(2)) or (FT0_SEG(3) and FT2_SEG(3));
--------------------------------------------

-- Global OR for the T0 searches
--------------------------------------------
	FT0_GLB <= FT0_SEG(0) or FT0_SEG(1) or FT0_SEG(2) or FT0_SEG(3);
	FT2_GLB <= FT2_SEG(0) or FT2_SEG(1) or FT2_SEG(2) or FT2_SEG(3);
--------------------------------------------

-- Normalizing interval 0.8 s
--------------------------------------------
	process(Clock)
	begin
		if (Clock'event and Clock = '0') then
			Timer <= Timer + 1;
		end if;
	end process;
--------------------------------------------

-- Enable data collection (Clock ->)
--------------------------------------------
	process(Clock, Timer, Firewood)
	begin
		if (Clock'event and Clock = '1') then
			if (Timer = 0 or 8388575 <= Firewood) then
				Collect <= '0';
			elsif (Timer = 7) then
				Collect <= '1';
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Keep collected data (Clock ->)
--------------------------------------------
	process(Clock, Timer)
	begin
		if (Clock'event and Clock = '1') then
			case Timer is
				when 2 =>
					Rescue <= '1';
				when 3 =>
					Rescue <= '0';
				when others =>
					null;
			end case;
		end if;
	end process;
--------------------------------------------

-- Clear buffers (Clock ->)
--------------------------------------------
	process(Clock, Timer)
	begin
		if (Clock'event and Clock = '1') then
			case Timer is
				when 5 =>
					Worker <= '1';
				when 6 =>
					Worker <= '0';
				when others =>
					null;
			end case;
		end if;
	end process;
--------------------------------------------

-- Hit counter (Clock <-)
--------------------------------------------
	process(Clock, Worker, Collect, Basket)
	begin
		if (Clock'event and Clock = '0') then
			if (Worker = '1') then
				Firewood <= 0;
			elsif (Collect = '1') then
				Firewood <= Firewood + SUM_of_ONES_32(Basket);
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Latching the frequency value (Clock ->)
--------------------------------------------
	process(Clock, Rescue, ST_RATE, Firewood)
	begin
		if (Clock'event and Clock = '0') then
			if (Rescue = '1' and ST_RATE = '0') then
				Frequency <= Firewood;
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Computing the pedestal frequency
-- (1 kHz per register unit);
--------------------------------------------
	Pedestal <= 1000 * BIT4_to_NUM(PED_REG);
--------------------------------------------

-- The Oven must be a positive integer
-- to prevent division by zero. 
--------------------------------------------
	process(Frequency, Pedestal)
	begin
		if (Frequency <= Pedestal) then
			Oven <= 1;	-- Must not be zero;
		else
			Oven <= Frequency - Pedestal;
		end if;
	end process;
--------------------------------------------

-- Convert data format
--------------------------------------------
	DIV_DEN <= conv_std_logic_vector(Oven, 23);
	DIV_NUM <= "11111111111111111111111";
--------------------------------------------

-- Computing the number of loops
--------------------------------------------
	lpm_divide_component : lpm_divide
	generic map (
			lpm_widthn => 23,
			lpm_widthd => 23,
			lpm_type => "LPM_DIVIDE",
			lpm_nrepresentation => "UNSIGNED",
			lpm_hint => "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE",
			lpm_drepresentation => "UNSIGNED"
			)
	port map (
			denom => DIV_DEN,
			numer => DIV_NUM,
			quotient => DIV_RES,
			remain => DIV_REM
			);
--------------------------------------------

-- Keep the result of division
--------------------------------------------
	process(Clock, Worker, Frequency, Pedestal, DIV_RES)
	begin
		if (Clock'event and Clock = '0') then
			if (Worker  = '1') then
				if (Frequency <= Pedestal) then
					Result <= 1 + BIT23_to_NUM(DIV_RES);
				else
					Result <= BIT23_to_NUM(DIV_RES);
				end if;
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Frequency modulation
--------------------------------------------
	process(Clock, RAD_MON, Worker)
	begin
		if (Clock'event and Clock = '0') then
			if (RAD_MON = '1' or Worker = '1') then
				FRQ_CNT <= 0;
				RAD_RES <= '1';
			else
				FRQ_CNT <= FRQ_CNT + 1;
				RAD_RES <= '0';
			end if;
		end if;
	end process;
--------------------------------------------

-- Radiation monitor
--------------------------------------------
	process(Clock, FRQ_CNT, Result)
	begin
		if (Clock'event and Clock = '1') then
			if (FRQ_CNT = Result) then
				RAD_MON <= '1';
			else
				RAD_MON <= '0';
			end if;
		end if;
	end process;
--------------------------
	process(RAD_RES, RAD_MON)
	begin
		if (RAD_RES = '1') then
			RAD_OUT <= '0';
		elsif (RAD_MON'event and RAD_MON = '1') then
			RAD_OUT <= '1';
		end if;
	end process;
--------------------------------------------

-- keep the radiation level (Clock <-)
--------------------------------------------
	process(Clock, Worker, DIV_DEN)
	begin
		if (Clock'event and Clock = '0') then
			if (Worker = '1') then
				RAD_LEV(3 downto 0) <= DIV_DEN(21 downto 18);
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Gate for the indicator counter (Clock <-)
--------------------------------------------
	process(Clock, FST_TRG, EVT_CNT)
	begin
		if (Clock'event and Clock = '0') then
			if (FST_TRG = '1') then
				EVT_GTE <= '1';
			elsif (EVT_CNT = 1048575) then
				EVT_GTE <= '0';
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Indicator counter
--------------------------------------------
	process(Clock, EVT_GTE)
	begin
		if (Clock'event and Clock = '1') then
			if (EVT_GTE = '1') then
				EVT_CNT <= EVT_CNT + 1;
			else
				EVT_CNT <= 0;
			end if;
		end if;
	end process;
--------------------------------------------

-- Lighting the "Event" indicator
--------------------------------------------
	process(EVT_CNT)
	begin
		case EVT_CNT is
			when 1 to 131071 =>
				EVT_LED <= '0';
			when others =>
				EVT_LED <= '1';
		end case;
	end process;
--------------------------------------------

-- Radiation level warning
--------------------------------------------
	process(RAD_LEV)
	begin
		if (RAD_LEV /= "0000") then
			VTO_LED <= '0';
		else
			VTO_LED <= '1';
		end if;
	end process;
--------------------------------------------

-- Latch the PAD data
--------------------------------------------
	process(Keep, Tinp50(3 downto 0))
	begin
		if (Keep'event and Keep = '1') then
			Tbuf <= Tinp50(3 downto 0);
		end if;
	end process;
--------------------------------------------

-- synchronize PAD output
--------------------------------------------
	process(Clock, Tbuf)
	begin
		if (Clock'event and Clock = '1') then
			BST_TRG <= Tbuf(0) or Tbuf(1);
			BST_LNG <= Tbuf(2);
			BST_VTO <= Tbuf(3);
		end if;
	end process;
--------------------------------------------

-- Output data (Clock ->)
--------------------------------------------
	Mout(0) <= BST_TRG;
	Mout(1) <= BST_LNG;
	Mout(2) <= BST_VTO;
	Mout(3) <= FST_TRG;
	Mout(4) <= FT0_GLB;
	Mout(5) <= FT2_GLB;
	Mout(6) <= RAD_OUT;
	Mout(7) <= Tinp50(7); -- asynchronuous;
--------------------------------------------

end;