-- The BST trigger and the H1 radiation monitor based on
-- the silicon pad detectors. Trigger elements are routed
-- to the central trigger through the FTI_0/2 system.
--
--	BST trigger elements:
--	--------------------
--	Bit_0 - Track with projection onto the inner SpaCal;
--	Bit_1 - Track with projection onto the outer SpaCal;
--	Bit_2 - Calibration track parallel to the beampipe;
--	Bit_3 - Veto on high multiplicity of triggered pads;
--	Bit_4 - Reserved;
--	Bit_5 - Reserved
--	Bit_6 - Reserved;
--	Bit_7 - BST Pad radiation monitor;

-- The L1-data strobe has a fixed delay of 32 ns.

-- The current strategy has an identifier (hardware stamp),
-- whose description must be given in the H1 hypernews.

-- ID_1 word:
--------------------------
-- Data = 000D DDDD (binary);
--	DDDDD - day   (0...31);

-- ID_0 word:
--------------------------
-- Data = MMMM YYYY (binary);
--	 MMMM - month (0...12);
--	 YYYY - year  (0...15) keeping in mind 2000+;
--------------------------------------------


-- Channel mapping:
--
--	Board	Location	 Geometry	 Pin	Signal	Strobe	Status	 Mask
--------------------------------------------------------------------------
--	  0		Sector_0	     0-22.5	Tinp00	Trig00	TSTB0	LAM0(0)	 Bit_0
--			Sector_1	  22.5-45.0	Tinp01	Trig01	TSTB0	LAM0(0)	 Bit_1
--
--	  1		Sector_2	  45.0-67.5	Tinp20	Trig10	TSTB2	LAM0(1)	 Bit_2
--			Sector_3	  67.5-90.0	Tinp21	Trig11	TSTB2	LAM0(1)	 Bit_3
--
--	  2		Sector_4	 90.0-112.5	Tinp40	Trig20	TSTB4	LAM0(2)	 Bit_4
--			Sector_5	112.5-135.0	Tinp41	Trig21	TSTB4	LAM0(2)	 Bit_5
--
--	  3		Sector_10	225.0-247.5	Tinp10	Trig30	TSTB1	LAM1(0)	 Bit_0
--			Sector_11	247.5-270.0	Tinp11	Trig31	TSTB1	LAM1(0)	 Bit_1
--
--	  4		Sector_12	270.0-292.5	Tinp30	Trig40	TSTB3	LAM1(1)	 Bit_2
--			Sector_13	292.5-315.0	Tinp31	Trig41	TSTB3	LAM1(1)	 Bit_3
--
--	  5		Sector_14	315.0-337.5	Tinp50	Trig50	TSTB5	LAM1(2)	 Bit_4
--			Sector_15	337.5-360.0	Tinp51	Trig51	TSTB5	LAM1(2)	 Bit_5
--------------------------------------------------------------------------

-- The topological data (track geometries) and the generated
-- L1 trigger elements are pipelined for up to 32 consequent
-- bunch X-ngs. The T0-relevant data (selected by the 'x50'
-- register) are transmitted to the ACEX after the L1-keep.

-- The raw data packages are received from the frontend
-- in a certain timing slot after the L1-Keep announcement.
-- Beyond this window they and multiplexed one by one to
-- the ACEX chip .

-- Every BST Pad sector (22.5 deg.) can be disabled
-- from the trigger algorithm via registers 'x53' and
-- 'x54' and from the radiation monitor via registers
-- 'x55' and 'x56' of the serial interface. Default
-- register settings enable all sectors.

-- The radiation monitor has a pedestal subtraction
-- (0...255) kHz in steps of 1 kHz that allows for
-- the lower threshold settings for the trigger. The
-- subtracted value is kept in register 'x57'.

-- The radiation monitor rate could be stuck at the
-- current level through register 'x58' (Bit_0 = '1') in
-- order do not make HERA shift crew nervous during the
-- system reset. Be aware you may stuck the high value !

-- The radiation level is controlled through the
-- register x59. The measurement range is 0...5 MHz
-- with a 16 kHz resolution.

-- Slow control registers:
--------------------------
-- x50 Pipeline depth for the L1 topological
--	   data; sampling stops after the L1Keep
--     and the last word (the earliest in the
--     history) is sent to the APEX chip
--
-- x51 Default pipeline offset as
--     experimentally found delay:
--     Repeater Card -> Front-End ->
--     Repeater Card -> Master Card;
--
-- x52 HERA clock tuning in 10 steps of 10 ns;
--
-- x53 Trigger mask for sectors  0...5;
-- x54 Trigger mask for sectors 10...15;
-- x55 Rad. mon. mask for sect.  0...5;
-- x56 Rad. mon. mask for sect. 10...55;
--
-- x57 Number subtracted from rad. monitor rate;
-- x58 Bit_0 = '1' stucks the rad. monitor rate;
-- x59 Radiation level control;
--------------------------------------------

-- Mask format:
--------------------------
-- Data = 00MM MMMM (binary)
--  M_i - Front-end sector 'i' = 0...5 (10...15);
--------------------------------------------

-- Copyright I.Tsurin, University of Antwerpen,
-- on behalf of DESY.
--------------------------------------------

-- Preparing to the low energy run:

-- The new serial protocal is based on 27-bit messages,
-- each bit lasts 0.8 us For the 16 MHz VME-transmitter
-- (62.5 ns) the message length is equal to 350 + 4 clock
-- periods (13 per bit), for the 10 MHz front-end receiver
-- (96.0 ns) this corresponds to 230 clock periods (8.5 per
-- bit). Messages may closely follow each other (no pause
-- is required in between). The internal counters are reset
-- after each word transmission, thus the errors due to
-- the frequency mismatch do not accumulate.
--
-- Bit_0 in the data package is a wake-up signal. Single
-- event upsets can imitate beginning of the new frame, but
-- the messages are protected against corruption by the code
-- key 0x55 and by the parity bit.

-- Data frame for the serial interface (the PCA82C250T CAN
-- driver requires complementary signals)
--------------------------------------------
-- Bit_26 - wake up (TX='0' -> CAN='1' -> RX='0');
--
-- Bit_25 - permanent 0;
-- Bit_24 - permanent 1;
-- Bit_23 - permanent 0;
-- Bit_22 - permanent 1;
-- Bit_21 - permanent 0;
-- Bit_20 - permanent 1;
-- Bit_19 - permanent 0;
-- Bit_18 - permanent 1;
--
--          The code key 0x55 assures
--          validity of the next bit:
--
-- Bit_17 - write flag = 1;
--
-- Bit_16 - address Bit_6;
-- Bit_15 - address Bit_5;
-- Bit_14 - address Bit_4;
-- Bit_13 - address Bit_3;
-- Bit_12 - address Bit_2;
-- Bit_11 - address Bit_1;
-- Bit_10 - address Bit_0;
--
-- Bit_9  - data Bit_7;
-- Bit_8  - data Bit_6;
-- Bit_7  - data Bit_5;
-- Bit_6  - data Bit_4;
-- Bit_5  - data Bit_3;
-- Bit_4  - data Bit_2;
-- Bit_3  - data Bit_1;
-- Bit_2  - data Bit_0;
--
-- Bit_1  - odd parity flag set by controller
--          for bits 17...2 if the write flag = 1,
--          otherwise the parity bit is set for
--          bits 17...2 by the front-end;

-- Bit_0  - end of package (off line:
--          (TX='1' -> CAN='Z' -> RX='1')
--          reset timers making the next
--          wake-up possible without delay;
--------------------------------------------

-- Changed on 18.02.07 by I.Tsurin, DESY Zeuthen
--------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;

library LPM;
use LPM.LPM_components.all;

--	OK. Here the entity starts...
--------------------------------------------
entity L1trigger is
port(
	MSTB_SW: in std_logic_vector(3 downto 0);	-- spare (for use without VME access);

	DLY_OUT: out std_logic;						-- HERA clock routing to the delay line;
	DLY_TAP: in  std_logic_vector(9 downto 0);	-- Delayed HERA clock frequency;
	
	Rdata: out std_logic_vector(7 downto 0);	-- Raw data bus to the ACEX;
	RDstb: out std_logic;						-- Strobe for the raw data;

	TXD: out std_logic;							-- Serial interface output;
	RXD: in  std_logic;							-- Serial interface input;
	
	Enable: in std_logic;						-- "Pipeline enable" in the test mode;
	Clear: in std_logic;						-- "Fast clear" in the test mode;

	Tinp00: in std_logic_vector(7 downto 0);	-- |	
	Tinp01: in std_logic_vector(7 downto 0);	-- |
	Tinp10: in std_logic_vector(7 downto 0);	-- |
	Tinp11: in std_logic_vector(7 downto 0);	-- |
	Tinp20: in std_logic_vector(7 downto 0);	-- |
	Tinp21: in std_logic_vector(7 downto 0);	-- | Input trigger data from 6 repeaters;
	Tinp30: in std_logic_vector(7 downto 0);	-- |
	Tinp31: in std_logic_vector(7 downto 0);	-- |
	Tinp40: in std_logic_vector(7 downto 0);	-- |
	Tinp41: in std_logic_vector(7 downto 0);	-- |
	Tinp50: in std_logic_vector(7 downto 0);	-- |
	Tinp51: in std_logic_vector(7 downto 0);	-- |

	TSTB0: in std_logic;	-- Strobe for the trigger data from the 1st repeater;
	TSTB1: in std_logic;	-- Strobe for the trigger data from the 2nd repeater;
	TSTB2: in std_logic;	-- |
	TSTB3: in std_logic;	-- | ...
	TSTB4: in std_logic;	-- |
	TSTB5: in std_logic;	-- Strobe for the trigger data from the 6th repeater;
	
	Mout: out std_logic_vector(7 downto 0);		-- L1 output word;	
	MSTB: out std_logic;						-- L1 data strobe;
	
	HCLK: in std_logic;			-- HERA synchronization frequency;
	GEN: in std_logic;			-- Synchronization frequency in the test mode;
	
	BCK_PAN: in std_logic;		-- Jumper for the external controls;
	
	EVT_LED: out std_logic;		-- LED indicating the successful event;
	VTO_LED: out std_logic;		-- LED indicating the veto event;
	
	FCLR: in std_logic;			-- "Fast clear" signal from the H1 central trigger;
	PEN: in std_logic;			-- "Pipeline enable" from the H1 central triger;
	
	LAM0: in std_logic_vector(2 downto 0); 	-- Frontend Alteras download status;
	LAM1: in std_logic_vector(2 downto 0)	-- Frontend Alteras download status;
	);

	attribute pinnum: string;

	attribute pinnum of MSTB_SW: signal is "7,4,3,2";		
	attribute pinnum of DLY_OUT: signal is "8";
	attribute pinnum of DLY_TAP: signal is "41,40,20,18,17,16,13,11,10,9";
	
	attribute pinnum of Rdata: signal is "43,44,46,47,53,54,55,57";
	attribute pinnum of RDstb: signal is "49";

	attribute pinnum of RXD: signal is "48";
	attribute pinnum of TXD: signal is "50";
	
	attribute pinnum of Enable: signal is "58";
	attribute pinnum of Clear: signal is "59";

	attribute pinnum of Tinp00: signal is "184,183,182,181,180,178,174,173";
	attribute pinnum of Tinp01: signal is "195,192,191,190,189,187,186,185";
	attribute pinnum of Tinp10: signal is "204,203,202,201,200,198,197,196";
	attribute pinnum of Tinp11: signal is "220,219,217,216,215,207,206,205";
	attribute pinnum of Tinp20: signal is "231,230,226,225,224,223,222,221";
	attribute pinnum of Tinp21: signal is "239,238,237,236,235,234,233,232";
	attribute pinnum of Tinp30: signal is "69,68,66,65,64,63,62,61";
	attribute pinnum of Tinp31: signal is "80,79,77,76,75,74,71,70";
	attribute pinnum of Tinp40: signal is "96,95,94,85,84,83,82,81";
	attribute pinnum of Tinp41: signal is "105,104,103,102,101,100,99,98";
	attribute pinnum of Tinp50: signal is "116,115,114,113,112,111,110,109";
	attribute pinnum of Tinp51: signal is "126,125,124,123,121,119,118,117";

	attribute pinnum of TSTB0: signal is "209";
	attribute pinnum of TSTB1: signal is "212";
	attribute pinnum of TSTB2: signal is "31";
	attribute pinnum of TSTB3: signal is "34";
	attribute pinnum of TSTB4: signal is "88";
	attribute pinnum of TSTB5: signal is "91";
	
	attribute pinnum of Mout: signal is "129,130,131,133,134,135,136,138";
	attribute pinnum of MSTB: signal is "143";
	
	attribute pinnum of HCLK: signal is "151";
	attribute pinnum of GEN: signal is "154";
	
	attribute pinnum of BCK_PAN: signal is "156";
	
	attribute pinnum of EVT_LED: signal is "157";
	attribute pinnum of VTO_LED: signal is "161";
	
	attribute pinnum of FCLR: signal is "160";
	attribute pinnum of PEN: signal is "163";
	
	attribute pinnum of LAM0: signal is "169,166,164";
	attribute pinnum of LAM1: signal is "172,171,170";

	end;

architecture behavior of L1trigger is

-- Initialization
--------------------------------------------
	signal DUM_RES: std_logic;
	signal RES_PUL: std_logic;
	signal RES_DEL: std_logic;
	signal INI_CNT: natural range 0 to 524287;
--------------------------------------------

-- Communication tools
--------------------------------------------
	signal FED_CNT: natural range 0 to 511;
	signal IAM_BSY: std_logic;
	signal FED_END: std_logic;
	signal FED_CLR: std_logic;
	signal Write: std_logic;

	signal COD_KEY: std_logic_vector(7 downto 0);
	signal BRD_ADR: std_logic_vector(7 downto 0);
	signal BRD_INP: std_logic_vector(7 downto 0);
	signal BRD_OUT: std_logic_vector(7 downto 0);

	signal PAR_INP: std_logic;
	signal PAR_OUT: std_logic;
	signal PAR_CMI: std_logic;
--------------------------------------------

-- Control registers
--------------------------------------------
	signal TRG_RG0: std_logic_vector(5 downto 0);
	signal TRG_RG1: std_logic_vector(5 downto 0);
	signal MON_RG0: std_logic_vector(5 downto 0);
	signal MON_RG1: std_logic_vector(5 downto 0);
	signal PED_REG: std_logic_vector(7 downto 0);
	signal ST_RATE: std_logic;
--------------------------------------------

-- Steering signals
--------------------------------------------
	signal CLK_REG: std_logic_vector(3 downto 0);

	signal Oscillator: std_logic;
	signal Permission: std_logic;
	signal Fast_Reset: std_logic;

	signal SYN_SEL: std_logic;
	signal PEN_SEL: std_logic;
	signal CLR_SEL: std_logic;

	signal Gate: std_logic;
	signal Clock: std_logic;
	signal L1Keep: std_logic;

	signal TCLK_CNT: natural range 0 to 15;
	signal MSTB_CNT: natural range 0 to 15;
	signal MSTB_VAL: natural range 0 to 15;
--------------------------------------------

-- Auxiliary signals
--------------------------------------------
	signal PEN_TL0: std_logic;
	signal PEN_TL1: std_logic;
	signal PEN_TL2: std_logic;
	signal PEN_TL3: std_logic;
	signal PEN_TL4: std_logic;
	signal PEN_TL5: std_logic;
	signal PEN_TL6: std_logic;
	signal PEN_TL7: std_logic;
	signal PEN_TL8: std_logic;
	signal PEN_TL9: std_logic;

	signal CLR_TL0: std_logic;
	signal CLR_TL1: std_logic;
	signal CLR_TL2: std_logic;
	signal CLR_TL3: std_logic;
	signal CLR_TL4: std_logic;
	signal CLR_TL5: std_logic;
	signal CLR_TL6: std_logic;
	signal CLR_TL7: std_logic;
	signal CLR_TL8: std_logic;
	signal CLR_TL9: std_logic;
	
	signal TRHF_SYN: std_logic;
	signal TRHR_SYN: std_logic;
--------------------------------------------

-- Input data registers
--------------------------------------------
	signal Temp00: std_logic_vector(7 downto 0);	
	signal Temp01: std_logic_vector(7 downto 0);
	signal Temp10: std_logic_vector(7 downto 0);
	signal Temp11: std_logic_vector(7 downto 0);
	signal Temp20: std_logic_vector(7 downto 0);
	signal Temp21: std_logic_vector(7 downto 0);

	signal Temp30: std_logic_vector(7 downto 0);
	signal Temp31: std_logic_vector(7 downto 0);
	signal Temp40: std_logic_vector(7 downto 0);
	signal Temp41: std_logic_vector(7 downto 0);
	signal Temp50: std_logic_vector(7 downto 0);
	signal Temp51: std_logic_vector(7 downto 0);

	signal Pass00: std_logic_vector(7 downto 0);	
	signal Pass01: std_logic_vector(7 downto 0);
	signal Pass10: std_logic_vector(7 downto 0);
	signal Pass11: std_logic_vector(7 downto 0);
	signal Pass20: std_logic_vector(7 downto 0);
	signal Pass21: std_logic_vector(7 downto 0);

	signal Pass30: std_logic_vector(7 downto 0);
	signal Pass31: std_logic_vector(7 downto 0);
	signal Pass40: std_logic_vector(7 downto 0);
	signal Pass41: std_logic_vector(7 downto 0);
	signal Pass50: std_logic_vector(7 downto 0);
	signal Pass51: std_logic_vector(7 downto 0);

	signal Trig00: std_logic_vector(6 downto 0);	
	signal Trig01: std_logic_vector(6 downto 0);
	signal Trig10: std_logic_vector(6 downto 0);
	signal Trig11: std_logic_vector(6 downto 0);
	signal Trig20: std_logic_vector(6 downto 0);
	signal Trig21: std_logic_vector(6 downto 0);

	signal Trig30: std_logic_vector(6 downto 0);
	signal Trig31: std_logic_vector(6 downto 0);
	signal Trig40: std_logic_vector(6 downto 0);
	signal Trig41: std_logic_vector(6 downto 0);
	signal Trig50: std_logic_vector(6 downto 0);
	signal Trig51: std_logic_vector(6 downto 0);
	
	alias Num00: std_logic_vector(3 downto 0) is Trig00(3 downto 0);
	alias Num01: std_logic_vector(3 downto 0) is Trig01(3 downto 0);
	alias Num10: std_logic_vector(3 downto 0) is Trig10(3 downto 0);
	alias Num11: std_logic_vector(3 downto 0) is Trig11(3 downto 0);
	alias Num20: std_logic_vector(3 downto 0) is Trig20(3 downto 0);
	alias Num21: std_logic_vector(3 downto 0) is Trig21(3 downto 0);

	alias Num30: std_logic_vector(3 downto 0) is Trig30(3 downto 0);
	alias Num31: std_logic_vector(3 downto 0) is Trig31(3 downto 0);
	alias Num40: std_logic_vector(3 downto 0) is Trig40(3 downto 0);
	alias Num41: std_logic_vector(3 downto 0) is Trig41(3 downto 0);
	alias Num50: std_logic_vector(3 downto 0) is Trig50(3 downto 0);
	alias Num51: std_logic_vector(3 downto 0) is Trig51(3 downto 0);

	signal HM_VECT: std_logic_vector(11 downto 0);
	signal NSECT: natural range 0 to 15;

	signal INT_TRC: std_logic_vector(11 downto 0);
	signal OUT_TRC: std_logic_vector(11 downto 0);
	signal LT_VECT: std_logic_vector(11 downto 0);
--------------------------------------------

-- Buffered trigger signals
--------------------------------------------
	signal TSP_INN: std_logic;
	signal TSP_OUT: std_logic;
	signal LNG_TRK: std_logic;
	signal BST_VTO: std_logic;
--------------------------------------------

-- Topological data pipeline
--------------------------------------------
	signal L1K_DEL: std_logic;

	signal PIP_C00: natural range 0 to 31;
	signal PIP_C01: natural range 0 to 31;
	signal PIP_C02: natural range 0 to 31;
	signal PIP_C03: natural range 0 to 31;
	signal PIP_C04: natural range 0 to 31;
	signal PIP_C05: natural range 0 to 31;
	signal PIP_C10: natural range 0 to 31;
	signal PIP_C11: natural range 0 to 31;
	signal PIP_C12: natural range 0 to 31;
	signal PIP_C13: natural range 0 to 31;
	signal PIP_C14: natural range 0 to 31;
	signal PIP_C15: natural range 0 to 31;
	signal PIP_CL1: natural range 0 to 31;

	signal PIP_S00: natural range 0 to 31;
	signal PIP_S01: natural range 0 to 31;
	signal PIP_S02: natural range 0 to 31;
	signal PIP_S03: natural range 0 to 31;
	signal PIP_S04: natural range 0 to 31;
	signal PIP_S05: natural range 0 to 31;
	signal PIP_S10: natural range 0 to 31;
	signal PIP_S11: natural range 0 to 31;
	signal PIP_S12: natural range 0 to 31;
	signal PIP_S13: natural range 0 to 31;
	signal PIP_S14: natural range 0 to 31;
	signal PIP_S15: natural range 0 to 31;
	signal PIP_SL1: natural range 0 to 31;

	signal Answer: std_logic_vector(3 downto 0);
	signal Resque: std_logic_vector(3 downto 0);

	signal P00_00: std_logic_vector(6 downto 0);
	signal P00_01: std_logic_vector(6 downto 0);
	signal P00_02: std_logic_vector(6 downto 0);
	signal P00_03: std_logic_vector(6 downto 0);
	signal P00_04: std_logic_vector(6 downto 0);
	signal P00_05: std_logic_vector(6 downto 0);
	signal P00_10: std_logic_vector(6 downto 0);
	signal P00_11: std_logic_vector(6 downto 0);
	signal P00_12: std_logic_vector(6 downto 0);
	signal P00_13: std_logic_vector(6 downto 0);
	signal P00_14: std_logic_vector(6 downto 0);
	signal P00_15: std_logic_vector(6 downto 0);

	signal P01_00: std_logic_vector(6 downto 0);
	signal P01_01: std_logic_vector(6 downto 0);
	signal P01_02: std_logic_vector(6 downto 0);
	signal P01_03: std_logic_vector(6 downto 0);
	signal P01_04: std_logic_vector(6 downto 0);
	signal P01_05: std_logic_vector(6 downto 0);
	signal P01_10: std_logic_vector(6 downto 0);
	signal P01_11: std_logic_vector(6 downto 0);
	signal P01_12: std_logic_vector(6 downto 0);
	signal P01_13: std_logic_vector(6 downto 0);
	signal P01_14: std_logic_vector(6 downto 0);
	signal P01_15: std_logic_vector(6 downto 0);

	signal P02_00: std_logic_vector(6 downto 0);
	signal P02_01: std_logic_vector(6 downto 0);
	signal P02_02: std_logic_vector(6 downto 0);
	signal P02_03: std_logic_vector(6 downto 0);
	signal P02_04: std_logic_vector(6 downto 0);
	signal P02_05: std_logic_vector(6 downto 0);
	signal P02_10: std_logic_vector(6 downto 0);
	signal P02_11: std_logic_vector(6 downto 0);
	signal P02_12: std_logic_vector(6 downto 0);
	signal P02_13: std_logic_vector(6 downto 0);
	signal P02_14: std_logic_vector(6 downto 0);
	signal P02_15: std_logic_vector(6 downto 0);

	signal P03_00: std_logic_vector(6 downto 0);
	signal P03_01: std_logic_vector(6 downto 0);
	signal P03_02: std_logic_vector(6 downto 0);
	signal P03_03: std_logic_vector(6 downto 0);
	signal P03_04: std_logic_vector(6 downto 0);
	signal P03_05: std_logic_vector(6 downto 0);
	signal P03_10: std_logic_vector(6 downto 0);
	signal P03_11: std_logic_vector(6 downto 0);
	signal P03_12: std_logic_vector(6 downto 0);
	signal P03_13: std_logic_vector(6 downto 0);
	signal P03_14: std_logic_vector(6 downto 0);
	signal P03_15: std_logic_vector(6 downto 0);

	signal P04_00: std_logic_vector(6 downto 0);
	signal P04_01: std_logic_vector(6 downto 0);
	signal P04_02: std_logic_vector(6 downto 0);
	signal P04_03: std_logic_vector(6 downto 0);
	signal P04_04: std_logic_vector(6 downto 0);
	signal P04_05: std_logic_vector(6 downto 0);
	signal P04_10: std_logic_vector(6 downto 0);
	signal P04_11: std_logic_vector(6 downto 0);
	signal P04_12: std_logic_vector(6 downto 0);
	signal P04_13: std_logic_vector(6 downto 0);
	signal P04_14: std_logic_vector(6 downto 0);
	signal P04_15: std_logic_vector(6 downto 0);

	signal P05_00: std_logic_vector(6 downto 0);
	signal P05_01: std_logic_vector(6 downto 0);
	signal P05_02: std_logic_vector(6 downto 0);
	signal P05_03: std_logic_vector(6 downto 0);
	signal P05_04: std_logic_vector(6 downto 0);
	signal P05_05: std_logic_vector(6 downto 0);
	signal P05_10: std_logic_vector(6 downto 0);
	signal P05_11: std_logic_vector(6 downto 0);
	signal P05_12: std_logic_vector(6 downto 0);
	signal P05_13: std_logic_vector(6 downto 0);
	signal P05_14: std_logic_vector(6 downto 0);
	signal P05_15: std_logic_vector(6 downto 0);

	signal P06_00: std_logic_vector(6 downto 0);
	signal P06_01: std_logic_vector(6 downto 0);
	signal P06_02: std_logic_vector(6 downto 0);
	signal P06_03: std_logic_vector(6 downto 0);
	signal P06_04: std_logic_vector(6 downto 0);
	signal P06_05: std_logic_vector(6 downto 0);
	signal P06_10: std_logic_vector(6 downto 0);
	signal P06_11: std_logic_vector(6 downto 0);
	signal P06_12: std_logic_vector(6 downto 0);
	signal P06_13: std_logic_vector(6 downto 0);
	signal P06_14: std_logic_vector(6 downto 0);
	signal P06_15: std_logic_vector(6 downto 0);

	signal P07_00: std_logic_vector(6 downto 0);
	signal P07_01: std_logic_vector(6 downto 0);
	signal P07_02: std_logic_vector(6 downto 0);
	signal P07_03: std_logic_vector(6 downto 0);
	signal P07_04: std_logic_vector(6 downto 0);
	signal P07_05: std_logic_vector(6 downto 0);
	signal P07_10: std_logic_vector(6 downto 0);
	signal P07_11: std_logic_vector(6 downto 0);
	signal P07_12: std_logic_vector(6 downto 0);
	signal P07_13: std_logic_vector(6 downto 0);
	signal P07_14: std_logic_vector(6 downto 0);
	signal P07_15: std_logic_vector(6 downto 0);

	signal P08_00: std_logic_vector(6 downto 0);
	signal P08_01: std_logic_vector(6 downto 0);
	signal P08_02: std_logic_vector(6 downto 0);
	signal P08_03: std_logic_vector(6 downto 0);
	signal P08_04: std_logic_vector(6 downto 0);
	signal P08_05: std_logic_vector(6 downto 0);
	signal P08_10: std_logic_vector(6 downto 0);
	signal P08_11: std_logic_vector(6 downto 0);
	signal P08_12: std_logic_vector(6 downto 0);
	signal P08_13: std_logic_vector(6 downto 0);
	signal P08_14: std_logic_vector(6 downto 0);
	signal P08_15: std_logic_vector(6 downto 0);

	signal P09_00: std_logic_vector(6 downto 0);
	signal P09_01: std_logic_vector(6 downto 0);
	signal P09_02: std_logic_vector(6 downto 0);
	signal P09_03: std_logic_vector(6 downto 0);
	signal P09_04: std_logic_vector(6 downto 0);
	signal P09_05: std_logic_vector(6 downto 0);
	signal P09_10: std_logic_vector(6 downto 0);
	signal P09_11: std_logic_vector(6 downto 0);
	signal P09_12: std_logic_vector(6 downto 0);
	signal P09_13: std_logic_vector(6 downto 0);
	signal P09_14: std_logic_vector(6 downto 0);
	signal P09_15: std_logic_vector(6 downto 0);

	signal P10_00: std_logic_vector(6 downto 0);
	signal P10_01: std_logic_vector(6 downto 0);
	signal P10_02: std_logic_vector(6 downto 0);
	signal P10_03: std_logic_vector(6 downto 0);
	signal P10_04: std_logic_vector(6 downto 0);
	signal P10_05: std_logic_vector(6 downto 0);
	signal P10_10: std_logic_vector(6 downto 0);
	signal P10_11: std_logic_vector(6 downto 0);
	signal P10_12: std_logic_vector(6 downto 0);
	signal P10_13: std_logic_vector(6 downto 0);
	signal P10_14: std_logic_vector(6 downto 0);
	signal P10_15: std_logic_vector(6 downto 0);

	signal P11_00: std_logic_vector(6 downto 0);
	signal P11_01: std_logic_vector(6 downto 0);
	signal P11_02: std_logic_vector(6 downto 0);
	signal P11_03: std_logic_vector(6 downto 0);
	signal P11_04: std_logic_vector(6 downto 0);
	signal P11_05: std_logic_vector(6 downto 0);
	signal P11_10: std_logic_vector(6 downto 0);
	signal P11_11: std_logic_vector(6 downto 0);
	signal P11_12: std_logic_vector(6 downto 0);
	signal P11_13: std_logic_vector(6 downto 0);
	signal P11_14: std_logic_vector(6 downto 0);
	signal P11_15: std_logic_vector(6 downto 0);

	signal P12_00: std_logic_vector(6 downto 0);
	signal P12_01: std_logic_vector(6 downto 0);
	signal P12_02: std_logic_vector(6 downto 0);
	signal P12_03: std_logic_vector(6 downto 0);
	signal P12_04: std_logic_vector(6 downto 0);
	signal P12_05: std_logic_vector(6 downto 0);
	signal P12_10: std_logic_vector(6 downto 0);
	signal P12_11: std_logic_vector(6 downto 0);
	signal P12_12: std_logic_vector(6 downto 0);
	signal P12_13: std_logic_vector(6 downto 0);
	signal P12_14: std_logic_vector(6 downto 0);
	signal P12_15: std_logic_vector(6 downto 0);

	signal P13_00: std_logic_vector(6 downto 0);
	signal P13_01: std_logic_vector(6 downto 0);
	signal P13_02: std_logic_vector(6 downto 0);
	signal P13_03: std_logic_vector(6 downto 0);
	signal P13_04: std_logic_vector(6 downto 0);
	signal P13_05: std_logic_vector(6 downto 0);
	signal P13_10: std_logic_vector(6 downto 0);
	signal P13_11: std_logic_vector(6 downto 0);
	signal P13_12: std_logic_vector(6 downto 0);
	signal P13_13: std_logic_vector(6 downto 0);
	signal P13_14: std_logic_vector(6 downto 0);
	signal P13_15: std_logic_vector(6 downto 0);

	signal P14_00: std_logic_vector(6 downto 0);
	signal P14_01: std_logic_vector(6 downto 0);
	signal P14_02: std_logic_vector(6 downto 0);
	signal P14_03: std_logic_vector(6 downto 0);
	signal P14_04: std_logic_vector(6 downto 0);
	signal P14_05: std_logic_vector(6 downto 0);
	signal P14_10: std_logic_vector(6 downto 0);
	signal P14_11: std_logic_vector(6 downto 0);
	signal P14_12: std_logic_vector(6 downto 0);
	signal P14_13: std_logic_vector(6 downto 0);
	signal P14_14: std_logic_vector(6 downto 0);
	signal P14_15: std_logic_vector(6 downto 0);

	signal P15_00: std_logic_vector(6 downto 0);
	signal P15_01: std_logic_vector(6 downto 0);
	signal P15_02: std_logic_vector(6 downto 0);
	signal P15_03: std_logic_vector(6 downto 0);
	signal P15_04: std_logic_vector(6 downto 0);
	signal P15_05: std_logic_vector(6 downto 0);
	signal P15_10: std_logic_vector(6 downto 0);
	signal P15_11: std_logic_vector(6 downto 0);
	signal P15_12: std_logic_vector(6 downto 0);
	signal P15_13: std_logic_vector(6 downto 0);
	signal P15_14: std_logic_vector(6 downto 0);
	signal P15_15: std_logic_vector(6 downto 0);

	signal P16_00: std_logic_vector(6 downto 0);
	signal P16_01: std_logic_vector(6 downto 0);
	signal P16_02: std_logic_vector(6 downto 0);
	signal P16_03: std_logic_vector(6 downto 0);
	signal P16_04: std_logic_vector(6 downto 0);
	signal P16_05: std_logic_vector(6 downto 0);
	signal P16_10: std_logic_vector(6 downto 0);
	signal P16_11: std_logic_vector(6 downto 0);
	signal P16_12: std_logic_vector(6 downto 0);
	signal P16_13: std_logic_vector(6 downto 0);
	signal P16_14: std_logic_vector(6 downto 0);
	signal P16_15: std_logic_vector(6 downto 0);

	signal P17_00: std_logic_vector(6 downto 0);
	signal P17_01: std_logic_vector(6 downto 0);
	signal P17_02: std_logic_vector(6 downto 0);
	signal P17_03: std_logic_vector(6 downto 0);
	signal P17_04: std_logic_vector(6 downto 0);
	signal P17_05: std_logic_vector(6 downto 0);
	signal P17_10: std_logic_vector(6 downto 0);
	signal P17_11: std_logic_vector(6 downto 0);
	signal P17_12: std_logic_vector(6 downto 0);
	signal P17_13: std_logic_vector(6 downto 0);
	signal P17_14: std_logic_vector(6 downto 0);
	signal P17_15: std_logic_vector(6 downto 0);

	signal P18_00: std_logic_vector(6 downto 0);
	signal P18_01: std_logic_vector(6 downto 0);
	signal P18_02: std_logic_vector(6 downto 0);
	signal P18_03: std_logic_vector(6 downto 0);
	signal P18_04: std_logic_vector(6 downto 0);
	signal P18_05: std_logic_vector(6 downto 0);
	signal P18_10: std_logic_vector(6 downto 0);
	signal P18_11: std_logic_vector(6 downto 0);
	signal P18_12: std_logic_vector(6 downto 0);
	signal P18_13: std_logic_vector(6 downto 0);
	signal P18_14: std_logic_vector(6 downto 0);
	signal P18_15: std_logic_vector(6 downto 0);

	signal P19_00: std_logic_vector(6 downto 0);
	signal P19_01: std_logic_vector(6 downto 0);
	signal P19_02: std_logic_vector(6 downto 0);
	signal P19_03: std_logic_vector(6 downto 0);
	signal P19_04: std_logic_vector(6 downto 0);
	signal P19_05: std_logic_vector(6 downto 0);
	signal P19_10: std_logic_vector(6 downto 0);
	signal P19_11: std_logic_vector(6 downto 0);
	signal P19_12: std_logic_vector(6 downto 0);
	signal P19_13: std_logic_vector(6 downto 0);
	signal P19_14: std_logic_vector(6 downto 0);
	signal P19_15: std_logic_vector(6 downto 0);

	signal P20_00: std_logic_vector(6 downto 0);
	signal P20_01: std_logic_vector(6 downto 0);
	signal P20_02: std_logic_vector(6 downto 0);
	signal P20_03: std_logic_vector(6 downto 0);
	signal P20_04: std_logic_vector(6 downto 0);
	signal P20_05: std_logic_vector(6 downto 0);
	signal P20_10: std_logic_vector(6 downto 0);
	signal P20_11: std_logic_vector(6 downto 0);
	signal P20_12: std_logic_vector(6 downto 0);
	signal P20_13: std_logic_vector(6 downto 0);
	signal P20_14: std_logic_vector(6 downto 0);
	signal P20_15: std_logic_vector(6 downto 0);

	signal P21_00: std_logic_vector(6 downto 0);
	signal P21_01: std_logic_vector(6 downto 0);
	signal P21_02: std_logic_vector(6 downto 0);
	signal P21_03: std_logic_vector(6 downto 0);
	signal P21_04: std_logic_vector(6 downto 0);
	signal P21_05: std_logic_vector(6 downto 0);
	signal P21_10: std_logic_vector(6 downto 0);
	signal P21_11: std_logic_vector(6 downto 0);
	signal P21_12: std_logic_vector(6 downto 0);
	signal P21_13: std_logic_vector(6 downto 0);
	signal P21_14: std_logic_vector(6 downto 0);
	signal P21_15: std_logic_vector(6 downto 0);

	signal P22_00: std_logic_vector(6 downto 0);
	signal P22_01: std_logic_vector(6 downto 0);
	signal P22_02: std_logic_vector(6 downto 0);
	signal P22_03: std_logic_vector(6 downto 0);
	signal P22_04: std_logic_vector(6 downto 0);
	signal P22_05: std_logic_vector(6 downto 0);
	signal P22_10: std_logic_vector(6 downto 0);
	signal P22_11: std_logic_vector(6 downto 0);
	signal P22_12: std_logic_vector(6 downto 0);
	signal P22_13: std_logic_vector(6 downto 0);
	signal P22_14: std_logic_vector(6 downto 0);
	signal P22_15: std_logic_vector(6 downto 0);

	signal P23_00: std_logic_vector(6 downto 0);
	signal P23_01: std_logic_vector(6 downto 0);
	signal P23_02: std_logic_vector(6 downto 0);
	signal P23_03: std_logic_vector(6 downto 0);
	signal P23_04: std_logic_vector(6 downto 0);
	signal P23_05: std_logic_vector(6 downto 0);
	signal P23_10: std_logic_vector(6 downto 0);
	signal P23_11: std_logic_vector(6 downto 0);
	signal P23_12: std_logic_vector(6 downto 0);
	signal P23_13: std_logic_vector(6 downto 0);
	signal P23_14: std_logic_vector(6 downto 0);
	signal P23_15: std_logic_vector(6 downto 0);

	signal P24_00: std_logic_vector(6 downto 0);
	signal P24_01: std_logic_vector(6 downto 0);
	signal P24_02: std_logic_vector(6 downto 0);
	signal P24_03: std_logic_vector(6 downto 0);
	signal P24_04: std_logic_vector(6 downto 0);
	signal P24_05: std_logic_vector(6 downto 0);
	signal P24_10: std_logic_vector(6 downto 0);
	signal P24_11: std_logic_vector(6 downto 0);
	signal P24_12: std_logic_vector(6 downto 0);
	signal P24_13: std_logic_vector(6 downto 0);
	signal P24_14: std_logic_vector(6 downto 0);
	signal P24_15: std_logic_vector(6 downto 0);

	signal P25_00: std_logic_vector(6 downto 0);
	signal P25_01: std_logic_vector(6 downto 0);
	signal P25_02: std_logic_vector(6 downto 0);
	signal P25_03: std_logic_vector(6 downto 0);
	signal P25_04: std_logic_vector(6 downto 0);
	signal P25_05: std_logic_vector(6 downto 0);
	signal P25_10: std_logic_vector(6 downto 0);
	signal P25_11: std_logic_vector(6 downto 0);
	signal P25_12: std_logic_vector(6 downto 0);
	signal P25_13: std_logic_vector(6 downto 0);
	signal P25_14: std_logic_vector(6 downto 0);
	signal P25_15: std_logic_vector(6 downto 0);

	signal P26_00: std_logic_vector(6 downto 0);
	signal P26_01: std_logic_vector(6 downto 0);
	signal P26_02: std_logic_vector(6 downto 0);
	signal P26_03: std_logic_vector(6 downto 0);
	signal P26_04: std_logic_vector(6 downto 0);
	signal P26_05: std_logic_vector(6 downto 0);
	signal P26_10: std_logic_vector(6 downto 0);
	signal P26_11: std_logic_vector(6 downto 0);
	signal P26_12: std_logic_vector(6 downto 0);
	signal P26_13: std_logic_vector(6 downto 0);
	signal P26_14: std_logic_vector(6 downto 0);
	signal P26_15: std_logic_vector(6 downto 0);

	signal P27_00: std_logic_vector(6 downto 0);
	signal P27_01: std_logic_vector(6 downto 0);
	signal P27_02: std_logic_vector(6 downto 0);
	signal P27_03: std_logic_vector(6 downto 0);
	signal P27_04: std_logic_vector(6 downto 0);
	signal P27_05: std_logic_vector(6 downto 0);
	signal P27_10: std_logic_vector(6 downto 0);
	signal P27_11: std_logic_vector(6 downto 0);
	signal P27_12: std_logic_vector(6 downto 0);
	signal P27_13: std_logic_vector(6 downto 0);
	signal P27_14: std_logic_vector(6 downto 0);
	signal P27_15: std_logic_vector(6 downto 0);

	signal P28_00: std_logic_vector(6 downto 0);
	signal P28_01: std_logic_vector(6 downto 0);
	signal P28_02: std_logic_vector(6 downto 0);
	signal P28_03: std_logic_vector(6 downto 0);
	signal P28_04: std_logic_vector(6 downto 0);
	signal P28_05: std_logic_vector(6 downto 0);
	signal P28_10: std_logic_vector(6 downto 0);
	signal P28_11: std_logic_vector(6 downto 0);
	signal P28_12: std_logic_vector(6 downto 0);
	signal P28_13: std_logic_vector(6 downto 0);
	signal P28_14: std_logic_vector(6 downto 0);
	signal P28_15: std_logic_vector(6 downto 0);

	signal P29_00: std_logic_vector(6 downto 0);
	signal P29_01: std_logic_vector(6 downto 0);
	signal P29_02: std_logic_vector(6 downto 0);
	signal P29_03: std_logic_vector(6 downto 0);
	signal P29_04: std_logic_vector(6 downto 0);
	signal P29_05: std_logic_vector(6 downto 0);
	signal P29_10: std_logic_vector(6 downto 0);
	signal P29_11: std_logic_vector(6 downto 0);
	signal P29_12: std_logic_vector(6 downto 0);
	signal P29_13: std_logic_vector(6 downto 0);
	signal P29_14: std_logic_vector(6 downto 0);
	signal P29_15: std_logic_vector(6 downto 0);

	signal P30_00: std_logic_vector(6 downto 0);
	signal P30_01: std_logic_vector(6 downto 0);
	signal P30_02: std_logic_vector(6 downto 0);
	signal P30_03: std_logic_vector(6 downto 0);
	signal P30_04: std_logic_vector(6 downto 0);
	signal P30_05: std_logic_vector(6 downto 0);
	signal P30_10: std_logic_vector(6 downto 0);
	signal P30_11: std_logic_vector(6 downto 0);
	signal P30_12: std_logic_vector(6 downto 0);
	signal P30_13: std_logic_vector(6 downto 0);
	signal P30_14: std_logic_vector(6 downto 0);
	signal P30_15: std_logic_vector(6 downto 0);

	signal P31_00: std_logic_vector(6 downto 0);
	signal P31_01: std_logic_vector(6 downto 0);
	signal P31_02: std_logic_vector(6 downto 0);
	signal P31_03: std_logic_vector(6 downto 0);
	signal P31_04: std_logic_vector(6 downto 0);
	signal P31_05: std_logic_vector(6 downto 0);
	signal P31_10: std_logic_vector(6 downto 0);
	signal P31_11: std_logic_vector(6 downto 0);
	signal P31_12: std_logic_vector(6 downto 0);
	signal P31_13: std_logic_vector(6 downto 0);
	signal P31_14: std_logic_vector(6 downto 0);
	signal P31_15: std_logic_vector(6 downto 0);

	signal PIP_OUT00: std_logic_vector(6 downto 0);
	signal PIP_OUT01: std_logic_vector(6 downto 0);
	signal PIP_OUT02: std_logic_vector(6 downto 0);
	signal PIP_OUT03: std_logic_vector(6 downto 0);
	signal PIP_OUT04: std_logic_vector(6 downto 0);
	signal PIP_OUT05: std_logic_vector(6 downto 0);
	signal PIP_OUT10: std_logic_vector(6 downto 0);
	signal PIP_OUT11: std_logic_vector(6 downto 0);
	signal PIP_OUT12: std_logic_vector(6 downto 0);
	signal PIP_OUT13: std_logic_vector(6 downto 0);
	signal PIP_OUT14: std_logic_vector(6 downto 0);
	signal PIP_OUT15: std_logic_vector(6 downto 0);

	signal P00_L1: std_logic_vector(3 downto 0);
	signal P01_L1: std_logic_vector(3 downto 0);
	signal P02_L1: std_logic_vector(3 downto 0);
	signal P03_L1: std_logic_vector(3 downto 0);
	signal P04_L1: std_logic_vector(3 downto 0);
	signal P05_L1: std_logic_vector(3 downto 0);
	signal P06_L1: std_logic_vector(3 downto 0);
	signal P07_L1: std_logic_vector(3 downto 0);
	signal P08_L1: std_logic_vector(3 downto 0);
	signal P09_L1: std_logic_vector(3 downto 0);
	signal P10_L1: std_logic_vector(3 downto 0);
	signal P11_L1: std_logic_vector(3 downto 0);
	signal P12_L1: std_logic_vector(3 downto 0);
	signal P13_L1: std_logic_vector(3 downto 0);
	signal P14_L1: std_logic_vector(3 downto 0);
	signal P15_L1: std_logic_vector(3 downto 0);
	signal P16_L1: std_logic_vector(3 downto 0);
	signal P17_L1: std_logic_vector(3 downto 0);
	signal P18_L1: std_logic_vector(3 downto 0);
	signal P19_L1: std_logic_vector(3 downto 0);
	signal P20_L1: std_logic_vector(3 downto 0);
	signal P21_L1: std_logic_vector(3 downto 0);
	signal P22_L1: std_logic_vector(3 downto 0);
	signal P23_L1: std_logic_vector(3 downto 0);
	signal P24_L1: std_logic_vector(3 downto 0);
	signal P25_L1: std_logic_vector(3 downto 0);
	signal P26_L1: std_logic_vector(3 downto 0);
	signal P27_L1: std_logic_vector(3 downto 0);
	signal P28_L1: std_logic_vector(3 downto 0);
	signal P29_L1: std_logic_vector(3 downto 0);
	signal P30_L1: std_logic_vector(3 downto 0);
	signal P31_L1: std_logic_vector(3 downto 0);

	signal PIP_OUT: std_logic_vector(3 downto 0);
--------------------------------------------

-- Data cluster counter
--------------------------------------------
	signal DEP_REG: std_logic_vector(4 downto 0);
	signal OFF_REG: std_logic_vector(6 downto 0);

    signal PIP_DEP: natural range 0 to 31;
	signal PIP_OFF: natural range 0 to 127;
	signal CLS_CNT: natural range 0 to 127;

	signal CLS_GTE: std_logic;
	
	signal RDS_CLR: std_logic_vector(0 downto 0);
	signal STB_EVE: std_logic;
	signal STB_ODD: std_logic;
--------------------------------------------

-- Memory for the raw data
--------------------------------------------
	signal ID0_REG: std_logic_vector(7 downto 0);
	signal ID1_REG: std_logic_vector(7 downto 0);

	signal PRO_A0: std_logic_vector(7 downto 0);
	signal PRO_A1: std_logic_vector(7 downto 0);
	signal PRO_A2: std_logic_vector(7 downto 0);
	signal PRO_A3: std_logic_vector(7 downto 0);
	signal PRO_A4: std_logic_vector(7 downto 0);
	signal PRO_A5: std_logic_vector(7 downto 0);

	signal S00P0: std_logic_vector(7 downto 0);
	signal S00P1: std_logic_vector(7 downto 0);
	signal S00P2: std_logic_vector(7 downto 0);
	signal S00P3: std_logic_vector(7 downto 0);

	signal S01P0: std_logic_vector(7 downto 0);
	signal S01P1: std_logic_vector(7 downto 0);
	signal S01P2: std_logic_vector(7 downto 0);
	signal S01P3: std_logic_vector(7 downto 0);

	signal S02P0: std_logic_vector(7 downto 0);
	signal S02P1: std_logic_vector(7 downto 0);
	signal S02P2: std_logic_vector(7 downto 0);
	signal S02P3: std_logic_vector(7 downto 0);

	signal S03P0: std_logic_vector(7 downto 0);
	signal S03P1: std_logic_vector(7 downto 0);
	signal S03P2: std_logic_vector(7 downto 0);
	signal S03P3: std_logic_vector(7 downto 0);

	signal S04P0: std_logic_vector(7 downto 0);
	signal S04P1: std_logic_vector(7 downto 0);
	signal S04P2: std_logic_vector(7 downto 0);
	signal S04P3: std_logic_vector(7 downto 0);

	signal S05P0: std_logic_vector(7 downto 0);
	signal S05P1: std_logic_vector(7 downto 0);
	signal S05P2: std_logic_vector(7 downto 0);
	signal S05P3: std_logic_vector(7 downto 0);

	signal S10P0: std_logic_vector(7 downto 0);
	signal S10P1: std_logic_vector(7 downto 0);
	signal S10P2: std_logic_vector(7 downto 0);
	signal S10P3: std_logic_vector(7 downto 0);

	signal S11P0: std_logic_vector(7 downto 0);
	signal S11P1: std_logic_vector(7 downto 0);
	signal S11P2: std_logic_vector(7 downto 0);
	signal S11P3: std_logic_vector(7 downto 0);

	signal S12P0: std_logic_vector(7 downto 0);
	signal S12P1: std_logic_vector(7 downto 0);
	signal S12P2: std_logic_vector(7 downto 0);
	signal S12P3: std_logic_vector(7 downto 0);

	signal S13P0: std_logic_vector(7 downto 0);
	signal S13P1: std_logic_vector(7 downto 0);
	signal S13P2: std_logic_vector(7 downto 0);
	signal S13P3: std_logic_vector(7 downto 0);

	signal S14P0: std_logic_vector(7 downto 0);
	signal S14P1: std_logic_vector(7 downto 0);
	signal S14P2: std_logic_vector(7 downto 0);
	signal S14P3: std_logic_vector(7 downto 0);

	signal S15P0: std_logic_vector(7 downto 0);
	signal S15P1: std_logic_vector(7 downto 0);
	signal S15P2: std_logic_vector(7 downto 0);
	signal S15P3: std_logic_vector(7 downto 0);
--------------------------------------------

-- Radiation monitor variables
--------------------------------------------
	signal RM_Lock: std_logic;

	signal Basket0: natural range 0 to 8388607;
	signal Basket1: natural range 0 to 8388607;
	signal Basket2: natural range 0 to 8388607;
	signal Basket3: natural range 0 to 8388607;
	signal Basket4: natural range 0 to 8388607;
	signal Basket5: natural range 0 to 8388607;
	signal Basket6: natural range 0 to 8388607;
	signal Basket7: natural range 0 to 8388607;
	signal Basket8: natural range 0 to 8388607;
	signal Basket9: natural range 0 to 8388607;
	signal Basket10: natural range 0 to 8388607;
	signal Basket11: natural range 0 to 8388607;

	signal Firewood0: natural range 0 to 8388607;
	signal Firewood1: natural range 0 to 8388607;
	signal Firewood2: natural range 0 to 8388607;
	signal Firewood3: natural range 0 to 8388607;
	signal Firewood4: natural range 0 to 8388607;
	signal Firewood5: natural range 0 to 8388607;
	signal Firewood6: natural range 0 to 8388607;
	signal Firewood7: natural range 0 to 8388607;
	signal Firewood8: natural range 0 to 8388607;
	signal Firewood9: natural range 0 to 8388607;
	signal Firewood10: natural range 0 to 8388607;
	signal Firewood11: natural range 0 to 8388607;

	signal TIM_CNT: natural range 0 to 8388607;

	signal Collect: std_logic;
	signal Rescue: std_logic;
	signal Worker: std_logic;

	signal Frequency: natural range 0 to 8388607;
	signal Pedestal: natural range 0 to 8388607;
--------------------------------------------

-- frequency modulation variables
--------------------------------------------
	signal DIV_NUM: std_logic_vector(22 downto 0);
	signal DIV_DEN: std_logic_vector(22 downto 0);
	signal DIV_RES: std_logic_vector(22 downto 0);
	signal DIV_DUM: std_logic_vector(22 downto 0);

	signal Oven: natural range 0 to 8388607;
	signal Result: natural range 0 to 8388607;
	signal FRQ_CNT: natural range 0 to 8388607;

	signal RAD_MON: std_logic;
	signal RAD_RES: std_logic;
	signal RAD_OUT: std_logic;
--------------------------------------------

-- LED mono-flope variables
--------------------------------------------
	signal EVT_OCU: std_logic;
	signal VTO_OCU: std_logic;
	signal EVT_GTE: std_logic;
	signal VTO_GTE: std_logic;
	
	signal EVT_Fire: std_logic;
	signal VTO_Fire: std_logic;
	
	signal EVT_CNT: natural range 0 to 1048575;
	signal VTO_CNT: natural range 0 to 1048575;
--------------------------------------------

-- Radiation alarm variables
--------------------------------------------
	signal RAD_LEV: std_logic_vector(7 downto 0);
--------------------------------------------

-- "NOT" library component declaration
--------------------------------------------
	component LPM_INV
	generic(
			LPM_Width: natural;
			LPM_Type: string
			);
	port(
			Data: in std_logic_vector(7 downto 0);
			Result: out std_logic_vector(7 downto 0)
			);
	end component;
--------------------------------------------

-- Divider declaration
--------------------------------------------
	component lpm_divide
	generic (
			lpm_widthn: natural;
			lpm_widthd: natural;
			lpm_type: string;
			lpm_nrepresentation: string;
			lpm_hint: string;
			lpm_drepresentation: string
			);
	port (
			Denom: in std_logic_vector (22 downto 0);
			Quotient: out std_logic_vector (22 downto 0);
			Remain: out std_logic_vector (22 downto 0);
			Numer: in std_logic_vector (22 downto 0)
	);
	end component;
--------------------------------------------

-- function declarations
--------------------------

-- Data type conversion:
-- binary#23 -> natural
--------------------------------------------
	function BIT23_to_NUM(BIT_ARR: std_logic_vector(22 downto 0)) return natural is
		variable TEMP: natural range 0 to 8388607;
	begin
			TEMP:=0;
		for I in BIT_ARR'range loop
			TEMP:= TEMP * 2;
			if (BIT_ARR(I) = '1') then
				TEMP:= TEMP + 1;
			else
				null;
			end if;
		end loop;
	return TEMP;
	end BIT23_to_NUM;
--------------------------------------------

-- Data type conversion:
-- binary#8 -> natural
--------------------------------------------
	function BIT8_to_NUM(BIT_ARR: std_logic_vector(7 downto 0)) return natural is
		variable TEMP: natural range 0 to 255;
	begin
			TEMP:=0;
		for I in BIT_ARR'range loop
			TEMP:= TEMP * 2;
			if (BIT_ARR(I) = '1') then
				TEMP:= TEMP + 1;
			else
				null;
			end if;
		end loop;
	return TEMP;
	end BIT8_to_NUM;
--------------------------------------------

-- Data type conversion:
-- binary#7 -> natural
--------------------------------------------
	function BIT7_to_NUM(BIT_ARR: std_logic_vector(6 downto 0)) return natural is
		variable TEMP: natural range 0 to 127;
	begin
			TEMP:=0;
		for I in BIT_ARR'range loop
			TEMP:= TEMP * 2;
			if (BIT_ARR(I) = '1') then
				TEMP:= TEMP + 1;
			else
				null;
			end if;
		end loop;
	return TEMP;
	end BIT7_to_NUM;
--------------------------------------------

-- Data type conversion:
-- binary#5 -> natural
--------------------------------------------
	function BIT5_to_NUM(BIT_ARR: std_logic_vector(4 downto 0)) return natural is
		variable TEMP: natural range 0 to 31;
	begin
			TEMP:=0;
		for I in BIT_ARR'range loop
			TEMP:= TEMP * 2;
			if (BIT_ARR(I) = '1') then
				TEMP:= TEMP + 1;
			else
				null;
			end if;
		end loop;
	return TEMP;
	end BIT5_to_NUM;
--------------------------------------------

-- This function selects events in the
-- inner SPACAL region (radii < 235 mm);
-- unresolved tracks are assigned to the
-- inner SPACAL - to be tested
--------------------------------------------
	function SP_INN(Zahl: std_logic_vector(3 downto 0)) return std_logic is
		variable TEMP: std_logic;
	begin
		case Zahl is
			when "0001" =>
				TEMP:= '1';	-- First 16 masks;
			when "0010" =>
				TEMP:= '1';	-- Second 16 masks;
			when "0011" =>
				TEMP:= '1';	-- Third 16 masks;
			when "0100" =>
				TEMP:= '1';	-- Fourth 16 masks;
--------------------------
			when "1001" =>
				TEMP:= '1';	-- First 32 masks;
			when "1010" =>
				TEMP:= '1';	-- Second 32 masks;
--------------------------
			when "1101" =>
				TEMP:= '1';	-- First 64 masks;
--------------------------
			when "1111" =>
				TEMP:= '1';	-- The whole range;
			when others =>
				TEMP:= '0';
		end case;			
	return TEMP;
	end SP_INN;
--------------------------------------------

-- This function selects events in the
-- outer SPACAL regin (radii > 235 mm);
--------------------------------------------
	function SP_OUT(Zahl: std_logic_vector(3 downto 0)) return std_logic is
		variable TEMP: std_logic;
	begin
		case Zahl is
			when "0101" =>
				TEMP:= '1';	-- Fifth 16 masks;
			when "0110" =>
				TEMP:= '1';	-- Sixth 16 masks;
			when "0111" =>
				TEMP:= '1';	-- Seventh 16 masks;
			when "1000" =>
				TEMP:= '1';	-- Eighth 16 masks;
--------------------------
			when "1011" =>
				TEMP:= '1';	-- Third 32 masks;
			when "1100" =>
				TEMP:= '1';	-- Fourth 32 masks;
--------------------------
			when "1110" =>
				TEMP:= '1';	-- Second 64 masks;
--------------------------
			when "1111" =>
				TEMP:= '1';	-- The whole range;
			when others =>
				TEMP:= '0';
		end case;			
	return TEMP;
	end SP_OUT;
--------------------------------------------

-- SUM_of_ONES_12 is used to count a number
-- of sectors with a high background cond.
--------------------------------------------
	function SUM_of_ONES_12(TRIG_PAT: std_logic_vector(11 downto 0)) return natural is
		variable SUM_TOT: natural range 0 to 15;
	begin
		SUM_TOT:= 0;
		for Index in TRIG_PAT'range loop
			if (TRIG_PAT(Index) = '1') then
				SUM_TOT:= SUM_TOT + 1;
			end if;
		end loop;
		return SUM_TOT;
	end SUM_of_ONES_12;
--------------------------------------------



-- Odd parity bit (making odd
-- the entire number of ones)
--------------------------------------------
	function ODD_PAR(BIT_ARR: std_logic_vector(7 downto 0)) return std_logic is
		variable TEMP: std_logic;
	begin
			TEMP:= '1';
		for I in BIT_ARR'range loop
			if (BIT_ARR(I) = '1') then
				TEMP:= not TEMP;
			else
				null;
			end if;
		end loop;
	return TEMP;
	end ODD_PAR;
--------------------------------------------

begin

-- Permanent statements
--------------------------------------------
	DUM_RES <= '0';
--------------------------
	Write   <= BRD_ADR(7);
--------------------------
	DLY_OUT <= SYN_SEL;
--------------------------
	EVT_LED <= not EVT_Fire;
	VTO_LED <= not VTO_Fire;
--------------------------
	PIP_DEP <= BIT5_to_NUM(DEP_REG);
	PIP_OFF <= BIT7_to_NUM(OFF_REG);
--------------------------
	EVT_OCU <= TSP_INN or TSP_OUT;
	VTO_OCU <= BST_VTO;
--------------------------
	ID1_REG <= "00001111";	-- Data coded in two
	ID0_REG <= "00100110";	-- registers: "15.02.2006"
--------------------------------------------

-- Start-up counter (Clock ->)
--------------------------------------------
	process(DUM_RES, Clock, RES_PUL)
	begin
		if (DUM_RES = '1') then
			INI_CNT <= 0;
		elsif (Clock'event and Clock = '1') then
			if (RES_PUL = '1') then
				INI_CNT <= INI_CNT + 1;
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Start-up reset pulse (Clock <-)
--------------------------------------------
	process(DUM_RES, Clock, INI_CNT)
	begin
		if (DUM_RES = '1') then
			RES_PUL <= '1';
		elsif (Clock'event and Clock = '0') then
			if (INI_CNT = 524287) then
				RES_PUL <= '0';
			else
				RES_PUL <= '1';
			end if;
		end if;
	end process;
--------------------------
	process(Clock, RES_PUL)
	begin
		if (Clock'event and Clock = '1') then
			RES_DEL <= RES_PUL;
		end if;
	end process;
--------------------------------------------

-- wake up - set busy (Clear by Clock ->)
--------------------------------------------
	process(RES_DEL, FED_CLR, FED_END, RXD)
	begin
		if (RES_DEL = '1' or FED_CLR = '1' or FED_END = '1') then
			IAM_BSY <= '0';
		elsif (RXD'event and RXD = '0') then
			IAM_BSY <= '1';
		end if;
	end process;
--------------------------------------------

-- Frame counter (Clock <-)
--------------------------------------------
	process(Clock, IAM_BSY)
	begin
		if (Clock'event and Clock = '0') then
			if (IAM_BSY = '1') then
				FED_CNT <= FED_CNT + 1;
			else
				FED_CNT <= 0;
			end if;
		end if;
	end process;
--------------------------------------------

-- Clear frame signal (Clock ->)
-- if code key validation fails
-- after the 77'th clock period
--------------------------------------------
	process(FED_CNT, Clock, COD_KEY)
	begin
		if (FED_CNT /= 77) then
			FED_CLR <= '0';
		elsif (Clock'event and Clock = '1') then
			if (COD_KEY /= "01010101") then
				FED_CLR <= '1';
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- End of frame signal (Clock ->)
--------------------------------------------
	process(FED_CNT, COD_KEY, Clock)
	begin
		if (FED_CNT /= 234) then
			FED_END <= '0';
		elsif (Clock'event and Clock = '1') then
			FED_END <= '1';
		end if;
	end process;
--------------------------------------------

-- latching serial address and data (Clock ->)
--------------------------------------------
	process(Clock, FED_CNT, RXD)
	begin
		if (Clock'event and Clock = '1') then
			case FED_CNT is
				when 13 => -- +8
					COD_KEY(7) <= not RXD;
				when 22 => -- +9
					COD_KEY(6) <= not RXD;
				when 30 => -- +8
					COD_KEY(5) <= not RXD;
				when 39 => -- +9
					COD_KEY(4) <= not RXD;
				when 47 => -- +8
					COD_KEY(3) <= not RXD;
				when 56 => -- +9
					COD_KEY(2) <= not RXD;
				when 64 => -- +8
					COD_KEY(1) <= not RXD;
				when 73 => -- +9
					COD_KEY(0) <= not RXD;
				when 81 => -- +8
					BRD_ADR(7) <= not RXD;
				when 90 => -- +9
					BRD_ADR(6) <= not RXD;
				when 98 => -- +8
					BRD_ADR(5) <= not RXD;
				when 107 => -- +9
					BRD_ADR(4) <= not RXD;
				when 115 => -- +8
					BRD_ADR(3) <= not RXD;
				when 124 => -- +9
					BRD_ADR(2) <= not RXD;
				when 132 => -- +8
					BRD_ADR(1) <= not RXD;
				when 141 => -- +9
					BRD_ADR(0) <= not RXD;
				when 149 => -- +8
					BRD_INP(7) <= not RXD;
				when 158 => -- +9
					BRD_INP(6) <= not RXD;
				when 166 => -- +8
					BRD_INP(5) <= not RXD;
				when 175 => -- +9
					BRD_INP(4) <= not RXD;
				when 183 => -- +8
					BRD_INP(3) <= not RXD;
				when 192 => -- +9
					BRD_INP(2) <= not RXD;
				when 200 => -- +8
					BRD_INP(1) <= not RXD;
				when 209 => -- +9
					BRD_INP(0) <= not RXD;
				when 217 => -- +8
					PAR_INP    <= not RXD;
				when others =>
					null;
			end case;
		end if;
	end process;
--------------------------------------------

-- pushing out data (Clock ->)
--------------------------------------------
	process(Write, Clock, FED_CNT, BRD_OUT, PAR_OUT)
	begin
		if (Write = '1') then
			TXD <= '1';
		elsif (Clock'event and Clock = '1') then
			case FED_CNT is
				when 1 =>
					TXD <= '1';
				when 149 => -- +8
					TXD <= not BRD_OUT(7);
				when 158 => -- +9
					TXD <= not BRD_OUT(6);
				when 166 => -- +8
					TXD <= not BRD_OUT(5);
				when 175 => -- +9
					TXD <= not BRD_OUT(4);
				when 183 => -- +8
					TXD <= not BRD_OUT(3);
				when 192 => -- +9
					TXD <= not BRD_OUT(2);
				when 200 => -- +8
					TXD <= not BRD_OUT(1);
				when 209 => -- +9
					TXD <= not BRD_OUT(0);
				when 217 => -- +8
					TXD <= not PAR_OUT;
				when 226 => -- +9
					TXD <= '1';
				when others =>
					null;
			end case;
		end if;
	end process;
--------------------------------------------

-- Monitoring parities
--------------------------------------------
	PAR_OUT <= ODD_PAR(BRD_ADR) xnor ODD_PAR(BRD_OUT);
	PAR_CMI <= ODD_PAR(BRD_ADR) xnor ODD_PAR(BRD_INP);
--------------------------------------------

-- Control register assignment (Clock ->)
-- MSB of the INP_ADR register = 'Write'
--------------------------------------------
	process(RES_DEL, Clock, FED_CNT, PAR_INP, PAR_CMI, BRD_ADR, BRD_INP)
	begin
		if (RES_DEL = '1') then
			DEP_REG <= "10100";
			OFF_REG <= "0000110";
			CLK_REG <= "0000";
			TRG_RG0 <= (others => '1');
			TRG_RG1 <= (others => '1');
			MON_RG0 <= (others => '1');
			MON_RG1 <= (others => '1');
			PED_REG <= (others => '0');
		elsif (Clock'event and Clock = '1') then
			if (FED_CNT = 222 and PAR_INP = PAR_CMI) then
				case BRD_ADR is
					when "11010000" =>
						DEP_REG(4 downto 0) <= BRD_INP(4 downto 0);
					when "11010001" =>
						OFF_REG(6 downto 0) <= BRD_INP(6 downto 0);
					when "11010010" =>
						CLK_REG(3 downto 0) <= BRD_INP(3 downto 0);
					when "11010011" =>
						TRG_RG0(5 downto 0) <= BRD_INP(5 downto 0);
					when "11010100" =>
						TRG_RG1(5 downto 0) <= BRD_INP(5 downto 0);
					when "11010101" =>
						MON_RG0(5 downto 0) <= BRD_INP(5 downto 0);
					when "11010110" =>
						MON_RG1(5 downto 0) <= BRD_INP(5 downto 0);
					when "11010111" =>
						PED_REG <= BRD_INP;
					when "11011000" =>
						ST_RATE <= BRD_INP(0);
					when others =>
						null;
				end case;
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Forming the output string
--------------------------------------------
	process(BRD_ADR, DEP_REG, OFF_REG, CLK_REG,
			TRG_RG0, TRG_RG1, MON_RG0, MON_RG1,
			PED_REG, ST_RATE, RAD_LEV)
	begin
		case BRD_ADR is
			when "01010000" =>
				BRD_OUT(7 downto 5) <= "000";
				BRD_OUT(4 downto 0) <= DEP_REG;
			when "01010001" =>
				BRD_OUT(7) <= '0';
				BRD_OUT(6 downto 0) <= OFF_REG;
			when "01010010" =>
				BRD_OUT(7 downto 4) <= "0000";
				BRD_OUT(3 downto 0) <= CLK_REG;
			when "01010011" =>
				BRD_OUT(7 downto 6) <= "00";
				BRD_OUT(5 downto 0) <= TRG_RG0;
			when "01010100" =>
				BRD_OUT(7 downto 6) <= "00";
				BRD_OUT(5 downto 0) <= TRG_RG1;
			when "01010101" =>
				BRD_OUT(7 downto 6) <= "00";
				BRD_OUT(5 downto 0) <= MON_RG0;
			when "01010110" =>
				BRD_OUT(7 downto 6) <= "00";
				BRD_OUT(5 downto 0) <= MON_RG1;
			when "01010111" =>
				BRD_OUT <= PED_REG;
			when "01011000" =>
				BRD_OUT(7 downto 1) <= "0000000";
				BRD_OUT(0) <= ST_RATE;
			when "01011001" =>
				BRD_OUT <= RAD_LEV;
			when others =>
				BRD_OUT <= (others => '0');
		end case;
	end process;
--------------------------------------------

-- Clock frequency with an external pulser.
-- It is useful when the H1 central trigger
-- is stopped and the default potential of
-- the HCLK signal is not known (thought to
-- be zero). The scheme allows running with
-- the "GEN" connector pluged or unpluged.
--------------------------------------------
	process(HCLK, GEN)
	begin
		case HCLK is
			when '1' =>
				Oscillator <= GEN;
			when others =>
				Oscillator <= not GEN;
			end case;
	end process;
--------------------------------------------

-- Combined "Pipeline Enable" signal
--------------------------------------------
	process(PEN, Enable)
	begin
		case PEN is
			when '1' =>
				Permission <= Enable;
			when others =>
				Permission <= not Enable;
			end case;
	end process;
--------------------------------------------

-- Combined "Fast clear" signal
--------------------------------------------
	process(FCLR, Clear)
	begin
		case FCLR is
			when '1' =>
				Fast_Reset <= Clear;
			when others =>
				Fast_Reset <= not Clear;
			end case;
	end process;
--------------------------------------------

-- Selecting external controls between the
-- backplane and the front panel. The first
-- choice is needed when the card is operated
-- in H1 without control signals from the
-- central trigger, but the backplane signals
-- are well defined. The system will accept
-- external control automatically. The second
-- case is for the pure stand-alone operation
-- with external controls (the levels at the
-- backplane may oscillate).
--------------------------------------------
	process(BCK_PAN, Oscillator, Permission,
			Fast_Reset, GEN, Enable, Clear)
	begin
		case BCK_PAN is
			when '1' =>
				SYN_SEL <= Oscillator;	-- Clock from the backpl. / Fr. panel.;
				PEN_SEL <= Permission;	-- "Pipeline Enable" from the backpl.;
				CLR_SEL <= Fast_Reset;	-- H1 "Clear" from the backplane;
			when others =>
				SYN_SEL <= GEN;			-- "Clock" pulses (positive polarity);
				PEN_SEL <= Enable;		-- "Pipeline Enable" = ON when absent;
				CLR_SEL <= not Clear;	-- Inversed "Clear" = OFF when absent.
		end case;
	end process;
--------------------------------------------

-- Phase adjustment for the Clock freq.
--------------------------------------------
	process(CLK_REG, DLY_TAP, SYN_SEL)
	begin
		case CLK_REG is
			when "1001" =>
				Clock <= DLY_TAP(9);
				TCLK_CNT <= 10;
			when "1000" =>
				Clock <= DLY_TAP(8);
				TCLK_CNT <= 9;
			when "0111" =>
				Clock <= DLY_TAP(7);
				TCLK_CNT <= 8;
			when "0110" =>
				Clock <= DLY_TAP(6);
				TCLK_CNT <= 7;
			when "0101" =>
				Clock <= DLY_TAP(5);
				TCLK_CNT <= 6;
			when "0100" =>
				Clock <= DLY_TAP(4);
				TCLK_CNT <= 5;
			when "0011" =>
				Clock <= DLY_TAP(3);
				TCLK_CNT <= 4;
			when "0010" =>
				Clock <= DLY_TAP(2);
				TCLK_CNT <= 3;
			when "0001" =>
				Clock <= DLY_TAP(1);
				TCLK_CNT <= 2;
			when "0000" =>
				Clock <= DLY_TAP(0);
				TCLK_CNT <= 1;
			when others =>
				Clock <= SYN_SEL;
				TCLK_CNT <= 0;
		end case;
	end process;
--------------------------------------------

-- Delay for the data strobe
--------------------------------------------
	MSTB_CNT <= TCLK_CNT + 3;
--------------------------------------------

-- Periodic correction (excluding zero)
--------------------------------------------
	process(MSTB_CNT)
	begin
		case MSTB_CNT is
			when 0 to 10 =>
				MSTB_VAL <= MSTB_CNT;
			when others =>
				MSTB_VAL <= MSTB_CNT - 10;
		end case;
	end process;
--------------------------------------------

-- Phase adjustment for the data strobe
--------------------------------------------
	process(MSTB_VAL, DLY_TAP, SYN_SEL)
	begin
		case MSTB_VAL is
			when 10 =>
				MSTB <= DLY_TAP(9);
			when 9 =>
				MSTB <= DLY_TAP(8);
			when 8 =>
				MSTB <= DLY_TAP(7);
			when 7 =>
				MSTB <= DLY_TAP(6);
			when 6 =>
				MSTB <= DLY_TAP(5);
			when 5 =>
				MSTB <= DLY_TAP(4);
			when 4 =>
				MSTB <= DLY_TAP(3);
			when 3 =>
				MSTB <= DLY_TAP(2);
			when 2 =>
				MSTB <= DLY_TAP(1);
			when 1 =>
				MSTB <= DLY_TAP(0);
			when others =>
				MSTB <= SYN_SEL;
		end case;
	end process;
--------------------------------------------

-- Reset telescope
--------------------------------------------
	process(DLY_TAP(0), CLR_SEL)
	begin
		if (DLY_TAP(0)'event and DLY_TAP(0) = '1') then
			CLR_TL0 <= CLR_SEL;
		end if;
	end process;
--------------------------
	process(DLY_TAP(1), CLR_TL0)
	begin
		if (DLY_TAP(1)'event and DLY_TAP(1) = '1') then
			CLR_TL1 <= CLR_TL0;
		end if;
	end process;
--------------------------
	process(DLY_TAP(2), CLR_TL1)
	begin
		if (DLY_TAP(2)'event and DLY_TAP(2) = '1') then
			CLR_TL2 <= CLR_TL1;
		end if;
	end process;
--------------------------
	process(DLY_TAP(3), CLR_TL2)
	begin
		if (DLY_TAP(3)'event and DLY_TAP(3) = '1') then
			CLR_TL3 <= CLR_TL2;
		end if;
	end process;
--------------------------
	process(DLY_TAP(4), CLR_TL3)
	begin
		if (DLY_TAP(4)'event and DLY_TAP(4) = '1') then
			CLR_TL4 <= CLR_TL3;
		end if;
	end process;
--------------------------
	process(DLY_TAP(5), CLR_TL4)
	begin
		if (DLY_TAP(5)'event and DLY_TAP(5) = '1') then
			CLR_TL5 <= CLR_TL4;
		end if;
	end process;
--------------------------
	process(DLY_TAP(6), CLR_TL5)
	begin
		if (DLY_TAP(6)'event and DLY_TAP(6) = '1') then
			CLR_TL6 <= CLR_TL5;
		end if;
	end process;
--------------------------
	process(DLY_TAP(7), CLR_TL6)
	begin
		if (DLY_TAP(7)'event and DLY_TAP(7) = '1') then
			CLR_TL7 <= CLR_TL6;
		end if;
	end process;
--------------------------
	process(DLY_TAP(8), CLR_TL7)
	begin
		if (DLY_TAP(8)'event and DLY_TAP(8) = '1') then
			CLR_TL8 <= CLR_TL7;
		end if;
	end process;
--------------------------
	process(DLY_TAP(9), CLR_TL8)
	begin
		if (DLY_TAP(9)'event and DLY_TAP(9) = '1') then
			CLR_TL9 <= CLR_TL8;
		end if;
	end process;
--------------------------------------------

-- "Pipeline enable" telescope
--------------------------------------------
	process(DLY_TAP(0), PEN_SEL)
	begin
		if (DLY_TAP(0)'event and DLY_TAP(0) = '1') then
			PEN_TL0 <= PEN_SEL;
		end if;
	end process;
--------------------------
	process(DLY_TAP(1), PEN_TL0)
	begin
		if (DLY_TAP(1)'event and DLY_TAP(1) = '1') then
			PEN_TL1 <= PEN_TL0;
		end if;
	end process;
--------------------------
	process(DLY_TAP(2), PEN_TL1)
	begin
		if (DLY_TAP(2)'event and DLY_TAP(2) = '1') then
			PEN_TL2 <= PEN_TL1;
		end if;
	end process;
--------------------------
	process(DLY_TAP(3), PEN_TL2)
	begin
		if (DLY_TAP(3)'event and DLY_TAP(3) = '1') then
			PEN_TL3 <= PEN_TL2;
		end if;
	end process;
--------------------------
	process(DLY_TAP(4), PEN_TL3)
	begin
		if (DLY_TAP(4)'event and DLY_TAP(4) = '1') then
			PEN_TL4 <= PEN_TL3;
		end if;
	end process;
--------------------------
	process(DLY_TAP(5), PEN_TL4)
	begin
		if (DLY_TAP(5)'event and DLY_TAP(5) = '1') then
			PEN_TL5 <= PEN_TL4;
		end if;
	end process;
--------------------------
	process(DLY_TAP(6), PEN_TL5)
	begin
		if (DLY_TAP(6)'event and DLY_TAP(6) = '1') then
			PEN_TL6 <= PEN_TL5;
		end if;
	end process;
--------------------------
	process(DLY_TAP(7), PEN_TL6)
	begin
		if (DLY_TAP(7)'event and DLY_TAP(7) = '1') then
			PEN_TL7 <= PEN_TL6;
		end if;
	end process;
--------------------------
	process(DLY_TAP(8), PEN_TL7)
	begin
		if (DLY_TAP(8)'event and DLY_TAP(8) = '1') then
			PEN_TL8 <= PEN_TL7;
		end if;
	end process;
--------------------------
	process(DLY_TAP(9), PEN_TL8)
	begin
		if (DLY_TAP(9)'event and DLY_TAP(9) = '1') then
			PEN_TL9 <= PEN_TL8;
		end if;
	end process;
--------------------------------------------

-- Phase adjustment for the "L1Keep" signal
--------------------------------------------
	process(CLK_REG, PEN_TL9, PEN_TL8, PEN_TL7,
			PEN_TL6, PEN_TL5, PEN_TL4, PEN_TL3,
			PEN_TL2, PEN_TL1, PEN_TL0, PEN_SEL,
			CLR_TL9, CLR_TL8, CLR_TL7, CLR_TL6,
			CLR_TL5, CLR_TL4, CLR_TL3, CLR_TL2,
			CLR_TL1, CLR_TL0, CLR_SEL)
	begin
		case CLK_REG is
			when "1001" =>
				TRHF_SYN <= PEN_TL9;
				TRHR_SYN <= CLR_TL9;
			when "1000" =>
				TRHF_SYN <= PEN_TL8;
				TRHR_SYN <= CLR_TL8;
			when "0111" =>
				TRHF_SYN <= PEN_TL7;
				TRHR_SYN <= CLR_TL7;
			when "0110" =>
				TRHF_SYN <= PEN_TL6;
				TRHR_SYN <= CLR_TL6;
			when "0101" =>
				TRHF_SYN <= PEN_TL5;
				TRHR_SYN <= CLR_TL5;
			when "0100" =>
				TRHF_SYN <= PEN_TL4;
				TRHR_SYN <= CLR_TL4;
			when "0011" =>
				TRHF_SYN <= PEN_TL3;
				TRHR_SYN <= CLR_TL3;
			when "0010" =>
				TRHF_SYN <= PEN_TL2;
				TRHR_SYN <= CLR_TL2;
			when "0001" =>
				TRHF_SYN <= PEN_TL1;
				TRHR_SYN <= CLR_TL1;
			when "0000" =>
				TRHF_SYN <= PEN_TL0;
				TRHR_SYN <= CLR_TL0;
			when others =>
				TRHF_SYN <= PEN_SEL;
				TRHR_SYN <= CLR_SEL;
		end case;
	end process;
--------------------------------------------

-- Starting the "L1Keep" signal
--------------------------------------------
	process(TRHR_SYN, TRHF_SYN)
	begin
		if (TRHR_SYN = '1') then
			Gate <= '0';
		elsif (TRHF_SYN'event and TRHF_SYN = '0') then
			Gate <= '1';
		end if;
	end process;
--------------------------------------------

-- Finishing the "L1Keep" signal
--------------------------------------------
	process(Gate, TRHR_SYN)
	begin
		if (Gate = '1') then
			L1Keep <= '1';
		elsif (TRHR_SYN'event and TRHR_SYN = '0') then
			L1Keep <= '0';
		end if;
	end process;
--------------------------------------------

-- Latching input trigger data (Clock <-)
--------------------------------------------

-- Sector 0
--------------------------
	process(TRG_RG0(0), Clock, Tinp00)
	begin
		if (TRG_RG0(0) = '0') then
			Temp00 <= (others => '1');
		elsif (Clock'event and Clock = '0') then
			Temp00 <= Tinp00;
		end if;
	end process;
--------------------------

-- Sector 1
--------------------------
	process(TRG_RG0(1), Clock, Tinp01)
	begin
		if (TRG_RG0(1) = '0') then
			Temp01 <= (others => '1');
		elsif (Clock'event and Clock = '0') then
			Temp01 <= Tinp01;
		end if;
	end process;
--------------------------

-- Sector 2
--------------------------
	process(TRG_RG0(2), Clock, Tinp20)
	begin
		if (TRG_RG0(2) = '0') then
			Temp10 <= (others => '1');
		elsif (Clock'event and Clock = '0') then
			Temp10 <= Tinp20;
		end if;
	end process;
--------------------------

-- Sector 3
--------------------------
	process(TRG_RG0(3), Clock, Tinp21)
	begin
		if (TRG_RG0(3) = '0') then
			Temp11 <= (others => '1');
		elsif (Clock'event and Clock = '0') then
			Temp11 <= Tinp21;
		end if;
	end process;
--------------------------

-- Sector 4
--------------------------
	process(TRG_RG0(4), Clock, Tinp40)
	begin
		if (TRG_RG0(4) = '0') then
			Temp20 <= (others => '1');
		elsif (Clock'event and Clock = '0') then
			Temp20 <= Tinp40;
		end if;
	end process;
--------------------------

-- Sector 5
--------------------------
	process(TRG_RG0(5), Clock, Tinp41)
	begin
		if (TRG_RG0(5) = '0') then
			Temp21 <= (others => '1');
		elsif (Clock'event and Clock = '0') then
			Temp21 <= Tinp41;
		end if;
	end process;
--------------------------

-- Sector 10
--------------------------
	process(TRG_RG1(0), Clock, Tinp10)
	begin
		if (TRG_RG1(0) = '0') then
			Temp30 <= (others => '1');
		elsif (Clock'event and Clock = '0') then
			Temp30 <= Tinp10;
		end if;
	end process;
--------------------------

-- Sector 11
--------------------------
	process(TRG_RG1(1), Clock, Tinp11)
	begin
		if (TRG_RG1(1) = '0') then
			Temp31 <= (others => '1');
		elsif (Clock'event and Clock = '0') then
			Temp31 <= Tinp11;
		end if;
	end process;
--------------------------

-- Sector 12
--------------------------
	process(TRG_RG1(2), Clock, Tinp30)
	begin
		if (TRG_RG1(2) = '0') then
			Temp40 <= (others => '1');
		elsif (Clock'event and Clock = '0') then
			Temp40 <= Tinp30;
		end if;
	end process;
--------------------------

-- Sector 13
--------------------------
	process(TRG_RG1(3), Clock, Tinp31)
	begin
		if (TRG_RG1(3) = '0') then
			Temp41 <= (others => '1');
		elsif (Clock'event and Clock = '0') then
			Temp41 <= Tinp31;
		end if;
	end process;
--------------------------

-- Sector 14
--------------------------
	process(TRG_RG1(4), Clock, Tinp50)
	begin
		if (TRG_RG1(4) = '0') then
			Temp50 <= (others => '1');
		elsif (Clock'event and Clock = '0') then
			Temp50 <= Tinp50;
		end if;
	end process;
--------------------------

-- Sector 15
--------------------------
	process(TRG_RG1(5), Clock, Tinp51)
	begin
		if (TRG_RG1(5) = '0') then
			Temp51 <= (others => '1');
		elsif (Clock'event and Clock = '0') then
			Temp51 <= Tinp51;
		end if;
	end process;
--------------------------------------------

-- Data inversion
--------------------------------------------
	lpm_inv_component0: LPM_INV
	generic map(
				LPM_Width => 8,
				LPM_Type => "LPM_INV"
				)
	port map(
				Data => Temp00,
				Result => Pass00
				);
--------------------------
	lpm_inv_component1: LPM_INV
	generic map(
				LPM_Width => 8,
				LPM_Type => "LPM_INV"
				)
	port map(
				Data => Temp01,
				Result => Pass01
				);
--------------------------
	lpm_inv_component2: LPM_INV
	generic map(
				LPM_Width => 8,
				LPM_Type => "LPM_INV"
				)
	port map(
				Data => Temp10,
				Result => Pass10
				);
--------------------------
	lpm_inv_component3: LPM_INV
	generic map(
				LPM_Width => 8,
				LPM_Type => "LPM_INV"
				)
	port map(
				Data => Temp11,
				Result => Pass11
				);
--------------------------
	lpm_inv_component4: LPM_INV
	generic map(
				LPM_Width => 8,
				LPM_Type => "LPM_INV"
				)
	port map(
				Data => Temp20,
				Result => Pass20
				);
--------------------------
	lpm_inv_component5: LPM_INV
	generic map(
				LPM_Width => 8,
				LPM_Type => "LPM_INV"
				)
	port map(
				Data => Temp21,
				Result => Pass21
				);
--------------------------
	lpm_inv_component6: LPM_INV
	generic map(
				LPM_Width => 8,
				LPM_Type => "LPM_INV"
				)
	port map(
				Data => Temp30,
				Result => Pass30
				);
--------------------------
	lpm_inv_component7: LPM_INV
	generic map(
				LPM_Width => 8,
				LPM_Type => "LPM_INV"
				)
	port map(
				Data => Temp31,
				Result => Pass31
				);
--------------------------
	lpm_inv_component8: LPM_INV
	generic map(
				LPM_Width => 8,
				LPM_Type => "LPM_INV"
				)
	port map(
				Data => Temp40,
				Result => Pass40
				);
--------------------------
	lpm_inv_component9: LPM_INV
	generic map(
				LPM_Width => 8,
				LPM_Type => "LPM_INV"
				)
	port map(
				Data => Temp41,
				Result => Pass41
				);
--------------------------
	lpm_inv_component10: LPM_INV
	generic map(
				LPM_Width => 8,
				LPM_Type => "LPM_INV"
				)
	port map(
				Data => Temp50,
				Result => Pass50
				);
--------------------------
	lpm_inv_component11: LPM_INV
	generic map(
				LPM_Width => 8,
				LPM_Type => "LPM_INV"
				)
	port map(
				Data => Temp51,
				Result => Pass51
				);
--------------------------------------------

-- Trigger signals (Clock ->)
--------------------------------------------
	process(Clock, Pass00, Pass01, Pass10, Pass11, Pass20, Pass21,
				   Pass30, Pass31, Pass40, Pass41, Pass50, Pass51)
	begin
		if (Clock'event and Clock = '1') then
			Trig00(6 downto 0) <= Pass00(7 downto 1);
			Trig01(6 downto 0) <= Pass01(7 downto 1);
			Trig10(6 downto 0) <= Pass10(7 downto 1);
			Trig11(6 downto 0) <= Pass11(7 downto 1);
			Trig20(6 downto 0) <= Pass20(7 downto 1);
			Trig21(6 downto 0) <= Pass21(7 downto 1);
			Trig30(6 downto 0) <= Pass30(7 downto 1);
			Trig31(6 downto 0) <= Pass31(7 downto 1);
			Trig40(6 downto 0) <= Pass40(7 downto 1);
			Trig41(6 downto 0) <= Pass41(7 downto 1);
			Trig50(6 downto 0) <= Pass50(7 downto 1);
			Trig51(6 downto 0) <= Pass51(7 downto 1);
		end if;
	end process;
--------------------------------------------

-- Veto decision
--------------------------------------------
    HM_VECT(0)  <= Trig00(5);
	HM_VECT(1)  <= Trig01(5);
	HM_VECT(2)  <= Trig10(5);
	HM_VECT(3)  <= Trig11(5);
	HM_VECT(4)  <= Trig20(5);
	HM_VECT(5)  <= Trig21(5);
	HM_VECT(6)  <= Trig30(5);
	HM_VECT(7)  <= Trig31(5);
	HM_VECT(8)  <= Trig40(5);
	HM_VECT(9)  <= Trig41(5);
	HM_VECT(10) <= Trig50(5);
	HM_VECT(11) <= Trig51(5);
-------------------------
	NSECT <= SUM_of_ONES_12(HM_VECT);
-------------------------
	process(NSECT)
	begin
		if (2 <= NSECT) then
			BST_VTO <= '1';
		else
			BST_VTO <= '0';
		end if;
	end process;
--------------------------------------------

-- Splitting inner/outer track projection	
--------------------------------------------
	INT_TRC(0)  <= SP_INN(Num00) and Trig00(6);
	INT_TRC(1)  <= SP_INN(Num01) and Trig01(6);
	INT_TRC(2)  <= SP_INN(Num10) and Trig10(6);
	INT_TRC(3)  <= SP_INN(Num11) and Trig11(6);
	INT_TRC(4)  <= SP_INN(Num20) and Trig20(6);
	INT_TRC(5)  <= SP_INN(Num21) and Trig21(6);

	INT_TRC(6)  <= SP_INN(Num30) and Trig30(6);
	INT_TRC(7)  <= SP_INN(Num31) and Trig31(6);
	INT_TRC(8)  <= SP_INN(Num40) and Trig40(6);
	INT_TRC(9)  <= SP_INN(Num41) and Trig41(6);
	INT_TRC(10) <= SP_INN(Num50) and Trig50(6);
	INT_TRC(11) <= SP_INN(Num51) and Trig51(6);
-------------------------
	OUT_TRC(0)  <= SP_OUT(Num00) and Trig00(6);
	OUT_TRC(1)  <= SP_OUT(Num01) and Trig01(6);
	OUT_TRC(2)  <= SP_OUT(Num10) and Trig10(6);
	OUT_TRC(3)  <= SP_OUT(Num11) and Trig11(6);
	OUT_TRC(4)  <= SP_OUT(Num20) and Trig20(6);
	OUT_TRC(5)  <= SP_OUT(Num21) and Trig21(6);

	OUT_TRC(6)  <= SP_OUT(Num30) and Trig30(6);
	OUT_TRC(7)  <= SP_OUT(Num31) and Trig31(6);
	OUT_TRC(8)  <= SP_OUT(Num40) and Trig40(6);
	OUT_TRC(9)  <= SP_OUT(Num41) and Trig41(6);
	OUT_TRC(10) <= SP_OUT(Num50) and Trig50(6);
	OUT_TRC(11) <= SP_OUT(Num51) and Trig51(6);
-------------------------

-- Trigger decision
--------------------------------------------
	TSP_INN <= INT_TRC(0)  or INT_TRC(1)
			or INT_TRC(2)  or INT_TRC(3)
			or INT_TRC(4)  or INT_TRC(5)
			or INT_TRC(6)  or INT_TRC(7)
			or INT_TRC(8)  or INT_TRC(9)
			or INT_TRC(10) or INT_TRC(11);
--------------------------
	TSP_OUT <= OUT_TRC(0)  or OUT_TRC(1)
			or OUT_TRC(2)  or OUT_TRC(3)
			or OUT_TRC(4)  or OUT_TRC(5)
			or OUT_TRC(6)  or OUT_TRC(7)
			or OUT_TRC(8)  or OUT_TRC(9)
			or OUT_TRC(10) or OUT_TRC(11);
--------------------------------------------

-- Vector for searching pure long tracks
--------------------------------------------
	LT_VECT(0)  <= Trig00(4);
	LT_VECT(1)  <= Trig01(4);
	LT_VECT(2)  <= Trig10(4);
	LT_VECT(3)  <= Trig11(4);
	LT_VECT(4)  <= Trig20(4);
	LT_VECT(5)  <= Trig21(4);
	LT_VECT(6)  <= Trig30(4);
	LT_VECT(7)  <= Trig31(4);
	LT_VECT(8)  <= Trig40(4);
	LT_VECT(9)  <= Trig41(4);
	LT_VECT(10) <= Trig50(4);
	LT_VECT(11) <= Trig51(4);
--------------------------------------------

-- Select a single track
--------------------------------------------
	process(LT_VECT)
	begin
		case LT_VECT is
			when "000000000001" =>
				LNG_TRK <= '1';
			when "000000000010" =>
				LNG_TRK <= '1';
			when "000000000100" =>
				LNG_TRK <= '1';
			when "000000001000" =>
				LNG_TRK <= '1';
			when "000000010000" =>
				LNG_TRK <= '1';
			when "000000100000" =>
				LNG_TRK <= '1';
			when "000001000000" =>
				LNG_TRK <= '1';
			when "000010000000" =>
				LNG_TRK <= '1';
			when "000100000000" =>
				LNG_TRK <= '1';
			when "001000000000" =>
				LNG_TRK <= '1';
			when "010000000000" =>
				LNG_TRK <= '1';
			when "100000000000" =>
				LNG_TRK <= '1';
			when others =>
				LNG_TRK <= '0';
		end case;
	end process;
--------------------------------------------

-- Making the life some easier
--------------------------------------------
	process(Clock, TSP_INN, TSP_OUT, LNG_TRK, BST_VTO)
	begin
		if (Clock'event and Clock = '0') then
			Resque(0) <= TSP_INN;
			Resque(1) <= TSP_OUT;
			Resque(2) <= LNG_TRK;
			Resque(3) <= BST_VTO;	
		end if;
	end process;
-------------------------
	process(Clock, Resque)
	begin
		if (Clock'event and Clock = '1') then
			Answer <= Resque;
		end if;
	end process;
--------------------------------------------

-- Delay the L1Keep signal to match
-- the synchronization phase and to
-- increment the pipeline address
-- by one after event announcement
-- to point to the earliest time
-- slice in the data history (Clock <-)
--------------------------------------------
	process(Clock, L1Keep)
	begin
		if (Clock'event and Clock = '0') then
			L1K_DEL <= L1Keep;
		end if;
	end process;
--------------------------------------------

-- Pipeline counter - incremented by one
-- and blocked after event announcement (Clock ->)
--------------------------------------------
	process(Clock, L1K_DEL)
	begin
		if (Clock'event and Clock = '1') then
			if (L1K_DEL = '0') then
				PIP_C00 <= PIP_C00 + 1;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1K_DEL)
	begin
		if (Clock'event and Clock = '1') then
			if (L1K_DEL = '0') then
				PIP_C01 <= PIP_C01 + 1;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1K_DEL)
	begin
		if (Clock'event and Clock = '1') then
			if (L1K_DEL = '0') then
				PIP_C02 <= PIP_C02 + 1;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1K_DEL)
	begin
		if (Clock'event and Clock = '1') then
			if (L1K_DEL = '0') then
				PIP_C03 <= PIP_C03 + 1;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1K_DEL)
	begin
		if (Clock'event and Clock = '1') then
			if (L1K_DEL = '0') then
				PIP_C04 <= PIP_C04 + 1;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1K_DEL)
	begin
		if (Clock'event and Clock = '1') then
			if (L1K_DEL = '0') then
				PIP_C05 <= PIP_C05 + 1;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1K_DEL)
	begin
		if (Clock'event and Clock = '1') then
			if (L1K_DEL = '0') then
				PIP_C10 <= PIP_C10 + 1;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1K_DEL)
	begin
		if (Clock'event and Clock = '1') then
			if (L1K_DEL = '0') then
				PIP_C11 <= PIP_C11 + 1;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1K_DEL)
	begin
		if (Clock'event and Clock = '1') then
			if (L1K_DEL = '0') then
				PIP_C12 <= PIP_C12 + 1;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1K_DEL)
	begin
		if (Clock'event and Clock = '1') then
			if (L1K_DEL = '0') then
				PIP_C13 <= PIP_C13 + 1;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1K_DEL)
	begin
		if (Clock'event and Clock = '1') then
			if (L1K_DEL = '0') then
				PIP_C14 <= PIP_C14 + 1;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1K_DEL)
	begin
		if (Clock'event and Clock = '1') then
			if (L1K_DEL = '0') then
				PIP_C15 <= PIP_C15 + 1;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1K_DEL)
	begin
		if (Clock'event and Clock = '1') then
			if (L1K_DEL = '0') then
				PIP_CL1 <= PIP_CL1 + 1;
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Looking back into history (Clock <-)
--------------------------------------------
	process(Clock, PIP_C00, PIP_C01, PIP_C02, PIP_C03,
				   PIP_C04, PIP_C05, PIP_C10, PIP_C11,
				   PIP_C12, PIP_C13, PIP_C14, PIP_C15,
				   PIP_CL1, PIP_DEP)
	begin
		if (Clock'event and Clock = '0') then
			PIP_S00 <= PIP_C00 - PIP_DEP;
			PIP_S01 <= PIP_C01 - PIP_DEP;
			PIP_S02 <= PIP_C02 - PIP_DEP;
			PIP_S03 <= PIP_C03 - PIP_DEP;
			PIP_S04 <= PIP_C04 - PIP_DEP;
			PIP_S05 <= PIP_C05 - PIP_DEP;
			PIP_S10 <= PIP_C10 - PIP_DEP;
			PIP_S11 <= PIP_C11 - PIP_DEP;
			PIP_S12 <= PIP_C12 - PIP_DEP;
			PIP_S13 <= PIP_C13 - PIP_DEP;
			PIP_S14 <= PIP_C14 - PIP_DEP;
			PIP_S15 <= PIP_C15 - PIP_DEP;
			PIP_SL1 <= PIP_CL1 - PIP_DEP + 1;
		end if;	
	end process;
--------------------------------------------

-- Latch topological data only
-- during pipeline enable (Clock <-)
--------------------------------------------
	process(Clock, L1Keep, PIP_C00, Trig00)
	begin
		if (Clock'event and Clock = '0') then
			if (L1Keep = '0') then
				case PIP_C00 is
					when 0 =>
						P00_00 <= Trig00;
					when 1 =>
						P01_00 <= Trig00;
					when 2 =>
						P02_00 <= Trig00;
					when 3 =>
						P03_00 <= Trig00;
					when 4 =>
						P04_00 <= Trig00;
					when 5 =>
						P05_00 <= Trig00;
					when 6 =>
						P06_00 <= Trig00;
					when 7 =>
						P07_00 <= Trig00;
					when 8 =>
						P08_00 <= Trig00;
					when 9 =>
						P09_00 <= Trig00;
					when 10 =>
						P10_00 <= Trig00;
					when 11 =>
						P11_00 <= Trig00;
					when 12 =>
						P12_00 <= Trig00;
					when 13 =>
						P13_00 <= Trig00;
					when 14 =>
						P14_00 <= Trig00;
					when 15 =>
						P15_00 <= Trig00;
					when 16 =>
						P16_00 <= Trig00;
					when 17 =>
						P17_00 <= Trig00;
					when 18 =>
						P18_00 <= Trig00;
					when 19 =>
						P19_00 <= Trig00;
					when 20 =>
						P20_00 <= Trig00;
					when 21 =>
						P21_00 <= Trig00;
					when 22 =>
						P22_00 <= Trig00;
					when 23 =>
						P23_00 <= Trig00;
					when 24 =>
						P24_00 <= Trig00;
					when 25 =>
						P25_00 <= Trig00;
					when 26 =>
						P26_00 <= Trig00;
					when 27 =>
						P27_00 <= Trig00;
					when 28 =>
						P28_00 <= Trig00;
					when 29 =>
						P29_00 <= Trig00;
					when 30 =>
						P30_00 <= Trig00;
					when others =>
						P31_00 <= Trig00;
				end case;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1Keep, PIP_C01, Trig01)
	begin
		if (Clock'event and Clock = '0') then
			if (L1Keep = '0') then
				case PIP_C01 is
					when 0 =>
						P00_01 <= Trig01;
					when 1 =>
						P01_01 <= Trig01;
					when 2 =>
						P02_01 <= Trig01;
					when 3 =>
						P03_01 <= Trig01;
					when 4 =>
						P04_01 <= Trig01;
					when 5 =>
						P05_01 <= Trig01;
					when 6 =>
						P06_01 <= Trig01;
					when 7 =>
						P07_01 <= Trig01;
					when 8 =>
						P08_01 <= Trig01;
					when 9 =>
						P09_01 <= Trig01;
					when 10 =>
						P10_01 <= Trig01;
					when 11 =>
						P11_01 <= Trig01;
					when 12 =>
						P12_01 <= Trig01;
					when 13 =>
						P13_01 <= Trig01;
					when 14 =>
						P14_01 <= Trig01;
					when 15 =>
						P15_01 <= Trig01;
					when 16 =>
						P16_01 <= Trig01;
					when 17 =>
						P17_01 <= Trig01;
					when 18 =>
						P18_01 <= Trig01;
					when 19 =>
						P19_01 <= Trig01;
					when 20 =>
						P20_01 <= Trig01;
					when 21 =>
						P21_01 <= Trig01;
					when 22 =>
						P22_01 <= Trig01;
					when 23 =>
						P23_01 <= Trig01;
					when 24 =>
						P24_01 <= Trig01;
					when 25 =>
						P25_01 <= Trig01;
					when 26 =>
						P26_01 <= Trig01;
					when 27 =>
						P27_01 <= Trig01;
					when 28 =>
						P28_01 <= Trig01;
					when 29 =>
						P29_01 <= Trig01;
					when 30 =>
						P30_01 <= Trig01;
					when others =>
						P31_01 <= Trig01;
				end case;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1Keep, PIP_C02, Trig10)
	begin
		if (Clock'event and Clock = '0') then
			if (L1Keep = '0') then
				case PIP_C02 is
					when 0 =>
						P00_02 <= Trig10;
					when 1 =>
						P01_02 <= Trig10;
					when 2 =>
						P02_02 <= Trig10;
					when 3 =>
						P03_02 <= Trig10;
					when 4 =>
						P04_02 <= Trig10;
					when 5 =>
						P05_02 <= Trig10;
					when 6 =>
						P06_02 <= Trig10;
					when 7 =>
						P07_02 <= Trig10;
					when 8 =>
						P08_02 <= Trig10;
					when 9 =>
						P09_02 <= Trig10;
					when 10 =>
						P10_02 <= Trig10;
					when 11 =>
						P11_02 <= Trig10;
					when 12 =>
						P12_02 <= Trig10;
					when 13 =>
						P13_02 <= Trig10;
					when 14 =>
						P14_02 <= Trig10;
					when 15 =>
						P15_02 <= Trig10;
					when 16 =>
						P16_02 <= Trig10;
					when 17 =>
						P17_02 <= Trig10;
					when 18 =>
						P18_02 <= Trig10;
					when 19 =>
						P19_02 <= Trig10;
					when 20 =>
						P20_02 <= Trig10;
					when 21 =>
						P21_02 <= Trig10;
					when 22 =>
						P22_02 <= Trig10;
					when 23 =>
						P23_02 <= Trig10;
					when 24 =>
						P24_02 <= Trig10;
					when 25 =>
						P25_02 <= Trig10;
					when 26 =>
						P26_02 <= Trig10;
					when 27 =>
						P27_02 <= Trig10;
					when 28 =>
						P28_02 <= Trig10;
					when 29 =>
						P29_02 <= Trig10;
					when 30 =>
						P30_02 <= Trig10;
					when others =>
						P31_02 <= Trig10;
				end case;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1Keep, PIP_C03, Trig11)
	begin
		if (Clock'event and Clock = '0') then
			if (L1Keep = '0') then
				case PIP_C03 is
					when 0 =>
						P00_03 <= Trig11;
					when 1 =>
						P01_03 <= Trig11;
					when 2 =>
						P02_03 <= Trig11;
					when 3 =>
						P03_03 <= Trig11;
					when 4 =>
						P04_03 <= Trig11;
					when 5 =>
						P05_03 <= Trig11;
					when 6 =>
						P06_03 <= Trig11;
					when 7 =>
						P07_03 <= Trig11;
					when 8 =>
						P08_03 <= Trig11;
					when 9 =>
						P09_03 <= Trig11;
					when 10 =>
						P10_03 <= Trig11;
					when 11 =>
						P11_03 <= Trig11;
					when 12 =>
						P12_03 <= Trig11;
					when 13 =>
						P13_03 <= Trig11;
					when 14 =>
						P14_03 <= Trig11;
					when 15 =>
						P15_03 <= Trig11;
					when 16 =>
						P16_03 <= Trig11;
					when 17 =>
						P17_03 <= Trig11;
					when 18 =>
						P18_03 <= Trig11;
					when 19 =>
						P19_03 <= Trig11;
					when 20 =>
						P20_03 <= Trig11;
					when 21 =>
						P21_03 <= Trig11;
					when 22 =>
						P22_03 <= Trig11;
					when 23 =>
						P23_03 <= Trig11;
					when 24 =>
						P24_03 <= Trig11;
					when 25 =>
						P25_03 <= Trig11;
					when 26 =>
						P26_03 <= Trig11;
					when 27 =>
						P27_03 <= Trig11;
					when 28 =>
						P28_03 <= Trig11;
					when 29 =>
						P29_03 <= Trig11;
					when 30 =>
						P30_03 <= Trig11;
					when others =>
						P31_03 <= Trig11;
				end case;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1Keep, PIP_C04, Trig20)
	begin
		if (Clock'event and Clock = '0') then
			if (L1Keep = '0') then
				case PIP_C04 is
					when 0 =>
						P00_04 <= Trig20;
					when 1 =>
						P01_04 <= Trig20;
					when 2 =>
						P02_04 <= Trig20;
					when 3 =>
						P03_04 <= Trig20;
					when 4 =>
						P04_04 <= Trig20;
					when 5 =>
						P05_04 <= Trig20;
					when 6 =>
						P06_04 <= Trig20;
					when 7 =>
						P07_04 <= Trig20;
					when 8 =>
						P08_04 <= Trig20;
					when 9 =>
						P09_04 <= Trig20;
					when 10 =>
						P10_04 <= Trig20;
					when 11 =>
						P11_04 <= Trig20;
					when 12 =>
						P12_04 <= Trig20;
					when 13 =>
						P13_04 <= Trig20;
					when 14 =>
						P14_04 <= Trig20;
					when 15 =>
						P15_04 <= Trig20;
					when 16 =>
						P16_04 <= Trig20;
					when 17 =>
						P17_04 <= Trig20;
					when 18 =>
						P18_04 <= Trig20;
					when 19 =>
						P19_04 <= Trig20;
					when 20 =>
						P20_04 <= Trig20;
					when 21 =>
						P21_04 <= Trig20;
					when 22 =>
						P22_04 <= Trig20;
					when 23 =>
						P23_04 <= Trig20;
					when 24 =>
						P24_04 <= Trig20;
					when 25 =>
						P25_04 <= Trig20;
					when 26 =>
						P26_04 <= Trig20;
					when 27 =>
						P27_04 <= Trig20;
					when 28 =>
						P28_04 <= Trig20;
					when 29 =>
						P29_04 <= Trig20;
					when 30 =>
						P30_04 <= Trig20;
					when others =>
						P31_04 <= Trig20;
				end case;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1Keep, PIP_C05, Trig21)
	begin
		if (Clock'event and Clock = '0') then
			if (L1Keep = '0') then
				case PIP_C05 is
					when 0 =>
						P00_05 <= Trig21;
					when 1 =>
						P01_05 <= Trig21;
					when 2 =>
						P02_05 <= Trig21;
					when 3 =>
						P03_05 <= Trig21;
					when 4 =>
						P04_05 <= Trig21;
					when 5 =>
						P05_05 <= Trig21;
					when 6 =>
						P06_05 <= Trig21;
					when 7 =>
						P07_05 <= Trig21;
					when 8 =>
						P08_05 <= Trig21;
					when 9 =>
						P09_05 <= Trig21;
					when 10 =>
						P10_05 <= Trig21;
					when 11 =>
						P11_05 <= Trig21;
					when 12 =>
						P12_05 <= Trig21;
					when 13 =>
						P13_05 <= Trig21;
					when 14 =>
						P14_05 <= Trig21;
					when 15 =>
						P15_05 <= Trig21;
					when 16 =>
						P16_05 <= Trig21;
					when 17 =>
						P17_05 <= Trig21;
					when 18 =>
						P18_05 <= Trig21;
					when 19 =>
						P19_05 <= Trig21;
					when 20 =>
						P20_05 <= Trig21;
					when 21 =>
						P21_05 <= Trig21;
					when 22 =>
						P22_05 <= Trig21;
					when 23 =>
						P23_05 <= Trig21;
					when 24 =>
						P24_05 <= Trig21;
					when 25 =>
						P25_05 <= Trig21;
					when 26 =>
						P26_05 <= Trig21;
					when 27 =>
						P27_05 <= Trig21;
					when 28 =>
						P28_05 <= Trig21;
					when 29 =>
						P29_05 <= Trig21;
					when 30 =>
						P30_05 <= Trig21;
					when others =>
						P31_05 <= Trig21;
				end case;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1Keep, PIP_C10, Trig30)
	begin
		if (Clock'event and Clock = '0') then
			if (L1Keep = '0') then
				case PIP_C10 is
					when 0 =>
						P00_10 <= Trig30;
					when 1 =>
						P01_10 <= Trig30;
					when 2 =>
						P02_10 <= Trig30;
					when 3 =>
						P03_10 <= Trig30;
					when 4 =>
						P04_10 <= Trig30;
					when 5 =>
						P05_10 <= Trig30;
					when 6 =>
						P06_10 <= Trig30;
					when 7 =>
						P07_10 <= Trig30;
					when 8 =>
						P08_10 <= Trig30;
					when 9 =>
						P09_10 <= Trig30;
					when 10 =>
						P10_10 <= Trig30;
					when 11 =>
						P11_10 <= Trig30;
					when 12 =>
						P12_10 <= Trig30;
					when 13 =>
						P13_10 <= Trig30;
					when 14 =>
						P14_10 <= Trig30;
					when 15 =>
						P15_10 <= Trig30;
					when 16 =>
						P16_10 <= Trig30;
					when 17 =>
						P17_10 <= Trig30;
					when 18 =>
						P18_10 <= Trig30;
					when 19 =>
						P19_10 <= Trig30;
					when 20 =>
						P20_10 <= Trig30;
					when 21 =>
						P21_10 <= Trig30;
					when 22 =>
						P22_10 <= Trig30;
					when 23 =>
						P23_10 <= Trig30;
					when 24 =>
						P24_10 <= Trig30;
					when 25 =>
						P25_10 <= Trig30;
					when 26 =>
						P26_10 <= Trig30;
					when 27 =>
						P27_10 <= Trig30;
					when 28 =>
						P28_10 <= Trig30;
					when 29 =>
						P29_10 <= Trig30;
					when 30 =>
						P30_10 <= Trig30;
					when others =>
						P31_10 <= Trig30;
				end case;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1Keep, PIP_C11, Trig31)
	begin
		if (Clock'event and Clock = '0') then
			if (L1Keep = '0') then
				case PIP_C11 is
					when 0 =>
						P00_11 <= Trig31;
					when 1 =>
						P01_11 <= Trig31;
					when 2 =>
						P02_11 <= Trig31;
					when 3 =>
						P03_11 <= Trig31;
					when 4 =>
						P04_11 <= Trig31;
					when 5 =>
						P05_11 <= Trig31;
					when 6 =>
						P06_11 <= Trig31;
					when 7 =>
						P07_11 <= Trig31;
					when 8 =>
						P08_11 <= Trig31;
					when 9 =>
						P09_11 <= Trig31;
					when 10 =>
						P10_11 <= Trig31;
					when 11 =>
						P11_11 <= Trig31;
					when 12 =>
						P12_11 <= Trig31;
					when 13 =>
						P13_11 <= Trig31;
					when 14 =>
						P14_11 <= Trig31;
					when 15 =>
						P15_11 <= Trig31;
					when 16 =>
						P16_11 <= Trig31;
					when 17 =>
						P17_11 <= Trig31;
					when 18 =>
						P18_11 <= Trig31;
					when 19 =>
						P19_11 <= Trig31;
					when 20 =>
						P20_11 <= Trig31;
					when 21 =>
						P21_11 <= Trig31;
					when 22 =>
						P22_11 <= Trig31;
					when 23 =>
						P23_11 <= Trig31;
					when 24 =>
						P24_11 <= Trig31;
					when 25 =>
						P25_11 <= Trig31;
					when 26 =>
						P26_11 <= Trig31;
					when 27 =>
						P27_11 <= Trig31;
					when 28 =>
						P28_11 <= Trig31;
					when 29 =>
						P29_11 <= Trig31;
					when 30 =>
						P30_11 <= Trig31;
					when others =>
						P31_11 <= Trig31;
				end case;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1Keep, PIP_C12, Trig40)
	begin
		if (Clock'event and Clock = '0') then
			if (L1Keep = '0') then
				case PIP_C12 is
					when 0 =>
						P00_12 <= Trig40;
					when 1 =>
						P01_12 <= Trig40;
					when 2 =>
						P02_12 <= Trig40;
					when 3 =>
						P03_12 <= Trig40;
					when 4 =>
						P04_12 <= Trig40;
					when 5 =>
						P05_12 <= Trig40;
					when 6 =>
						P06_12 <= Trig40;
					when 7 =>
						P07_12 <= Trig40;
					when 8 =>
						P08_12 <= Trig40;
					when 9 =>
						P09_12 <= Trig40;
					when 10 =>
						P10_12 <= Trig40;
					when 11 =>
						P11_12 <= Trig40;
					when 12 =>
						P12_12 <= Trig40;
					when 13 =>
						P13_12 <= Trig40;
					when 14 =>
						P14_12 <= Trig40;
					when 15 =>
						P15_12 <= Trig40;
					when 16 =>
						P16_12 <= Trig40;
					when 17 =>
						P17_12 <= Trig40;
					when 18 =>
						P18_12 <= Trig40;
					when 19 =>
						P19_12 <= Trig40;
					when 20 =>
						P20_12 <= Trig40;
					when 21 =>
						P21_12 <= Trig40;
					when 22 =>
						P22_12 <= Trig40;
					when 23 =>
						P23_12 <= Trig40;
					when 24 =>
						P24_12 <= Trig40;
					when 25 =>
						P25_12 <= Trig40;
					when 26 =>
						P26_12 <= Trig40;
					when 27 =>
						P27_12 <= Trig40;
					when 28 =>
						P28_12 <= Trig40;
					when 29 =>
						P29_12 <= Trig40;
					when 30 =>
						P30_12 <= Trig40;
					when others =>
						P31_12 <= Trig40;
				end case;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1Keep, PIP_C13, Trig41)
	begin
		if (Clock'event and Clock = '0') then
			if (L1Keep = '0') then
				case PIP_C13 is
					when 0 =>
						P00_13 <= Trig41;
					when 1 =>
						P01_13 <= Trig41;
					when 2 =>
						P02_13 <= Trig41;
					when 3 =>
						P03_13 <= Trig41;
					when 4 =>
						P04_13 <= Trig41;
					when 5 =>
						P05_13 <= Trig41;
					when 6 =>
						P06_13 <= Trig41;
					when 7 =>
						P07_13 <= Trig41;
					when 8 =>
						P08_13 <= Trig41;
					when 9 =>
						P09_13 <= Trig41;
					when 10 =>
						P10_13 <= Trig41;
					when 11 =>
						P11_13 <= Trig41;
					when 12 =>
						P12_13 <= Trig41;
					when 13 =>
						P13_13 <= Trig41;
					when 14 =>
						P14_13 <= Trig41;
					when 15 =>
						P15_13 <= Trig41;
					when 16 =>
						P16_13 <= Trig41;
					when 17 =>
						P17_13 <= Trig41;
					when 18 =>
						P18_13 <= Trig41;
					when 19 =>
						P19_13 <= Trig41;
					when 20 =>
						P20_13 <= Trig41;
					when 21 =>
						P21_13 <= Trig41;
					when 22 =>
						P22_13 <= Trig41;
					when 23 =>
						P23_13 <= Trig41;
					when 24 =>
						P24_13 <= Trig41;
					when 25 =>
						P25_13 <= Trig41;
					when 26 =>
						P26_13 <= Trig41;
					when 27 =>
						P27_13 <= Trig41;
					when 28 =>
						P28_13 <= Trig41;
					when 29 =>
						P29_13 <= Trig41;
					when 30 =>
						P30_13 <= Trig41;
					when others =>
						P31_13 <= Trig41;
				end case;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1Keep, PIP_C14, Trig50)
	begin
		if (Clock'event and Clock = '0') then
			if (L1Keep = '0') then
				case PIP_C14 is
					when 0 =>
						P00_14 <= Trig50;
					when 1 =>
						P01_14 <= Trig50;
					when 2 =>
						P02_14 <= Trig50;
					when 3 =>
						P03_14 <= Trig50;
					when 4 =>
						P04_14 <= Trig50;
					when 5 =>
						P05_14 <= Trig50;
					when 6 =>
						P06_14 <= Trig50;
					when 7 =>
						P07_14 <= Trig50;
					when 8 =>
						P08_14 <= Trig50;
					when 9 =>
						P09_14 <= Trig50;
					when 10 =>
						P10_14 <= Trig50;
					when 11 =>
						P11_14 <= Trig50;
					when 12 =>
						P12_14 <= Trig50;
					when 13 =>
						P13_14 <= Trig50;
					when 14 =>
						P14_14 <= Trig50;
					when 15 =>
						P15_14 <= Trig50;
					when 16 =>
						P16_14 <= Trig50;
					when 17 =>
						P17_14 <= Trig50;
					when 18 =>
						P18_14 <= Trig50;
					when 19 =>
						P19_14 <= Trig50;
					when 20 =>
						P20_14 <= Trig50;
					when 21 =>
						P21_14 <= Trig50;
					when 22 =>
						P22_14 <= Trig50;
					when 23 =>
						P23_14 <= Trig50;
					when 24 =>
						P24_14 <= Trig50;
					when 25 =>
						P25_14 <= Trig50;
					when 26 =>
						P26_14 <= Trig50;
					when 27 =>
						P27_14 <= Trig50;
					when 28 =>
						P28_14 <= Trig50;
					when 29 =>
						P29_14 <= Trig50;
					when 30 =>
						P30_14 <= Trig50;
					when others =>
						P31_14 <= Trig50;
				end case;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1Keep, PIP_C15, Trig51)
	begin
		if (Clock'event and Clock = '0') then
			if (L1Keep = '0') then
				case PIP_C15 is
					when 0 =>
						P00_15 <= Trig51;
					when 1 =>
						P01_15 <= Trig51;
					when 2 =>
						P02_15 <= Trig51;
					when 3 =>
						P03_15 <= Trig51;
					when 4 =>
						P04_15 <= Trig51;
					when 5 =>
						P05_15 <= Trig51;
					when 6 =>
						P06_15 <= Trig51;
					when 7 =>
						P07_15 <= Trig51;
					when 8 =>
						P08_15 <= Trig51;
					when 9 =>
						P09_15 <= Trig51;
					when 10 =>
						P10_15 <= Trig51;
					when 11 =>
						P11_15 <= Trig51;
					when 12 =>
						P12_15 <= Trig51;
					when 13 =>
						P13_15 <= Trig51;
					when 14 =>
						P14_15 <= Trig51;
					when 15 =>
						P15_15 <= Trig51;
					when 16 =>
						P16_15 <= Trig51;
					when 17 =>
						P17_15 <= Trig51;
					when 18 =>
						P18_15 <= Trig51;
					when 19 =>
						P19_15 <= Trig51;
					when 20 =>
						P20_15 <= Trig51;
					when 21 =>
						P21_15 <= Trig51;
					when 22 =>
						P22_15 <= Trig51;
					when 23 =>
						P23_15 <= Trig51;
					when 24 =>
						P24_15 <= Trig51;
					when 25 =>
						P25_15 <= Trig51;
					when 26 =>
						P26_15 <= Trig51;
					when 27 =>
						P27_15 <= Trig51;
					when 28 =>
						P28_15 <= Trig51;
					when 29 =>
						P29_15 <= Trig51;
					when 30 =>
						P30_15 <= Trig51;
					when others =>
						P31_15 <= Trig51;
				end case;
			else
				null;
			end if;
		end if;
	end process;
-------------------------
	process(Clock, L1Keep, PIP_CL1, Answer)
	begin
		if (Clock'event and Clock = '0') then
			if (L1Keep = '0') then
				case PIP_CL1 is
					when 0 =>
						P00_L1 <= Answer;
					when 1 =>
						P01_L1 <= Answer;
					when 2 =>
						P02_L1 <= Answer;
					when 3 =>
						P03_L1 <= Answer;
					when 4 =>
						P04_L1 <= Answer;
					when 5 =>
						P05_L1 <= Answer;
					when 6 =>
						P06_L1 <= Answer;
					when 7 =>
						P07_L1 <= Answer;
					when 8 =>
						P08_L1 <= Answer;
					when 9 =>
						P09_L1 <= Answer;
					when 10 =>
						P10_L1 <= Answer;
					when 11 =>
						P11_L1 <= Answer;
					when 12 =>
						P12_L1 <= Answer;
					when 13 =>
						P13_L1 <= Answer;
					when 14 =>
						P14_L1 <= Answer;
					when 15 =>
						P15_L1 <= Answer;
					when 16 =>
						P16_L1 <= Answer;
					when 17 =>
						P17_L1 <= Answer;
					when 18 =>
						P18_L1 <= Answer;
					when 19 =>
						P19_L1 <= Answer;
					when 20 =>
						P20_L1 <= Answer;
					when 21 =>
						P21_L1 <= Answer;
					when 22 =>
						P22_L1 <= Answer;
					when 23 =>
						P23_L1 <= Answer;
					when 24 =>
						P24_L1 <= Answer;
					when 25 =>
						P25_L1 <= Answer;
					when 26 =>
						P26_L1 <= Answer;
					when 27 =>
						P27_L1 <= Answer;
					when 28 =>
						P28_L1 <= Answer;
					when 29 =>
						P29_L1 <= Answer;
					when 30 =>
						P30_L1 <= Answer;
					when others =>
						P31_L1 <= Answer;
				end case;
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Select output data (Clock ->)
--------------------------------------------
	process(PIP_S00,
			P00_00, P01_00, P02_00, P03_00,
			P04_00, P05_00, P06_00, P07_00,
			P08_00, P09_00, P10_00, P11_00,
			P12_00, P13_00, P14_00, P15_00,
			P16_00, P17_00, P18_00, P19_00,
			P20_00, P21_00, P22_00, P23_00,
			P24_00, P25_00, P26_00, P27_00,
			P28_00, P29_00, P30_00, P31_00)
	begin
		case PIP_S00 is
			when 0 =>
				PIP_OUT00 <= P00_00;
			when 1 =>
				PIP_OUT00 <= P01_00;
			when 2 =>
				PIP_OUT00 <= P02_00;
			when 3 =>
				PIP_OUT00 <= P03_00;
			when 4 =>
				PIP_OUT00 <= P04_00;
			when 5 =>
				PIP_OUT00 <= P05_00;
			when 6 =>
				PIP_OUT00 <= P06_00;
			when 7 =>
				PIP_OUT00 <= P07_00;
			when 8 =>
				PIP_OUT00 <= P08_00;
			when 9 =>
				PIP_OUT00 <= P09_00;
			when 10 =>
				PIP_OUT00 <= P10_00;
			when 11 =>
				PIP_OUT00 <= P11_00;
			when 12 =>
				PIP_OUT00 <= P12_00;
			when 13 =>
				PIP_OUT00 <= P13_00;
			when 14 =>
				PIP_OUT00 <= P14_00;
			when 15 =>
				PIP_OUT00 <= P15_00;
			when 16 =>
				PIP_OUT00 <= P16_00;
			when 17 =>
				PIP_OUT00 <= P17_00;
			when 18 =>
				PIP_OUT00 <= P18_00;
			when 19 =>
				PIP_OUT00 <= P19_00;
			when 20 =>
				PIP_OUT00 <= P20_00;
			when 21 =>
				PIP_OUT00 <= P21_00;
			when 22 =>
				PIP_OUT00 <= P22_00;
			when 23 =>
				PIP_OUT00 <= P23_00;
			when 24 =>
				PIP_OUT00 <= P24_00;
			when 25 =>
				PIP_OUT00 <= P25_00;
			when 26 =>
				PIP_OUT00 <= P26_00;
			when 27 =>
				PIP_OUT00 <= P27_00;
			when 28 =>
				PIP_OUT00 <= P28_00;
			when 29 =>
				PIP_OUT00 <= P29_00;
			when 30 =>
				PIP_OUT00 <= P30_00;
			when others =>
				PIP_OUT00 <= P31_00;
		end case;
	end process;
-------------------------
	process(PIP_S01,
			P00_01, P01_01, P02_01, P03_01,
			P04_01, P05_01, P06_01, P07_01,
			P08_01, P09_01, P10_01, P11_01,
			P12_01, P13_01, P14_01, P15_01,
			P16_01, P17_01, P18_01, P19_01,
			P20_01, P21_01, P22_01, P23_01,
			P24_01, P25_01, P26_01, P27_01,
			P28_01, P29_01, P30_01, P31_01)
	begin
		case PIP_S01 is
			when 0 =>
				PIP_OUT01 <= P00_01;
			when 1 =>
				PIP_OUT01 <= P01_01;
			when 2 =>
				PIP_OUT01 <= P02_01;
			when 3 =>
				PIP_OUT01 <= P03_01;
			when 4 =>
				PIP_OUT01 <= P04_01;
			when 5 =>
				PIP_OUT01 <= P05_01;
			when 6 =>
				PIP_OUT01 <= P06_01;
			when 7 =>
				PIP_OUT01 <= P07_01;
			when 8 =>
				PIP_OUT01 <= P08_01;
			when 9 =>
				PIP_OUT01 <= P09_01;
			when 10 =>
				PIP_OUT01 <= P10_01;
			when 11 =>
				PIP_OUT01 <= P11_01;
			when 12 =>
				PIP_OUT01 <= P12_01;
			when 13 =>
				PIP_OUT01 <= P13_01;
			when 14 =>
				PIP_OUT01 <= P14_01;
			when 15 =>
				PIP_OUT01 <= P15_01;
			when 16 =>
				PIP_OUT01 <= P16_01;
			when 17 =>
				PIP_OUT01 <= P17_01;
			when 18 =>
				PIP_OUT01 <= P18_01;
			when 19 =>
				PIP_OUT01 <= P19_01;
			when 20 =>
				PIP_OUT01 <= P20_01;
			when 21 =>
				PIP_OUT01 <= P21_01;
			when 22 =>
				PIP_OUT01 <= P22_01;
			when 23 =>
				PIP_OUT01 <= P23_01;
			when 24 =>
				PIP_OUT01 <= P24_01;
			when 25 =>
				PIP_OUT01 <= P25_01;
			when 26 =>
				PIP_OUT01 <= P26_01;
			when 27 =>
				PIP_OUT01 <= P27_01;
			when 28 =>
				PIP_OUT01 <= P28_01;
			when 29 =>
				PIP_OUT01 <= P29_01;
			when 30 =>
				PIP_OUT01 <= P30_01;
			when others =>
				PIP_OUT01 <= P31_01;
		end case;
	end process;
-------------------------
	process(PIP_S02,
			P00_02, P01_02, P02_02, P03_02,
			P04_02, P05_02, P06_02, P07_02,
			P08_02, P09_02, P10_02, P11_02,
			P12_02, P13_02, P14_02, P15_02,
			P16_02, P17_02, P18_02, P19_02,
			P20_02, P21_02, P22_02, P23_02,
			P24_02, P25_02, P26_02, P27_02,
			P28_02, P29_02, P30_02, P31_02)
	begin
		case PIP_S02 is
			when 0 =>
				PIP_OUT02 <= P00_02;
			when 1 =>
				PIP_OUT02 <= P01_02;
			when 2 =>
				PIP_OUT02 <= P02_02;
			when 3 =>
				PIP_OUT02 <= P03_02;
			when 4 =>
				PIP_OUT02 <= P04_02;
			when 5 =>
				PIP_OUT02 <= P05_02;
			when 6 =>
				PIP_OUT02 <= P06_02;
			when 7 =>
				PIP_OUT02 <= P07_02;
			when 8 =>
				PIP_OUT02 <= P08_02;
			when 9 =>
				PIP_OUT02 <= P09_02;
			when 10 =>
				PIP_OUT02 <= P10_02;
			when 11 =>
				PIP_OUT02 <= P11_02;
			when 12 =>
				PIP_OUT02 <= P12_02;
			when 13 =>
				PIP_OUT02 <= P13_02;
			when 14 =>
				PIP_OUT02 <= P14_02;
			when 15 =>
				PIP_OUT02 <= P15_02;
			when 16 =>
				PIP_OUT02 <= P16_02;
			when 17 =>
				PIP_OUT02 <= P17_02;
			when 18 =>
				PIP_OUT02 <= P18_02;
			when 19 =>
				PIP_OUT02 <= P19_02;
			when 20 =>
				PIP_OUT02 <= P20_02;
			when 21 =>
				PIP_OUT02 <= P21_02;
			when 22 =>
				PIP_OUT02 <= P22_02;
			when 23 =>
				PIP_OUT02 <= P23_02;
			when 24 =>
				PIP_OUT02 <= P24_02;
			when 25 =>
				PIP_OUT02 <= P25_02;
			when 26 =>
				PIP_OUT02 <= P26_02;
			when 27 =>
				PIP_OUT02 <= P27_02;
			when 28 =>
				PIP_OUT02 <= P28_02;
			when 29 =>
				PIP_OUT02 <= P29_02;
			when 30 =>
				PIP_OUT02 <= P30_02;
			when others =>
				PIP_OUT02 <= P31_02;
		end case;
	end process;
-------------------------
	process(PIP_S03,
			P00_03, P01_03, P02_03, P03_03,
			P04_03, P05_03, P06_03, P07_03,
			P08_03, P09_03, P10_03, P11_03,
			P12_03, P13_03, P14_03, P15_03,
			P16_03, P17_03, P18_03, P19_03,
			P20_03, P21_03, P22_03, P23_03,
			P24_03, P25_03, P26_03, P27_03,
			P28_03, P29_03, P30_03, P31_03)
	begin
		case PIP_S03 is
			when 0 =>
				PIP_OUT03 <= P00_03;
			when 1 =>
				PIP_OUT03 <= P01_03;
			when 2 =>
				PIP_OUT03 <= P02_03;
			when 3 =>
				PIP_OUT03 <= P03_03;
			when 4 =>
				PIP_OUT03 <= P04_03;
			when 5 =>
				PIP_OUT03 <= P05_03;
			when 6 =>
				PIP_OUT03 <= P06_03;
			when 7 =>
				PIP_OUT03 <= P07_03;
			when 8 =>
				PIP_OUT03 <= P08_03;
			when 9 =>
				PIP_OUT03 <= P09_03;
			when 10 =>
				PIP_OUT03 <= P10_03;
			when 11 =>
				PIP_OUT03 <= P11_03;
			when 12 =>
				PIP_OUT03 <= P12_03;
			when 13 =>
				PIP_OUT03 <= P13_03;
			when 14 =>
				PIP_OUT03 <= P14_03;
			when 15 =>
				PIP_OUT03 <= P15_03;
			when 16 =>
				PIP_OUT03 <= P16_03;
			when 17 =>
				PIP_OUT03 <= P17_03;
			when 18 =>
				PIP_OUT03 <= P18_03;
			when 19 =>
				PIP_OUT03 <= P19_03;
			when 20 =>
				PIP_OUT03 <= P20_03;
			when 21 =>
				PIP_OUT03 <= P21_03;
			when 22 =>
				PIP_OUT03 <= P22_03;
			when 23 =>
				PIP_OUT03 <= P23_03;
			when 24 =>
				PIP_OUT03 <= P24_03;
			when 25 =>
				PIP_OUT03 <= P25_03;
			when 26 =>
				PIP_OUT03 <= P26_03;
			when 27 =>
				PIP_OUT03 <= P27_03;
			when 28 =>
				PIP_OUT03 <= P28_03;
			when 29 =>
				PIP_OUT03 <= P29_03;
			when 30 =>
				PIP_OUT03 <= P30_03;
			when others =>
				PIP_OUT03 <= P31_03;
		end case;
	end process;
-------------------------
	process(PIP_S04,
			P00_04, P01_04, P02_04, P03_04,
			P04_04, P05_04, P06_04, P07_04,
			P08_04, P09_04, P10_04, P11_04,
			P12_04, P13_04, P14_04, P15_04,
			P16_04, P17_04, P18_04, P19_04,
			P20_04, P21_04, P22_04, P23_04,
			P24_04, P25_04, P26_04, P27_04,
			P28_04, P29_04, P30_04, P31_04)
	begin
		case PIP_S04 is
			when 0 =>
				PIP_OUT04 <= P00_04;
			when 1 =>
				PIP_OUT04 <= P01_04;
			when 2 =>
				PIP_OUT04 <= P02_04;
			when 3 =>
				PIP_OUT04 <= P03_04;
			when 4 =>
				PIP_OUT04 <= P04_04;
			when 5 =>
				PIP_OUT04 <= P05_04;
			when 6 =>
				PIP_OUT04 <= P06_04;
			when 7 =>
				PIP_OUT04 <= P07_04;
			when 8 =>
				PIP_OUT04 <= P08_04;
			when 9 =>
				PIP_OUT04 <= P09_04;
			when 10 =>
				PIP_OUT04 <= P10_04;
			when 11 =>
				PIP_OUT04 <= P11_04;
			when 12 =>
				PIP_OUT04 <= P12_04;
			when 13 =>
				PIP_OUT04 <= P13_04;
			when 14 =>
				PIP_OUT04 <= P14_04;
			when 15 =>
				PIP_OUT04 <= P15_04;
			when 16 =>
				PIP_OUT04 <= P16_04;
			when 17 =>
				PIP_OUT04 <= P17_04;
			when 18 =>
				PIP_OUT04 <= P18_04;
			when 19 =>
				PIP_OUT04 <= P19_04;
			when 20 =>
				PIP_OUT04 <= P20_04;
			when 21 =>
				PIP_OUT04 <= P21_04;
			when 22 =>
				PIP_OUT04 <= P22_04;
			when 23 =>
				PIP_OUT04 <= P23_04;
			when 24 =>
				PIP_OUT04 <= P24_04;
			when 25 =>
				PIP_OUT04 <= P25_04;
			when 26 =>
				PIP_OUT04 <= P26_04;
			when 27 =>
				PIP_OUT04 <= P27_04;
			when 28 =>
				PIP_OUT04 <= P28_04;
			when 29 =>
				PIP_OUT04 <= P29_04;
			when 30 =>
				PIP_OUT04 <= P30_04;
			when others =>
				PIP_OUT04 <= P31_04;
		end case;
	end process;
-------------------------
	process(PIP_S05,
			P00_05, P01_05, P02_05, P03_05,
			P04_05, P05_05, P06_05, P07_05,
			P08_05, P09_05, P10_05, P11_05,
			P12_05, P13_05, P14_05, P15_05,
			P16_05, P17_05, P18_05, P19_05,
			P20_05, P21_05, P22_05, P23_05,
			P24_05, P25_05, P26_05, P27_05,
			P28_05, P29_05, P30_05, P31_05)
	begin
		case PIP_S05 is
			when 0 =>
				PIP_OUT05 <= P00_05;
			when 1 =>
				PIP_OUT05 <= P01_05;
			when 2 =>
				PIP_OUT05 <= P02_05;
			when 3 =>
				PIP_OUT05 <= P03_05;
			when 4 =>
				PIP_OUT05 <= P04_05;
			when 5 =>
				PIP_OUT05 <= P05_05;
			when 6 =>
				PIP_OUT05 <= P06_05;
			when 7 =>
				PIP_OUT05 <= P07_05;
			when 8 =>
				PIP_OUT05 <= P08_05;
			when 9 =>
				PIP_OUT05 <= P09_05;
			when 10 =>
				PIP_OUT05 <= P10_05;
			when 11 =>
				PIP_OUT05 <= P11_05;
			when 12 =>
				PIP_OUT05 <= P12_05;
			when 13 =>
				PIP_OUT05 <= P13_05;
			when 14 =>
				PIP_OUT05 <= P14_05;
			when 15 =>
				PIP_OUT05 <= P15_05;
			when 16 =>
				PIP_OUT05 <= P16_05;
			when 17 =>
				PIP_OUT05 <= P17_05;
			when 18 =>
				PIP_OUT05 <= P18_05;
			when 19 =>
				PIP_OUT05 <= P19_05;
			when 20 =>
				PIP_OUT05 <= P20_05;
			when 21 =>
				PIP_OUT05 <= P21_05;
			when 22 =>
				PIP_OUT05 <= P22_05;
			when 23 =>
				PIP_OUT05 <= P23_05;
			when 24 =>
				PIP_OUT05 <= P24_05;
			when 25 =>
				PIP_OUT05 <= P25_05;
			when 26 =>
				PIP_OUT05 <= P26_05;
			when 27 =>
				PIP_OUT05 <= P27_05;
			when 28 =>
				PIP_OUT05 <= P28_05;
			when 29 =>
				PIP_OUT05 <= P29_05;
			when 30 =>
				PIP_OUT05 <= P30_05;
			when others =>
				PIP_OUT05 <= P31_05;
		end case;
	end process;
-------------------------
	process(PIP_S10,
			P00_10, P01_10, P02_10, P03_10,
			P04_10, P05_10, P06_10, P07_10,
			P08_10, P09_10, P10_10, P11_10,
			P12_10, P13_10, P14_10, P15_10,
			P16_10, P17_10, P18_10, P19_10,
			P20_10, P21_10, P22_10, P23_10,
			P24_10, P25_10, P26_10, P27_10,
			P28_10, P29_10, P30_10, P31_10)
	begin
		case PIP_S10 is
			when 0 =>
				PIP_OUT10 <= P00_10;
			when 1 =>
				PIP_OUT10 <= P01_10;
			when 2 =>
				PIP_OUT10 <= P02_10;
			when 3 =>
				PIP_OUT10 <= P03_10;
			when 4 =>
				PIP_OUT10 <= P04_10;
			when 5 =>
				PIP_OUT10 <= P05_10;
			when 6 =>
				PIP_OUT10 <= P06_10;
			when 7 =>
				PIP_OUT10 <= P07_10;
			when 8 =>
				PIP_OUT10 <= P08_10;
			when 9 =>
				PIP_OUT10 <= P09_10;
			when 10 =>
				PIP_OUT10 <= P10_10;
			when 11 =>
				PIP_OUT10 <= P11_10;
			when 12 =>
				PIP_OUT10 <= P12_10;
			when 13 =>
				PIP_OUT10 <= P13_10;
			when 14 =>
				PIP_OUT10 <= P14_10;
			when 15 =>
				PIP_OUT10 <= P15_10;
			when 16 =>
				PIP_OUT10 <= P16_10;
			when 17 =>
				PIP_OUT10 <= P17_10;
			when 18 =>
				PIP_OUT10 <= P18_10;
			when 19 =>
				PIP_OUT10 <= P19_10;
			when 20 =>
				PIP_OUT10 <= P20_10;
			when 21 =>
				PIP_OUT10 <= P21_10;
			when 22 =>
				PIP_OUT10 <= P22_10;
			when 23 =>
				PIP_OUT10 <= P23_10;
			when 24 =>
				PIP_OUT10 <= P24_10;
			when 25 =>
				PIP_OUT10 <= P25_10;
			when 26 =>
				PIP_OUT10 <= P26_10;
			when 27 =>
				PIP_OUT10 <= P27_10;
			when 28 =>
				PIP_OUT10 <= P28_10;
			when 29 =>
				PIP_OUT10 <= P29_10;
			when 30 =>
				PIP_OUT10 <= P30_10;
			when others =>
				PIP_OUT10 <= P31_10;
		end case;
	end process;
-------------------------
	process(PIP_S11,
			P00_11, P01_11, P02_11, P03_11,
			P04_11, P05_11, P06_11, P07_11,
			P08_11, P09_11, P10_11, P11_11,
			P12_11, P13_11, P14_11, P15_11,
			P16_11, P17_11, P18_11, P19_11,
			P20_11, P21_11, P22_11, P23_11,
			P24_11, P25_11, P26_11, P27_11,
			P28_11, P29_11, P30_11, P31_11)
	begin
		case PIP_S11 is
			when 0 =>
				PIP_OUT11 <= P00_11;
			when 1 =>
				PIP_OUT11 <= P01_11;
			when 2 =>
				PIP_OUT11 <= P02_11;
			when 3 =>
				PIP_OUT11 <= P03_11;
			when 4 =>
				PIP_OUT11 <= P04_11;
			when 5 =>
				PIP_OUT11 <= P05_11;
			when 6 =>
				PIP_OUT11 <= P06_11;
			when 7 =>
				PIP_OUT11 <= P07_11;
			when 8 =>
				PIP_OUT11 <= P08_11;
			when 9 =>
				PIP_OUT11 <= P09_11;
			when 10 =>
				PIP_OUT11 <= P10_11;
			when 11 =>
				PIP_OUT11 <= P11_11;
			when 12 =>
				PIP_OUT11 <= P12_11;
			when 13 =>
				PIP_OUT11 <= P13_11;
			when 14 =>
				PIP_OUT11 <= P14_11;
			when 15 =>
				PIP_OUT11 <= P15_11;
			when 16 =>
				PIP_OUT11 <= P16_11;
			when 17 =>
				PIP_OUT11 <= P17_11;
			when 18 =>
				PIP_OUT11 <= P18_11;
			when 19 =>
				PIP_OUT11 <= P19_11;
			when 20 =>
				PIP_OUT11 <= P20_11;
			when 21 =>
				PIP_OUT11 <= P21_11;
			when 22 =>
				PIP_OUT11 <= P22_11;
			when 23 =>
				PIP_OUT11 <= P23_11;
			when 24 =>
				PIP_OUT11 <= P24_11;
			when 25 =>
				PIP_OUT11 <= P25_11;
			when 26 =>
				PIP_OUT11 <= P26_11;
			when 27 =>
				PIP_OUT11 <= P27_11;
			when 28 =>
				PIP_OUT11 <= P28_11;
			when 29 =>
				PIP_OUT11 <= P29_11;
			when 30 =>
				PIP_OUT11 <= P30_11;
			when others =>
				PIP_OUT11 <= P31_11;
		end case;
	end process;
-------------------------
	process(PIP_S12,
			P00_12, P01_12, P02_12, P03_12,
			P04_12, P05_12, P06_12, P07_12,
			P08_12, P09_12, P10_12, P11_12,
			P12_12, P13_12, P14_12, P15_12,
			P16_12, P17_12, P18_12, P19_12,
			P20_12, P21_12, P22_12, P23_12,
			P24_12, P25_12, P26_12, P27_12,
			P28_12, P29_12, P30_12, P31_12)
	begin
		case PIP_S12 is
			when 0 =>
				PIP_OUT12 <= P00_12;
			when 1 =>
				PIP_OUT12 <= P01_12;
			when 2 =>
				PIP_OUT12 <= P02_12;
			when 3 =>
				PIP_OUT12 <= P03_12;
			when 4 =>
				PIP_OUT12 <= P04_12;
			when 5 =>
				PIP_OUT12 <= P05_12;
			when 6 =>
				PIP_OUT12 <= P06_12;
			when 7 =>
				PIP_OUT12 <= P07_12;
			when 8 =>
				PIP_OUT12 <= P08_12;
			when 9 =>
				PIP_OUT12 <= P09_12;
			when 10 =>
				PIP_OUT12 <= P10_12;
			when 11 =>
				PIP_OUT12 <= P11_12;
			when 12 =>
				PIP_OUT12 <= P12_12;
			when 13 =>
				PIP_OUT12 <= P13_12;
			when 14 =>
				PIP_OUT12 <= P14_12;
			when 15 =>
				PIP_OUT12 <= P15_12;
			when 16 =>
				PIP_OUT12 <= P16_12;
			when 17 =>
				PIP_OUT12 <= P17_12;
			when 18 =>
				PIP_OUT12 <= P18_12;
			when 19 =>
				PIP_OUT12 <= P19_12;
			when 20 =>
				PIP_OUT12 <= P20_12;
			when 21 =>
				PIP_OUT12 <= P21_12;
			when 22 =>
				PIP_OUT12 <= P22_12;
			when 23 =>
				PIP_OUT12 <= P23_12;
			when 24 =>
				PIP_OUT12 <= P24_12;
			when 25 =>
				PIP_OUT12 <= P25_12;
			when 26 =>
				PIP_OUT12 <= P26_12;
			when 27 =>
				PIP_OUT12 <= P27_12;
			when 28 =>
				PIP_OUT12 <= P28_12;
			when 29 =>
				PIP_OUT12 <= P29_12;
			when 30 =>
				PIP_OUT12 <= P30_12;
			when others =>
				PIP_OUT12 <= P31_12;
		end case;
	end process;
-------------------------
	process(PIP_S13,
			P00_13, P01_13, P02_13, P03_13,
			P04_13, P05_13, P06_13, P07_13,
			P08_13, P09_13, P10_13, P11_13,
			P12_13, P13_13, P14_13, P15_13,
			P16_13, P17_13, P18_13, P19_13,
			P20_13, P21_13, P22_13, P23_13,
			P24_13, P25_13, P26_13, P27_13,
			P28_13, P29_13, P30_13, P31_13)
	begin
		case PIP_S13 is
			when 0 =>
				PIP_OUT13 <= P00_13;
			when 1 =>
				PIP_OUT13 <= P01_13;
			when 2 =>
				PIP_OUT13 <= P02_13;
			when 3 =>
				PIP_OUT13 <= P03_13;
			when 4 =>
				PIP_OUT13 <= P04_13;
			when 5 =>
				PIP_OUT13 <= P05_13;
			when 6 =>
				PIP_OUT13 <= P06_13;
			when 7 =>
				PIP_OUT13 <= P07_13;
			when 8 =>
				PIP_OUT13 <= P08_13;
			when 9 =>
				PIP_OUT13 <= P09_13;
			when 10 =>
				PIP_OUT13 <= P10_13;
			when 11 =>
				PIP_OUT13 <= P11_13;
			when 12 =>
				PIP_OUT13 <= P12_13;
			when 13 =>
				PIP_OUT13 <= P13_13;
			when 14 =>
				PIP_OUT13 <= P14_13;
			when 15 =>
				PIP_OUT13 <= P15_13;
			when 16 =>
				PIP_OUT13 <= P16_13;
			when 17 =>
				PIP_OUT13 <= P17_13;
			when 18 =>
				PIP_OUT13 <= P18_13;
			when 19 =>
				PIP_OUT13 <= P19_13;
			when 20 =>
				PIP_OUT13 <= P20_13;
			when 21 =>
				PIP_OUT13 <= P21_13;
			when 22 =>
				PIP_OUT13 <= P22_13;
			when 23 =>
				PIP_OUT13 <= P23_13;
			when 24 =>
				PIP_OUT13 <= P24_13;
			when 25 =>
				PIP_OUT13 <= P25_13;
			when 26 =>
				PIP_OUT13 <= P26_13;
			when 27 =>
				PIP_OUT13 <= P27_13;
			when 28 =>
				PIP_OUT13 <= P28_13;
			when 29 =>
				PIP_OUT13 <= P29_13;
			when 30 =>
				PIP_OUT13 <= P30_13;
			when others =>
				PIP_OUT13 <= P31_13;
		end case;
	end process;
-------------------------
	process(PIP_S14,
			P00_14, P01_14, P02_14, P03_14,
			P04_14, P05_14, P06_14, P07_14,
			P08_14, P09_14, P10_14, P11_14,
			P12_14, P13_14, P14_14, P15_14,
			P16_14, P17_14, P18_14, P19_14,
			P20_14, P21_14, P22_14, P23_14,
			P24_14, P25_14, P26_14, P27_14,
			P28_14, P29_14, P30_14, P31_14)
	begin
		case PIP_S14 is
			when 0 =>
				PIP_OUT14 <= P00_14;
			when 1 =>
				PIP_OUT14 <= P01_14;
			when 2 =>
				PIP_OUT14 <= P02_14;
			when 3 =>
				PIP_OUT14 <= P03_14;
			when 4 =>
				PIP_OUT14 <= P04_14;
			when 5 =>
				PIP_OUT14 <= P05_14;
			when 6 =>
				PIP_OUT14 <= P06_14;
			when 7 =>
				PIP_OUT14 <= P07_14;
			when 8 =>
				PIP_OUT14 <= P08_14;
			when 9 =>
				PIP_OUT14 <= P09_14;
			when 10 =>
				PIP_OUT14 <= P10_14;
			when 11 =>
				PIP_OUT14 <= P11_14;
			when 12 =>
				PIP_OUT14 <= P12_14;
			when 13 =>
				PIP_OUT14 <= P13_14;
			when 14 =>
				PIP_OUT14 <= P14_14;
			when 15 =>
				PIP_OUT14 <= P15_14;
			when 16 =>
				PIP_OUT14 <= P16_14;
			when 17 =>
				PIP_OUT14 <= P17_14;
			when 18 =>
				PIP_OUT14 <= P18_14;
			when 19 =>
				PIP_OUT14 <= P19_14;
			when 20 =>
				PIP_OUT14 <= P20_14;
			when 21 =>
				PIP_OUT14 <= P21_14;
			when 22 =>
				PIP_OUT14 <= P22_14;
			when 23 =>
				PIP_OUT14 <= P23_14;
			when 24 =>
				PIP_OUT14 <= P24_14;
			when 25 =>
				PIP_OUT14 <= P25_14;
			when 26 =>
				PIP_OUT14 <= P26_14;
			when 27 =>
				PIP_OUT14 <= P27_14;
			when 28 =>
				PIP_OUT14 <= P28_14;
			when 29 =>
				PIP_OUT14 <= P29_14;
			when 30 =>
				PIP_OUT14 <= P30_14;
			when others =>
				PIP_OUT14 <= P31_14;
		end case;
	end process;
-------------------------
	process(PIP_S15,
			P00_15, P01_15, P02_15, P03_15,
			P04_15, P05_15, P06_15, P07_15,
			P08_15, P09_15, P10_15, P11_15,
			P12_15, P13_15, P14_15, P15_15,
			P16_15, P17_15, P18_15, P19_15,
			P20_15, P21_15, P22_15, P23_15,
			P24_15, P25_15, P26_15, P27_15,
			P28_15, P29_15, P30_15, P31_15)
	begin
		case PIP_S15 is
			when 0 =>
				PIP_OUT15 <= P00_15;
			when 1 =>
				PIP_OUT15 <= P01_15;
			when 2 =>
				PIP_OUT15 <= P02_15;
			when 3 =>
				PIP_OUT15 <= P03_15;
			when 4 =>
				PIP_OUT15 <= P04_15;
			when 5 =>
				PIP_OUT15 <= P05_15;
			when 6 =>
				PIP_OUT15 <= P06_15;
			when 7 =>
				PIP_OUT15 <= P07_15;
			when 8 =>
				PIP_OUT15 <= P08_15;
			when 9 =>
				PIP_OUT15 <= P09_15;
			when 10 =>
				PIP_OUT15 <= P10_15;
			when 11 =>
				PIP_OUT15 <= P11_15;
			when 12 =>
				PIP_OUT15 <= P12_15;
			when 13 =>
				PIP_OUT15 <= P13_15;
			when 14 =>
				PIP_OUT15 <= P14_15;
			when 15 =>
				PIP_OUT15 <= P15_15;
			when 16 =>
				PIP_OUT15 <= P16_15;
			when 17 =>
				PIP_OUT15 <= P17_15;
			when 18 =>
				PIP_OUT15 <= P18_15;
			when 19 =>
				PIP_OUT15 <= P19_15;
			when 20 =>
				PIP_OUT15 <= P20_15;
			when 21 =>
				PIP_OUT15 <= P21_15;
			when 22 =>
				PIP_OUT15 <= P22_15;
			when 23 =>
				PIP_OUT15 <= P23_15;
			when 24 =>
				PIP_OUT15 <= P24_15;
			when 25 =>
				PIP_OUT15 <= P25_15;
			when 26 =>
				PIP_OUT15 <= P26_15;
			when 27 =>
				PIP_OUT15 <= P27_15;
			when 28 =>
				PIP_OUT15 <= P28_15;
			when 29 =>
				PIP_OUT15 <= P29_15;
			when 30 =>
				PIP_OUT15 <= P30_15;
			when others =>
				PIP_OUT15 <= P31_15;
		end case;
	end process;
-------------------------
	process(PIP_SL1,
			P00_L1, P01_L1, P02_L1, P03_L1,
			P04_L1, P05_L1, P06_L1, P07_L1,
			P08_L1, P09_L1, P10_L1, P11_L1,
			P12_L1, P13_L1, P14_L1, P15_L1,
			P16_L1, P17_L1, P18_L1, P19_L1,
			P20_L1, P21_L1, P22_L1, P23_L1,
			P24_L1, P25_L1, P26_L1, P27_L1,
			P28_L1, P29_L1, P30_L1, P31_L1)
	begin
		case PIP_SL1 is
			when 0 =>
				PIP_OUT <= P00_L1;
			when 1 =>
				PIP_OUT <= P01_L1;
			when 2 =>
				PIP_OUT <= P02_L1;
			when 3 =>
				PIP_OUT <= P03_L1;
			when 4 =>
				PIP_OUT <= P04_L1;
			when 5 =>
				PIP_OUT <= P05_L1;
			when 6 =>
				PIP_OUT <= P06_L1;
			when 7 =>
				PIP_OUT <= P07_L1;
			when 8 =>
				PIP_OUT <= P08_L1;
			when 9 =>
				PIP_OUT <= P09_L1;
			when 10 =>
				PIP_OUT <= P10_L1;
			when 11 =>
				PIP_OUT <= P11_L1;
			when 12 =>
				PIP_OUT <= P12_L1;
			when 13 =>
				PIP_OUT <= P13_L1;
			when 14 =>
				PIP_OUT <= P14_L1;
			when 15 =>
				PIP_OUT <= P15_L1;
			when 16 =>
				PIP_OUT <= P16_L1;
			when 17 =>
				PIP_OUT <= P17_L1;
			when 18 =>
				PIP_OUT <= P18_L1;
			when 19 =>
				PIP_OUT <= P19_L1;
			when 20 =>
				PIP_OUT <= P20_L1;
			when 21 =>
				PIP_OUT <= P21_L1;
			when 22 =>
				PIP_OUT <= P22_L1;
			when 23 =>
				PIP_OUT <= P23_L1;
			when 24 =>
				PIP_OUT <= P24_L1;
			when 25 =>
				PIP_OUT <= P25_L1;
			when 26 =>
				PIP_OUT <= P26_L1;
			when 27 =>
				PIP_OUT <= P27_L1;
			when 28 =>
				PIP_OUT <= P28_L1;
			when 29 =>
				PIP_OUT <= P29_L1;
			when 30 =>
				PIP_OUT <= P30_L1;
			when others =>
				PIP_OUT <= P31_L1;
		end case;
	end process;
--------------------------------------------

-- Cluster counter - it is reset for rejected
-- events, the raw data readout is terminated.
--------------------------------------------
	process(Clock, L1Keep, CLS_GTE)
	begin
		if (Clock'event and Clock = '0') then
			if (L1Keep = '0') then
				CLS_CNT <= 0;
			elsif (CLS_GTE = '1') then
				CLS_CNT <= CLS_CNT + 1;
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Gate for the cluster counter (Clock ->)
-- After the interrupted readout the gate
-- remains active until the next event.
--------------------------------------------
	process(Clock, CLS_CNT, PIP_OFF)
	begin
		if (Clock'event and Clock = '1') then
			if (CLS_CNT = (PIP_OFF + 71)) then
				CLS_GTE <= '0';
			else
				CLS_GTE <= '1';
			end if;
		end if;
	end process;
--------------------------------------------

-- Latch the raw data (Clock ->)
--------------------------------------------
	process(Clock, CLS_CNT, PIP_OFF,
			Temp00, Temp01, Temp10, Temp11,
			Temp20, Temp21, Temp30, Temp31,
			Temp40, Temp41, Temp50, Temp51)
	begin
		if (Clock'event and Clock = '1') then
			if (CLS_CNT = (PIP_OFF + 1)) then
				PRO_A0 <= Temp00;
				PRO_A1 <= Temp10;
				PRO_A2 <= Temp20;
				PRO_A3 <= Temp30;
				PRO_A4 <= Temp40;
				PRO_A5 <= Temp50;
			elsif (CLS_CNT = (PIP_OFF + 2)) then
				S00P3 <= Temp00;
				S01P3 <= Temp01;
				S02P3 <= Temp10;
				S03P3 <= Temp11;
				S04P3 <= Temp20;
				S05P3 <= Temp21;
				S10P3 <= Temp30;
				S11P3 <= Temp31;
				S12P3 <= Temp40;
				S13P3 <= Temp41;
				S14P3 <= Temp50;
				S15P3 <= Temp51;
			elsif (CLS_CNT = (PIP_OFF + 3)) then
				S00P2 <= Temp00;
				S01P2 <= Temp01;
				S02P2 <= Temp10;
				S03P2 <= Temp11;
				S04P2 <= Temp20;
				S05P2 <= Temp21;
				S10P2 <= Temp30;
				S11P2 <= Temp31;
				S12P2 <= Temp40;
				S13P2 <= Temp41;
				S14P2 <= Temp50;
				S15P2 <= Temp51;
			elsif (CLS_CNT = (PIP_OFF + 4)) then
				S00P1 <= Temp00;
				S01P1 <= Temp01;
				S02P1 <= Temp10;
				S03P1 <= Temp11;
				S04P1 <= Temp20;
				S05P1 <= Temp21;
				S10P1 <= Temp30;
				S11P1 <= Temp31;
				S12P1 <= Temp40;
				S13P1 <= Temp41;
				S14P1 <= Temp50;
				S15P1 <= Temp51;
			elsif (CLS_CNT = (PIP_OFF + 5)) then
				S00P0 <= Temp00;
				S01P0 <= Temp01;
				S02P0 <= Temp10;
				S03P0 <= Temp11;
				S04P0 <= Temp20;
				S05P0 <= Temp21;
				S10P0 <= Temp30;
				S11P0 <= Temp31;
				S12P0 <= Temp40;
				S13P0 <= Temp41;
				S14P0 <= Temp50;
				S15P0 <= Temp51;
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Transmit the data to ACEX
--------------------------------------------
	process(CLS_CNT, PIP_OFF,
			ID1_REG, ID0_REG,
			TRG_RG1, TRG_RG0,
			PRO_A5, PRO_A4, PRO_A3,
			PRO_A2, PRO_A1, PRO_A0,
			S00P3, S00P2, S00P1, S00P0,
			S01P3, S01P2, S01P1, S01P0,
			S02P3, S02P2, S02P1, S02P0,
			S03P3, S03P2, S03P1, S03P0,
			S04P3, S04P2, S04P1, S04P0,
			S05P3, S05P2, S05P1, S05P0,
			S10P3, S10P2, S10P1, S10P0,
			S11P3, S11P2, S11P1, S11P0,
			S12P3, S12P2, S12P1, S12P0,
			S13P3, S13P2, S13P1, S13P0,
			S14P3, S14P2, S14P1, S14P0,
			S15P3, S15P2, S15P1, S15P0,
			PIP_OUT00, PIP_OUT01, PIP_OUT02,
			PIP_OUT03, PIP_OUT04, PIP_OUT05,
			PIP_OUT10, PIP_OUT11, PIP_OUT12,
			PIP_OUT13, PIP_OUT14, PIP_OUT15,
			PIP_OUT)
	begin
		if (CLS_CNT = PIP_OFF) then
			Rdata <= ID1_REG;
		elsif (CLS_CNT = (PIP_OFF + 1)) then
			Rdata <= ID0_REG;
		elsif (CLS_CNT = (PIP_OFF + 2)) then
			Rdata(7 downto 2) <= TRG_RG1;
			Rdata(1 downto 0) <= "00";
		elsif (CLS_CNT = (PIP_OFF + 3)) then
			Rdata(7 downto 6) <= "00";
			Rdata(5 downto 0) <= TRG_RG0;
		elsif (CLS_CNT = (PIP_OFF + 4)) then
			Rdata <= PRO_A5;
		elsif (CLS_CNT = (PIP_OFF + 5)) then
			Rdata <= PRO_A4;
		elsif (CLS_CNT = (PIP_OFF + 6)) then
			Rdata <= PRO_A3;
		elsif (CLS_CNT = (PIP_OFF + 7)) then
			Rdata <= PRO_A2;
		elsif (CLS_CNT = (PIP_OFF + 8)) then
			Rdata <= PRO_A1;
		elsif (CLS_CNT = (PIP_OFF + 9)) then
			Rdata <= PRO_A0;
		elsif (CLS_CNT = (PIP_OFF + 10)) then
			Rdata <= S00P3;
		elsif (CLS_CNT = (PIP_OFF + 11)) then
			Rdata <= S00P2;
		elsif (CLS_CNT = (PIP_OFF + 12)) then
			Rdata <= S00P1;
		elsif (CLS_CNT = (PIP_OFF + 13)) then
			Rdata <= S00P0;
		elsif (CLS_CNT = (PIP_OFF + 14)) then
			Rdata <= S01P3;
		elsif (CLS_CNT = (PIP_OFF + 15)) then
			Rdata <= S01P2;
		elsif (CLS_CNT = (PIP_OFF + 16)) then
			Rdata <= S01P1;
		elsif (CLS_CNT = (PIP_OFF + 17)) then
			Rdata <= S01P0;
		elsif (CLS_CNT = (PIP_OFF + 18)) then
			Rdata <= S02P3;
		elsif (CLS_CNT = (PIP_OFF + 19)) then
			Rdata <= S02P2;
		elsif (CLS_CNT = (PIP_OFF + 20)) then
			Rdata <= S02P1;
		elsif (CLS_CNT = (PIP_OFF + 21)) then
			Rdata <= S02P0;
		elsif (CLS_CNT = (PIP_OFF + 22)) then
			Rdata <= S03P3;
		elsif (CLS_CNT = (PIP_OFF + 23)) then
			Rdata <= S03P2;
		elsif (CLS_CNT = (PIP_OFF + 24)) then
			Rdata <= S03P1;
		elsif (CLS_CNT = (PIP_OFF + 25)) then
			Rdata <= S03P0;
		elsif (CLS_CNT = (PIP_OFF + 26)) then
			Rdata <= S04P3;
		elsif (CLS_CNT = (PIP_OFF + 27)) then
			Rdata <= S04P2;
		elsif (CLS_CNT = (PIP_OFF + 28)) then
			Rdata <= S04P1;
		elsif (CLS_CNT = (PIP_OFF + 29)) then
			Rdata <= S04P0;
		elsif (CLS_CNT = (PIP_OFF + 30)) then
			Rdata <= S05P3;
		elsif (CLS_CNT = (PIP_OFF + 31)) then
			Rdata <= S05P2;
		elsif (CLS_CNT = (PIP_OFF + 32)) then
			Rdata <= S05P1;
		elsif (CLS_CNT = (PIP_OFF + 33)) then
			Rdata <= S05P0;
		elsif (CLS_CNT = (PIP_OFF + 34)) then
			Rdata <= S10P3;
		elsif (CLS_CNT = (PIP_OFF + 35)) then
			Rdata <= S10P2;
		elsif (CLS_CNT = (PIP_OFF + 36)) then
			Rdata <= S10P1;
		elsif (CLS_CNT = (PIP_OFF + 37)) then
			Rdata <= S10P0;
		elsif (CLS_CNT = (PIP_OFF + 38)) then
			Rdata <= S11P3;
		elsif (CLS_CNT = (PIP_OFF + 39)) then
			Rdata <= S11P2;
		elsif (CLS_CNT = (PIP_OFF + 40)) then
			Rdata <= S11P1;
		elsif (CLS_CNT = (PIP_OFF + 41)) then
			Rdata <= S11P0;
		elsif (CLS_CNT = (PIP_OFF + 42)) then
			Rdata <= S12P3;
		elsif (CLS_CNT = (PIP_OFF + 43)) then
			Rdata <= S12P2;
		elsif (CLS_CNT = (PIP_OFF + 44)) then
			Rdata <= S12P1;
		elsif (CLS_CNT = (PIP_OFF + 45)) then
			Rdata <= S12P0;
		elsif (CLS_CNT = (PIP_OFF + 46)) then
			Rdata <= S13P3;
		elsif (CLS_CNT = (PIP_OFF + 47)) then
			Rdata <= S13P2;
		elsif (CLS_CNT = (PIP_OFF + 48)) then
			Rdata <= S13P1;
		elsif (CLS_CNT = (PIP_OFF + 49)) then
			Rdata <= S13P0;
		elsif (CLS_CNT = (PIP_OFF + 50)) then
			Rdata <= S14P3;
		elsif (CLS_CNT = (PIP_OFF + 51)) then
			Rdata <= S14P2;
		elsif (CLS_CNT = (PIP_OFF + 52)) then
			Rdata <= S14P1;
		elsif (CLS_CNT = (PIP_OFF + 53)) then
			Rdata <= S14P0;
		elsif (CLS_CNT = (PIP_OFF + 54)) then
			Rdata <= S15P3;
		elsif (CLS_CNT = (PIP_OFF + 55)) then
			Rdata <= S15P2;
		elsif (CLS_CNT = (PIP_OFF + 56)) then
			Rdata <= S15P1;
		elsif (CLS_CNT = (PIP_OFF + 57)) then
			Rdata <= S15P0;
		elsif (CLS_CNT = (PIP_OFF + 58)) then
			Rdata(7 downto 1) <= PIP_OUT00(6 downto 0);
			Rdata(0) <= '0';
		elsif (CLS_CNT = (PIP_OFF + 59)) then
			Rdata(7 downto 1) <= PIP_OUT01(6 downto 0);
			Rdata(0) <= '0';
		elsif (CLS_CNT = (PIP_OFF + 60)) then
			Rdata(7 downto 1) <= PIP_OUT02(6 downto 0);
			Rdata(0) <= '0';
		elsif (CLS_CNT = (PIP_OFF + 61)) then
			Rdata(7 downto 1) <= PIP_OUT03(6 downto 0);
			Rdata(0) <= '0';
		elsif (CLS_CNT = (PIP_OFF + 62)) then
			Rdata(7 downto 1) <= PIP_OUT04(6 downto 0);
			Rdata(0) <= '0';
		elsif (CLS_CNT = (PIP_OFF + 63)) then
			Rdata(7 downto 1) <= PIP_OUT05(6 downto 0);
			Rdata(0) <= '0';
		elsif (CLS_CNT = (PIP_OFF + 64)) then
			Rdata(7 downto 1) <= PIP_OUT10(6 downto 0);
			Rdata(0) <= '0';
		elsif (CLS_CNT = (PIP_OFF + 65)) then
			Rdata(7 downto 1) <= PIP_OUT11(6 downto 0);
			Rdata(0) <= '0';
		elsif (CLS_CNT = (PIP_OFF + 66)) then
			Rdata(7 downto 1) <= PIP_OUT12(6 downto 0);
			Rdata(0) <= '0';
		elsif (CLS_CNT = (PIP_OFF + 67)) then
			Rdata(7 downto 1) <= PIP_OUT13(6 downto 0);
			Rdata(0) <= '0';
		elsif (CLS_CNT = (PIP_OFF + 68)) then
			Rdata(7 downto 1) <= PIP_OUT14(6 downto 0);
			Rdata(0) <= '0';
		elsif (CLS_CNT = (PIP_OFF + 69)) then
			Rdata(7 downto 1) <= PIP_OUT15(6 downto 0);
			Rdata(0) <= '0';
		elsif (CLS_CNT = (PIP_OFF + 70)) then
			Rdata(7 downto 4) <= "0000";
			Rdata(3 downto 0) <= PIP_OUT;
		else
			Rdata <= (others => '0');
		end if;
	end process;
--------------------------------------------

-- Raw data strobe
--------------------------------------------
	RDS_CLR(0 downto 0) <= conv_std_logic_vector(CLS_CNT, 1);
--------------------------
	process(RDS_CLR, Clock, CLS_CNT, PIP_OFF)
	begin
		if (RDS_CLR(0) = '0') then
			STB_EVE <= '0';
		elsif(Clock'event and Clock = '1') then
			if (PIP_OFF <= CLS_CNT and CLS_CNT <= (PIP_OFF + 70)) then
				STB_EVE <= '1';
			else
				STB_EVE <= '0';
			end if;
		end if;
	end process;
--------------------------
	process(RDS_CLR, Clock, CLS_CNT, PIP_OFF)
	begin
		if (RDS_CLR(0) = '1') then
			STB_ODD <= '0';
		elsif(Clock'event and Clock = '1') then
			if (PIP_OFF <= CLS_CNT and CLS_CNT <= (PIP_OFF + 70)) then
				STB_ODD <= '1';
			else
				STB_ODD <= '0';
			end if;
		end if;
	end process;
--------------------------
	RDstb <= STB_EVE or STB_ODD;
--------------------------------------------

-- Lock the radiation monitor
-- between (0 and 4) b.c. + offset
-- (the front-end has same window)
--------------------------------------------
	process(Clock, CLS_CNT, PIP_OFF)
	begin
		if (Clock'event and Clock = '1') then
			if (PIP_OFF <= CLS_CNT and CLS_CNT <= (PIP_OFF + 4)) then
				RM_Lock <= '1';
			else
				RM_Lock <= '0';
			end if;
		end if;
	end process;
--------------------------------------------

-- Computing the number of pads fired in
-- every sector. The radiation monitor is
-- gated when the channel is masked out or
-- during the raw data transmission
--------------------------------------------
	process(Worker, Tinp00(0), Collect, RM_lock, MON_RG0(0))
	begin
		if (Worker = '1') then
			Basket0 <= 0;
		elsif (Tinp00(0)'event and Tinp00(0) = '0') then
			if (Collect = '1' and RM_Lock = '0' and MON_RG0(0) = '1') then
				Basket0 <= Basket0 + 1;
			else
				null;
			end if;
		end if;
	end process;
--------------------------
	process(Worker, Tinp01(0), Collect, RM_lock, MON_RG0(1))
	begin
		if (Worker = '1') then
			Basket1 <= 0;
		elsif (Tinp01(0)'event and Tinp01(0) = '0') then
			if (Collect = '1' and RM_Lock = '0' and MON_RG0(1) = '1') then
				Basket1 <= Basket1 + 1;
			else
				null;
			end if;
		end if;
	end process;
--------------------------
	process(Worker, Tinp20(0), Collect, RM_lock, MON_RG0(2))
	begin
		if (Worker = '1') then
			Basket2 <= 0;
		elsif (Tinp20(0)'event and Tinp20(0) = '0') then
			if (Collect = '1' and RM_Lock = '0' and MON_RG0(2) = '1') then
				Basket2 <= Basket2 + 1;
			else
				null;
			end if;
		end if;
	end process;
--------------------------
	process(Worker, Tinp21(0), Collect, RM_lock, MON_RG0(3))
	begin
		if (Worker = '1') then
			Basket3 <= 0;
		elsif (Tinp21(0)'event and Tinp21(0) = '0') then
			if (Collect = '1' and RM_Lock = '0' and MON_RG0(3) = '1') then
				Basket3 <= Basket3 + 1;
			else
				null;
			end if;
		end if;
	end process;
--------------------------
	process(Worker, Tinp40(0), Collect, RM_lock, MON_RG0(4))
	begin
		if (Worker = '1') then
			Basket4 <= 0;
		elsif (Tinp40(0)'event and Tinp40(0) = '0') then
			if (Collect = '1' and RM_Lock = '0' and MON_RG0(4) = '1') then
				Basket4 <= Basket4 + 1;
			else
				null;
			end if;
		end if;
	end process;
--------------------------
	process(Worker, Tinp41(0), Collect, RM_lock, MON_RG0(5))
	begin
		if (Worker = '1') then
			Basket5 <= 0;
		elsif (Tinp41(0)'event and Tinp41(0) = '0') then
			if (Collect = '1' and RM_Lock = '0' and MON_RG0(5) = '1') then
				Basket5 <= Basket5 + 1;
			else
				null;
			end if;
		end if;
	end process;
--------------------------
--------------------------
	process(Worker, Tinp10(0), Collect, RM_lock, MON_RG1(0))
	begin
		if (Worker = '1') then
			Basket6 <= 0;
		elsif (Tinp10(0)'event and Tinp10(0) = '0') then
			if (Collect = '1' and RM_Lock = '0' and MON_RG1(0) = '1') then
				Basket6 <= Basket6 + 1;
			else
				null;
			end if;
		end if;
	end process;
--------------------------
	process(Worker, Tinp11(0), Collect, RM_lock, MON_RG1(1))
	begin
		if (Worker = '1') then
			Basket7 <= 0;
		elsif (Tinp11(0)'event and Tinp11(0) = '0') then
			if (Collect = '1' and RM_Lock = '0' and MON_RG1(1) = '1') then
				Basket7 <= Basket7 + 1;
			else
				null;
			end if;
		end if;
	end process;
--------------------------
	process(Worker, Tinp30(0), Collect, RM_lock, MON_RG1(2))
	begin
		if (Worker = '1') then
			Basket8 <= 0;
		elsif (Tinp30(0)'event and Tinp30(0) = '0') then
			if (Collect = '1' and RM_Lock = '0' and MON_RG1(2) = '1') then
				Basket8 <= Basket8 + 1;
			else
				null;
			end if;
		end if;
	end process;
--------------------------
	process(Worker, Tinp31(0), Collect, RM_lock, MON_RG1(3))
	begin
		if (Worker = '1') then
			Basket9 <= 0;
		elsif (Tinp31(0)'event and Tinp31(0) = '0') then
			if (Collect = '1' and RM_Lock = '0' and MON_RG1(3) = '1') then
				Basket9 <= Basket9 + 1;
			else
				null;
			end if;
		end if;
	end process;
--------------------------
	process(Worker, Tinp50(0), Collect, RM_lock, MON_RG1(4))
	begin
		if (Worker = '1') then
			Basket10 <= 0;
		elsif (Tinp50(0)'event and Tinp50(0) = '0') then
			if (Collect = '1' and RM_Lock = '0' and MON_RG1(4) = '1') then
				Basket10 <= Basket10 + 1;
			else
				null;
			end if;
		end if;
	end process;
--------------------------
	process(Worker, Tinp51(0), Collect, RM_lock, MON_RG1(5))
	begin
		if (Worker = '1') then
			Basket11 <= 0;
		elsif (Tinp51(0)'event and Tinp51(0) = '0') then
			if (Collect = '1' and RM_Lock = '0' and MON_RG1(5) = '1') then
				Basket11 <= Basket11 + 1;
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- 0.8 sec interval counter (Clock <-)
--------------------------------------------
	process(Clock)
	begin
		if (Clock'event and Clock = '0') then
			TIM_CNT <= TIM_CNT + 1;
		end if;
	end process;
--------------------------------------------

-- Enable data collection (Clock ->)
--------------------------------------------
	process(Clock, TIM_CNT)
	begin
		if (Clock'event and Clock = '1') then
			case TIM_CNT is
				when 0 =>
					Collect <= '0';
				when 7 =>
					Collect <= '1';
				when others =>
					null;
			end case;
		end if;
	end process;
--------------------------------------------

-- Keep collected data (Clock ->)
--------------------------------------------
	process(Clock, TIM_CNT)
	begin
		if (Clock'event and Clock = '1') then
			case TIM_CNT is
				when 2 =>
					Rescue <= '1';
				when 3 =>
					Rescue <= '0';
				when others =>
					null;
			end case;
		end if;
	end process;
--------------------------------------------

-- Clear buffers (Clock ->)
--------------------------------------------
	process(Clock, TIM_CNT)
	begin
		if (Clock'event and Clock = '1') then
			case TIM_CNT is
				when 5 =>
					Worker <= '1';
				when 6 =>
					Worker <= '0';
				when others =>
					null;
			end case;
		end if;
	end process;
--------------------------------------------

-- Latching the frequency value (Clock <-)
--------------------------------------------
	process(Clock, Rescue, ST_RATE,
			Basket0, Basket1, Basket2, Basket3, Basket4, Basket5,
			Basket6, Basket7, Basket8, Basket9, Basket10, Basket11)
	begin
		if (Clock'event and Clock = '0') then
			if (Rescue = '1' and ST_RATE = '0') then				
				Firewood0 <= Basket0;
				Firewood1 <= Basket1;
				Firewood2 <= Basket2;
				Firewood3 <= Basket3;
				Firewood4 <= Basket4;
				Firewood5 <= Basket5;
				Firewood6 <= Basket6;
				Firewood7 <= Basket7;
				Firewood8 <= Basket8;
				Firewood9 <= Basket9;
				Firewood10 <= Basket10;
				Firewood11 <= Basket11;
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Maximum event rate
--------------------------------------------
	process(Firewood0, Firewood1, Firewood2, Firewood3, Firewood4, Firewood5,
			Firewood6, Firewood7, Firewood8, Firewood9, Firewood10, Firewood11)
		variable TEMP: natural range 0 to 8388607;
	begin
		TEMP:= 0;
			if (TEMP <= Firewood0) then
				TEMP:= Firewood0;
			end if;
			if (TEMP <= Firewood1) then
				TEMP:= Firewood1;
			end if;
			if (TEMP <= Firewood2) then
				TEMP:= Firewood2;
			end if;
			if (TEMP <= Firewood3) then
				TEMP:= Firewood3;
			end if;
			if (TEMP <= Firewood4) then
				TEMP:= Firewood4;
			end if;
			if (TEMP <= Firewood5) then
				TEMP:= Firewood5;
			end if;
			if (TEMP <= Firewood6) then
				TEMP:= Firewood6;
			end if;
			if (TEMP <= Firewood7) then
				TEMP:= Firewood7;
			end if;
			if (TEMP <= Firewood8) then
				TEMP:= Firewood8;
			end if;
			if (TEMP <= Firewood9) then
				TEMP:= Firewood9;
			end if;
			if (TEMP <= Firewood10) then
				TEMP:= Firewood10;
			end if;
			if (TEMP <= Firewood11) then
				TEMP:= Firewood11;
			end if;
		Frequency <= TEMP;
	end process;
--------------------------------------------

-- Computing the pedestal frequency
-- (1 kHz per register unit);
--------------------------------------------
	Pedestal <= 1000 * BIT8_to_NUM(PED_REG);
--------------------------------------------

-- Pedestal subtraction. The Oven must be a
-- positive integer to prevent division by zero.
--------------------------------------------
	process(Frequency, Pedestal)
	begin
		if (Frequency <= Pedestal) then
			Oven <= 1;	-- Must not be zero;
		else
			Oven <= Frequency - Pedestal;
		end if;
	end process;
--------------------------------------------

-- Convert data format
--------------------------------------------
	DIV_NUM <= "11111111111111111111111";
	DIV_DEN <= conv_std_logic_vector(Oven, 23);
--------------------------------------------

-- Computing the number of loops
--------------------------------------------
	lpm_divide_component : lpm_divide
	generic map (
			lpm_widthn => 23,
			lpm_widthd => 23,
			lpm_type => "LPM_DIVIDE",
			lpm_nrepresentation => "UNSIGNED",
			lpm_hint => "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE",
			lpm_drepresentation => "UNSIGNED"
			)
	port map (
			denom => DIV_DEN,
			numer => DIV_NUM,
			quotient => DIV_RES,
			remain => DIV_DUM
			);
--------------------------------------------

-- Keep the result of division
--------------------------------------------
	process(Clock, Worker, Frequency, Pedestal, DIV_RES)
	begin
		if (Clock'event and Clock = '0') then
			if (Worker = '1') then
				if (Frequency <= Pedestal) then
					Result <= 1 + BIT23_to_NUM(DIV_RES);
				else
					Result <= BIT23_to_NUM(DIV_RES);
				end if;
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Frequency modulation
--------------------------------------------
	process(Clock, RAD_MON, Worker)
	begin
		if (Clock'event and Clock = '0') then
			if (RAD_MON = '1' or Worker = '1') then
				FRQ_CNT <= 0;
				RAD_RES <= '1';
			else
				FRQ_CNT <= FRQ_CNT + 1;
				RAD_RES <= '0';
			end if;
		end if;
	end process;
--------------------------------------------

-- Radiation monitor
--------------------------------------------
	process(Clock, FRQ_CNT, Result)
	begin
		if (Clock'event and Clock = '1') then
			if (FRQ_CNT = Result) then
				RAD_MON <= '1';
			else
				RAD_MON <= '0';
			end if;
		end if;
	end process;
--------------------------
	process(RAD_RES, RAD_MON)
	begin
		if (RAD_RES = '1') then
			RAD_OUT <= '0';
		elsif (RAD_MON'event and RAD_MON = '1') then
			RAD_OUT <= '1';
		end if;
	end process;
--------------------------------------------

-- keep the radiation level (Clock <-)
--------------------------------------------
	process(Clock, Worker, IAM_BSY, DIV_DEN)
	begin
		if (Clock'event and Clock = '0') then
			if (Worker = '1' and IAM_BSY = '0') then
				RAD_LEV(7 downto 0) <= DIV_DEN(21 downto 14);
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Gate for the indicator counter (Clock <-)
--------------------------------------------
	process(Clock, EVT_OCU, EVT_CNT)
	begin
		if (Clock'event and Clock = '0') then
			if (EVT_OCU = '1') then
				EVT_GTE <= '1';
			elsif (EVT_CNT = 1048575) then
				EVT_GTE <= '0';
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Indicator counter
--------------------------------------------
	process(Clock, EVT_GTE)
	begin
		if (Clock'event and Clock = '1') then
			if (EVT_GTE = '1') then
				EVT_CNT <= EVT_CNT + 1;
			else
				EVT_CNT <= 0;
			end if;
		end if;
	end process;
--------------------------------------------

-- Lighting the "Event" indicator
--------------------------------------------
	process(EVT_CNT)
	begin
		case EVT_CNT is
			when 1 to 131071 =>
				EVT_fire <= '1';
			when others =>
				EVT_fire <= '0';
		end case;
	end process;
--------------------------------------------

-- Gate for the indicator counter (Clock <-)
--------------------------------------------
	process(Clock, VTO_OCU,VTO_CNT)
	begin
		if (Clock'event and Clock = '0') then
			if (VTO_OCU = '1') then
				VTO_GTE <= '1';
			elsif (VTO_CNT = 1048575) then
				VTO_GTE <= '0';
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Reference counter
--------------------------------------------
	process(Clock, VTO_GTE)
	begin
		if (Clock'event and Clock = '1') then
			if (VTO_GTE = '1') then
				VTO_CNT <= VTO_CNT + 1;
			else
				VTO_CNT <= 0;
			end if;
		end if;
	end process;
--------------------------------------------

-- Lighting the "Veto" indicator
--------------------------------------------
	process(VTO_CNT)
	begin
		case VTO_CNT is
			when 1 to 131071 =>
				VTO_fire <= '1';
			when others =>
				VTO_fire <= '0';
		end case;
	end process;
--------------------------------------------

-- Output data (Clock ->)
--------------------------------------------
	Mout(0) <= TSP_INN;
	Mout(1) <= TSP_OUT;
	Mout(2) <= LNG_TRK;
	Mout(3) <= BST_VTO;
	Mout(4) <= '0';
	Mout(5) <= '0';
	Mout(6) <= '0';
	Mout(7) <= RAD_OUT;
--------------------------------------------

end;