-- VME interface program for the standard (A24)
-- supervisory and non-privileged data access.

-- !!! Attention !!! The SiDAQ reads B16 words
-- and moves them one by one to the to event
-- builder, whose memory is segmented onto B32
-- (long) words. The early B16 word is placed
-- into bits 15...00 of this memory and the late
-- one - into bits 31...16. To keep the defined
-- SITR bank structure (which is well established
-- and seems logical/natural and convenient for
-- the offline) i swap the order of every two
-- VME addresses.

-- The full address = Base Address + Extension

-- Read functions:
--------------------------------------------

-- System info:
--------------------------
-- Extension = 0002 - ID word;
-- Extension = 0000 - System status;
-- Extension = 0006 - Enable trigger in sectors 15..00;
--------------------------

-- PRO/A load status:
---------------------------
-- Extension = 0004 - PRO/A in sectors 15, 14, 13, 12;
-- Extension = 000A - PRO/A in sectors 11, 10, 05, 04;
-- Extension = 0008 - PRO/A in sectors 03, 02, 01, 00;

-- Raw data:
---------------------------
-- Extension = 000E - Sector_00, plane 3 and 2;
-- Extension = 000C - Sector_00, plane 1 and 0;

-- Extension = 0012 - Sector_01, plane 3 and 2;
-- Extension = 0010 - Sector_01, plane 1 and 0;

-- Extension = 0016 - Sector_02, plane 3 and 2;
-- Extension = 0014 - Sector_02, plane 1 and 0;

-- Extension = 001A - Sector_03, plane 3 and 2;
-- Extension = 0018 - Sector_03, plane 1 and 0;

-- Extension = 001E - Sector_04, plane 3 and 2;
-- Extension = 001C - Sector_04, plane 1 and 0;

-- Extension = 0022 - Sector_05, plane 3 and 2;
-- Extension = 0020 - Sector_05, plane 1 and 0;

-- Extension = 0026 - Sector_10, plane 3 and 2;
-- Extension = 0024 - Sector_10, plane 1 and 0;

-- Extension = 002A - Sector_11, plane 3 and 2;
-- Extension = 0028 - Sector_11, plane 1 and 0;

-- Extension = 002E - Sector_12, plane 3 and 2;
-- Extension = 002C - Sector_12, plane 1 and 0;

-- Extension = 0032 - Sector_13, plane 3 and 2;
-- Extension = 0030 - Sector_13, plane 1 and 0;

-- Extension = 0036 - Sector_14, plane 3 and 2;
-- Extension = 0034 - Sector_14, plane 1 and 0;

-- Extension = 003A - Sector_15, plane 3 and 2;
-- Extension = 0038 - Sector_15, plane 1 and 0;

-- Extension = 003E - Track topology in Sectors 00 & 01;
-- Extension = 003C - Track topology in Sectors 02 & 03;

-- Extension = 0042 - Track topology in Sectors 04 & 05;
-- Extension = 0040 - Track topology in Sectors 10 & 11;

-- Extension = 0046 - Track topology in Sectors 12 & 13;
-- Extension = 0044 - Track topology in Sectors 14 & 15;

-- Extension = 004A - empty space;
-- Extension = 0048 - L1 trigger elements;
--------------------------------------------

-- Data format:
--------------------------------------------

-- ID word
--------------------------
-- Data = 000D DDDD MMMM YYYY (binary);
-- DDDDD - day   (0...31);
--  MMMM - month (0...12);
--  YYYY - year  (0...15) keeping in mind + 2000;

-- Component status
--------------------------
-- Data = 000T 00RR 00FF FFFF (binary);
--    T - supply of this Trigger card;
--  R_9 - supply of the Repater card 2;
--	R_8 - supply of the Repater card 1;
--	F_i - Front-end board_i readiness;

-- Trigger enable
--------------------------
-- Data = EEEE EE00 00EE EEEE (binary);
--  E_i - enable trigger in sector_i;

-- PRO/A settings
--------------------------
-- Data = BBBB BBBB BBBB BBBB (binary);

-- Ext:     0004   000A    0008
--------------------------------
-- Bit_15 - S15P3 / S11P3 / S03P3;
-- Bit_14 - S15P2 / S11P2 / S03P2;
-- Bit_13 - S15P1 / S11P1 / S03P1;
-- Bit_12 - S15P0 / S11P0 / S03P0;

-- Bit_11 - S14P3 / S10P3 / S02P3;
-- Bit_10 - S14P2 / S10P2 / S02P2;
-- Bit_9  - S14P1 / S10P1 / S02P1;
-- Bit_8  - S14P0 / S10P0 / S02P0;

-- Bit_7  - S13P3 / S05P3 / S01P3;
-- Bit_6  - S13P2 / S05P2 / S01P2;
-- Bit_5  - S13P1 / S05P1 / S01P1;
-- Bit_4  - S13P0 / S05P0 / S01P0;

-- Bit_3  - S12P3 / S04P3 / S00P3;
-- Bit_2  - S12P2 / S04P2 / S00P2;
-- Bit_1  - S12P1 / S04P1 / S00P1;
-- Bit_0  - S12P0 / S04P0 / S00P0;
--------------------------------------------

-- Raw data
--------------------------
-- Each byte corresponds to one silicon wafer,
-- the bits determine its radial subdivision.
--------------------------------------------

-- Topological data
--------------------------
-- Each byte corresponds to one sector, whose
-- number is equal to the azimuthal angle Theta.
-- Data = TV AAAAA X (binary)
--     T - Track trigger (mask found);
--     V - Multiplicity veto (N_hits > 6);
-- AAAAA - Theta of the track when T = '1',
--          otherwise the hit multiplicity;
--     X - has no meaning;
--------------------------------------------

-- L1 trigger elements
--------------------------
--	Bit_7 - no meaning;
--	Bit_5..Bit_4 = '0';
--	Bit_3 = BST_VTO;
--	Bit_2 = BC_2_BC;
--	Bit_1 = TSP_OUT;
--	Bit_0 = TSP_INN;
--------------------------------------------

-- Copyright I.Tsurin, University of Antwerpen,
-- on behalf of DESY.
--------------------------------------------
  
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;

--	OK. Here the entity starts...
--------------------------------------------
entity VMEinter is

port(
	SysCLK: in std_logic;

	SEL_ADD: in std_logic_vector(7 downto 0);

	RXD: in std_logic;
	TXD: in std_logic;

	Rdata: in std_logic_vector(7 downto 0);
	RDstb: in std_logic;

	Spare: out std_logic_vector(7 downto 0);

	nSetFER: in std_logic;
	L2KPul:  in std_logic;

	FERout: out std_logic;

	VME_ADD: in std_logic_vector(23 downto 1);

	nLWord:  in std_logic;
	nWrite:  in std_logic;

	VME_DAT: inout std_logic_vector(15 downto 0);

	DTACK: out std_logic;
	BError:  out std_logic;

	VME_AM: in std_logic_vector(5 downto 0);

	nAS:   in std_logic;
	nIACK: in std_logic;
	nSRes: in std_logic;

	Direct: out std_logic;
	nDatEN: out std_logic;
	nDS0:   in std_logic;
	nDS1:   in std_logic;

	Quartz: in std_logic;

	LAM0: in std_logic_vector(2 downto 0);
	LAM1: in std_logic_vector(2 downto 0);

	FERin: in std_logic_vector(1 downto 0);

	P18_Ok: in std_logic;
	P25_Ok: in std_logic;
	P33_Ok: in std_logic;
	N50_Ok: in std_logic;
	P50_Ok: in std_logic
	);

	attribute pinnum: string;

	attribute pinnum of SysCLK: signal is "7";

	attribute pinnum of SEL_ADD: signal is "10,9,8,144,14,13,12,11";

	attribute pinnum of RXD: signal is "17";
	attribute pinnum of TXD: signal is "18";

	attribute pinnum of Rdata: signal is "20,21,22,23,26,27,28,29";
	attribute pinnum of RDstb: signal is "19";

	attribute pinnum of Spare: signal is "30,31,32,33,36,37,38,39";

	attribute pinnum of nSetFER: signal is "41";
	attribute pinnum of L2KPul: signal is "42";

	attribute pinnum of FERout: signal is "43";

	attribute pinnum of VME_ADD: signal is "82,81,80,79,78,73,72,70,69,68,67,65,64,63,62,60,59,51,49,48,47,46,44";

	attribute pinnum of nLWord: signal is "54";
	attribute pinnum of nWrite: signal is "56";

	attribute pinnum of VME_DAT: signal is "83,86,87,88,89,90,91,92,95,96,97,98,99,100,101,102";

	attribute pinnum of DTACK: signal is "119";
	attribute pinnum of BError: signal is "120";

	attribute pinnum of VME_AM: signal is "114,113,112,111,110,109";

	attribute pinnum of nAS: signal is "116";
	attribute pinnum of nIACK: signal is "117";
	attribute pinnum of nSRes: signal is "118";

	attribute pinnum of Direct: signal is "121";
	attribute pinnum of nDatEN: signal is "122";
	attribute pinnum of nDS1: signal is "126";
	attribute pinnum of nDS0: signal is "124";

	attribute pinnum of Quartz: signal is "125";

	attribute pinnum of LAM0: signal is "131,130,128";
	attribute pinnum of LAM1: signal is "135,133,132";

	attribute pinnum of FERin: signal is "137,136";

	attribute pinnum of P18_Ok: signal is "138";
	attribute pinnum of P25_Ok: signal is "140";
	attribute pinnum of P33_Ok: signal is "141";
	attribute pinnum of N50_Ok: signal is "142";
	attribute pinnum of P50_Ok: signal is "143";

end;

architecture behavior of VMEinter is

-- Initialization
--------------------------------------------
	signal DUM_RES: std_logic;
	signal RES_PUL: std_logic;
	signal INI_CNT: natural range 0 to 524287;
--------------------------------------------

-- VME variables
--------------------------------------------
	signal nAS_CNT: natural range 0 to 3;
	signal nDS_CNT: natural range 0 to 7;

	signal nAS_BLK: std_logic;
	signal nDS_BLK: std_logic;

	signal BAS_SEL: std_logic_vector(7 downto 0);
	signal BAS_ADR: std_logic;

	signal VMD_INP: std_logic_vector(15 downto 0);
	signal VMD_OUT: std_logic_vector(15 downto 0);

	signal VMA_INP: std_logic_vector(23 downto 1);
	alias  REG_ADR: std_logic_vector(6 downto 1) is VMA_INP(6 downto 1);

	signal VMM_INP: std_logic_vector(5 downto 0);
	signal NLN_WRD: std_logic;

	signal DAT_ACC: std_logic;
	signal RDY_EXE: std_logic;

	signal ACTION:  std_logic;
	signal MOD_ACT: std_logic;
	signal DAT_ACK: std_logic;
--------------------------------------------

-- Raw data pipeline
--------------------------------------------
	signal ID0_REG: std_logic_vector(7 downto 0);
	signal ID1_REG: std_logic_vector(7 downto 0);

	signal TR0_REG: std_logic_vector(7 downto 0);
	signal TR1_REG: std_logic_vector(7 downto 0);

	signal PRO_A0: std_logic_vector(7 downto 0);
	signal PRO_A1: std_logic_vector(7 downto 0);
	signal PRO_A2: std_logic_vector(7 downto 0);

	signal PRO_A3: std_logic_vector(7 downto 0);
	signal PRO_A4: std_logic_vector(7 downto 0);
	signal PRO_A5: std_logic_vector(7 downto 0);

	signal S00P0: std_logic_vector(7 downto 0);
	signal S00P1: std_logic_vector(7 downto 0);
	signal S00P2: std_logic_vector(7 downto 0);
	signal S00P3: std_logic_vector(7 downto 0);

	signal S01P0: std_logic_vector(7 downto 0);
	signal S01P1: std_logic_vector(7 downto 0);
	signal S01P2: std_logic_vector(7 downto 0);
	signal S01P3: std_logic_vector(7 downto 0);

	signal S02P0: std_logic_vector(7 downto 0);
	signal S02P1: std_logic_vector(7 downto 0);
	signal S02P2: std_logic_vector(7 downto 0);
	signal S02P3: std_logic_vector(7 downto 0);

	signal S03P0: std_logic_vector(7 downto 0);
	signal S03P1: std_logic_vector(7 downto 0);
	signal S03P2: std_logic_vector(7 downto 0);
	signal S03P3: std_logic_vector(7 downto 0);

	signal S04P0: std_logic_vector(7 downto 0);
	signal S04P1: std_logic_vector(7 downto 0);
	signal S04P2: std_logic_vector(7 downto 0);
	signal S04P3: std_logic_vector(7 downto 0);

	signal S05P0: std_logic_vector(7 downto 0);
	signal S05P1: std_logic_vector(7 downto 0);
	signal S05P2: std_logic_vector(7 downto 0);
	signal S05P3: std_logic_vector(7 downto 0);

	signal S10P0: std_logic_vector(7 downto 0);
	signal S10P1: std_logic_vector(7 downto 0);
	signal S10P2: std_logic_vector(7 downto 0);
	signal S10P3: std_logic_vector(7 downto 0);

	signal S11P0: std_logic_vector(7 downto 0);
	signal S11P1: std_logic_vector(7 downto 0);
	signal S11P2: std_logic_vector(7 downto 0);
	signal S11P3: std_logic_vector(7 downto 0);

	signal S12P0: std_logic_vector(7 downto 0);
	signal S12P1: std_logic_vector(7 downto 0);
	signal S12P2: std_logic_vector(7 downto 0);
	signal S12P3: std_logic_vector(7 downto 0);

	signal S13P0: std_logic_vector(7 downto 0);
	signal S13P1: std_logic_vector(7 downto 0);
	signal S13P2: std_logic_vector(7 downto 0);
	signal S13P3: std_logic_vector(7 downto 0);

	signal S14P0: std_logic_vector(7 downto 0);
	signal S14P1: std_logic_vector(7 downto 0);
	signal S14P2: std_logic_vector(7 downto 0);
	signal S14P3: std_logic_vector(7 downto 0);

	signal S15P0: std_logic_vector(7 downto 0);
	signal S15P1: std_logic_vector(7 downto 0);
	signal S15P2: std_logic_vector(7 downto 0);
	signal S15P3: std_logic_vector(7 downto 0);

	signal S00TD: std_logic_vector(7 downto 0);
	signal S01TD: std_logic_vector(7 downto 0);
	signal S02TD: std_logic_vector(7 downto 0);
	signal S03TD: std_logic_vector(7 downto 0);
	signal S04TD: std_logic_vector(7 downto 0);
	signal S05TD: std_logic_vector(7 downto 0);
	signal S10TD: std_logic_vector(7 downto 0);
	signal S11TD: std_logic_vector(7 downto 0);
	signal S12TD: std_logic_vector(7 downto 0);
	signal S13TD: std_logic_vector(7 downto 0);
	signal S14TD: std_logic_vector(7 downto 0);
	signal S15TD: std_logic_vector(7 downto 0);

	signal L1TES: std_logic_vector(7 downto 0);
--------------------------

-- Buffers
--------------------------
	signal ID0_RGB: std_logic_vector(7 downto 0);

	signal TR0_RGB: std_logic_vector(7 downto 0);
	signal TR1_RGB: std_logic_vector(7 downto 0);

	signal PRO_B0: std_logic_vector(7 downto 0);
	signal PRO_B1: std_logic_vector(7 downto 0);
	signal PRO_B2: std_logic_vector(7 downto 0);

	signal PRO_B3: std_logic_vector(7 downto 0);
	signal PRO_B4: std_logic_vector(7 downto 0);
	signal PRO_B5: std_logic_vector(7 downto 0);

	signal B00P0: std_logic_vector(7 downto 0);
	signal B00P1: std_logic_vector(7 downto 0);
	signal B00P2: std_logic_vector(7 downto 0);
	signal B00P3: std_logic_vector(7 downto 0);

	signal B01P0: std_logic_vector(7 downto 0);
	signal B01P1: std_logic_vector(7 downto 0);
	signal B01P2: std_logic_vector(7 downto 0);
	signal B01P3: std_logic_vector(7 downto 0);

	signal B02P0: std_logic_vector(7 downto 0);
	signal B02P1: std_logic_vector(7 downto 0);
	signal B02P2: std_logic_vector(7 downto 0);
	signal B02P3: std_logic_vector(7 downto 0);

	signal B03P0: std_logic_vector(7 downto 0);
	signal B03P1: std_logic_vector(7 downto 0);
	signal B03P2: std_logic_vector(7 downto 0);
	signal B03P3: std_logic_vector(7 downto 0);

	signal B04P0: std_logic_vector(7 downto 0);
	signal B04P1: std_logic_vector(7 downto 0);
	signal B04P2: std_logic_vector(7 downto 0);
	signal B04P3: std_logic_vector(7 downto 0);

	signal B05P0: std_logic_vector(7 downto 0);
	signal B05P1: std_logic_vector(7 downto 0);
	signal B05P2: std_logic_vector(7 downto 0);
	signal B05P3: std_logic_vector(7 downto 0);

	signal B10P0: std_logic_vector(7 downto 0);
	signal B10P1: std_logic_vector(7 downto 0);
	signal B10P2: std_logic_vector(7 downto 0);
	signal B10P3: std_logic_vector(7 downto 0);

	signal B11P0: std_logic_vector(7 downto 0);
	signal B11P1: std_logic_vector(7 downto 0);
	signal B11P2: std_logic_vector(7 downto 0);
	signal B11P3: std_logic_vector(7 downto 0);

	signal B12P0: std_logic_vector(7 downto 0);
	signal B12P1: std_logic_vector(7 downto 0);
	signal B12P2: std_logic_vector(7 downto 0);
	signal B12P3: std_logic_vector(7 downto 0);

	signal B13P0: std_logic_vector(7 downto 0);
	signal B13P1: std_logic_vector(7 downto 0);
	signal B13P2: std_logic_vector(7 downto 0);
	signal B13P3: std_logic_vector(7 downto 0);

	signal B14P0: std_logic_vector(7 downto 0);
	signal B14P1: std_logic_vector(7 downto 0);
	signal B14P2: std_logic_vector(7 downto 0);
	signal B14P3: std_logic_vector(7 downto 0);

	signal B15P0: std_logic_vector(7 downto 0);
	signal B15P1: std_logic_vector(7 downto 0);
	signal B15P2: std_logic_vector(7 downto 0);
	signal B15P3: std_logic_vector(7 downto 0);

	signal S00TB: std_logic_vector(7 downto 0);
	signal S01TB: std_logic_vector(7 downto 0);
	signal S02TB: std_logic_vector(7 downto 0);
	signal S03TB: std_logic_vector(7 downto 0);
	signal S04TB: std_logic_vector(7 downto 0);
	signal S05TB: std_logic_vector(7 downto 0);
	signal S10TB: std_logic_vector(7 downto 0);
	signal S11TB: std_logic_vector(7 downto 0);
	signal S12TB: std_logic_vector(7 downto 0);
	signal S13TB: std_logic_vector(7 downto 0);
	signal S14TB: std_logic_vector(7 downto 0);
	signal S15TB: std_logic_vector(7 downto 0);

	signal L1TER: std_logic_vector(7 downto 0);
--------------------------------------------

-- Indicators
--------------------------------------------
	signal PWR_REG: std_logic_vector(4 downto 0);
	signal WDG_CLR: std_logic;

	signal Power:   std_logic;
	signal Status:  std_logic;

	signal ST0_REG: std_logic_vector(5 downto 0);
	signal ST1_REG: std_logic_vector(1 downto 0);
	
	signal STM_REG: std_logic_vector(5 downto 0);
--------------------------------------------

begin

-- Permanent statements
--------------------------------------------
	DUM_RES <= '0';
-------------------------
	BAS_SEL(7) <= not SEL_ADD(7);
	BAS_SEL(6) <= not SEL_ADD(6);
	BAS_SEL(5) <= not SEL_ADD(5);
	BAS_SEL(4) <= not SEL_ADD(4);
	BAS_SEL(3) <= not SEL_ADD(3);
	BAS_SEL(2) <= not SEL_ADD(2);
	BAS_SEL(1) <= not SEL_ADD(1);
	BAS_SEL(0) <= not SEL_ADD(0);
-------------------------
	Spare <= (others => '1');
--------------------------------------------

-- Start-up counter
--------------------------------------------
	process(DUM_RES, SysCLK, RES_PUL)
	begin
		if (DUM_RES = '1') then
			INI_CNT <= 0;
		elsif (SysCLK'event and SysCLK = '1') then
			if (RES_PUL = '1') then
				INI_CNT <= INI_CNT + 1;
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Start-up reset pulse (SysCLK <-)
--------------------------------------------
	process(DUM_RES, SysCLK, INI_CNT)
	begin
		if (DUM_RES = '1') then
			RES_PUL <= '1';
		elsif (SysCLK'event and SysCLK = '0') then
			if (INI_CNT = 524287) then
				RES_PUL <= '0';
			else
				RES_PUL <= '1';
			end if;
		end if;
	end process;
--------------------------------------------

-- Bidirectional port for the VME interface:
--------------------------------------------
	process(nWrite, VMD_OUT)
	begin
		if (nWrite = '0') then
			VME_DAT <= (others => 'Z');
		else
			VME_DAT <= VMD_OUT;
		end if;
	end process;
--------------------------
	VMD_INP <= VME_DAT;
--------------------------------------------

-- Address strobe timer
--------------------------------------------
	process(RES_PUL, nAS, SysCLK, nAS_BLK)
	begin
		if (RES_PUL = '1' or nAS = '1') then
			nAS_CNT <= 0;
		elsif (SysCLK'event and SysCLK = '1') then
			if (nAS_BLK = '0') then
				nAS_CNT <= nAS_CNT + 1;
			else
				null;
			end if;
		end if;
	end process;
--------------------------
	process(nAS, SysCLK, nAS_CNT)
	begin
		if (nAS = '1') then
			nAS_BLK <= '0';
		elsif (SysCLK'event and SysCLK = '0') then
			if (nAS_CNT = 3) then
				nAS_BLK <= '1';
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Latching the input address and modifier
--------------------------------------------
	process(nAS, SysCLK, nAS_CNT, nLWord, VME_ADD, VME_AM)
	begin
		if (nAS = '1') then
				NLN_WRD <= '1';			
				VMA_INP <= (others => '0');
				VMM_INP <= (others => '0');
		elsif (SysCLK'event and SysCLK = '0') then
			if (nAS_CNT = 2) then
				NLN_WRD <= nLWord;
				VMA_INP <= VME_ADD;
				VMM_INP <= VME_AM;
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Check for the base address matching 
--------------------------------------------
	process(VMA_INP, BAS_SEL)
	begin
		if (VMA_INP(23 downto 16) = BAS_SEL(7 downto 0)) then
			BAS_ADR <= '1';
		else
			BAS_ADR <= '0';
		end if;
	end process;
--------------------------------------------

-- Data access regime (SysCLK <-)
--------------------------------------------
	process(VMM_INP)
	begin
		case VMM_INP is
			when "111101" =>
				DAT_ACC <= '1';
			when "111001" =>
				DAT_ACC <= '1';
			when others =>
				DAT_ACC <= '0';
		end case;
	end process;
--------------------------------------------

-- Operation decoding (SysCLK <-)
--------------------------------------------
	process(VMA_INP)
	begin
		if ("000000000000000" <= VMA_INP(15 downto 1) and
		        VMA_INP(15 downto 1) <= "000000000100101") then
			RDY_EXE <= '1';
		else
			RDY_EXE <= '0';
		end if;
	end process;
--------------------------------------------

-- VME module activation (SysCLK <-)
--------------------------------------------
	ACTION <= NLN_WRD and RDY_EXE and DAT_ACC;
	MOD_ACT <= BAS_ADR and ACTION and nIACK;
--------------------------------------------

-- Enable data operation (SysCLK <-)
--------------------------------------------
	process(MOD_ACT, nDS0)
	begin
		if (MOD_ACT = '1' and nDS0 = '0') then
			nDatEN <= '0';
		else
			nDatEN <= '1';
		end if;
	end process;
--------------------------------------------

-- VME data flow direction
--------------------------------------------
	process(nWrite)
	begin
		if (nWrite = '0') then
			Direct <= '0';
		else
			Direct <= '1';
		end if;
	end process;
--------------------------------------------

-- Data strobe timer
--------------------------------------------
	process(RDstb, nDS0, SysCLK, nDS_BLK)
	begin
		if (RDstb = '1' or nDS0 = '1') then
			nDS_CNT <= 0;
		elsif (SysCLK'event and SysCLK = '0') then
			if (nDS_BLK = '0') then
				nDS_CNT <= nDS_CNT + 1;
			else
				null;
			end if;
		end if;
	end process;
--------------------------
	process(nDS0, SysCLK, nDS_CNT)
	begin
		if (nDS0 = '1') then
			nDS_BLK <= '0';
		elsif (SysCLK'event and SysCLK = '1') then
			if (nDS_CNT = 5) then
				nDS_BLK <= '1';
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Forming the output data
--------------------------------------------
	process(REG_ADR, ID1_REG, ID0_REG, Power,
			ST1_REG, ST0_REG, TR1_REG, TR0_REG,
			PRO_A5, PRO_A4, PRO_A3,
			PRO_A2, PRO_A1, PRO_A0,
			S00P3, S00P2, S00P1, S00P0,
			S01P3, S01P2, S01P1, S01P0,
			S02P3, S02P2, S02P1, S02P0,
			S03P3, S03P2, S03P1, S03P0,
			S04P3, S04P2, S04P1, S04P0,
			S05P3, S05P2, S05P1, S05P0,
			S10P3, S10P2, S10P1, S10P0,
			S11P3, S11P2, S11P1, S11P0,
			S12P3, S12P2, S12P1, S12P0,
			S13P3, S13P2, S13P1, S13P0,
			S14P3, S14P2, S14P1, S14P0,
			S15P3, S15P2, S15P1, S15P0,
			S00TD, S01TD, S02TD, S03TD,
			S04TD, S05TD, S10TD, S11TD,
			S12TD, S13TD, S14TD, S15TD,
			L1TES)
	begin
		case REG_ADR is
			when "000001" =>
				VMD_OUT(15 downto  8) <= ID1_REG(7 downto 0);
				VMD_OUT(7  downto  0) <= ID0_REG(7 downto 0);
			when "000000" =>
				VMD_OUT(15 downto 13) <= "000";
				VMD_OUT(12)           <= Power;
				VMD_OUT(11 downto 10) <= "00";
				VMD_OUT(9  downto  8) <= ST1_REG(1 downto 0);
				VMD_OUT(7  downto  6) <= "00";
				VMD_OUT(5  downto  0) <= ST0_REG(5 downto 0);
			when "000011" =>
				VMD_OUT(15 downto  8) <= TR1_REG;
				VMD_OUT(7  downto  0) <= TR0_REG;
			when "000010" =>
				VMD_OUT(15 downto  8) <= PRO_A5(7 downto 0);
				VMD_OUT(7  downto  0) <= PRO_A4(7 downto 0);
			when "000101" =>
				VMD_OUT(15 downto  8) <= PRO_A3(7 downto 0);
				VMD_OUT(7  downto  0) <= PRO_A2(7 downto 0);
			when "000100" =>
				VMD_OUT(15 downto  8) <= PRO_A1(7 downto 0);
				VMD_OUT(7  downto  0) <= PRO_A0(7 downto 0);
			when "000111" =>
				VMD_OUT(15 downto  8) <= S00P3(7 downto 0);
				VMD_OUT(7  downto  0) <= S00P2(7 downto 0);
			when "000110" =>
				VMD_OUT(15 downto  8) <= S00P1(7 downto 0);
				VMD_OUT(7  downto  0) <= S00P0(7 downto 0);
			when "001001" =>
				VMD_OUT(15 downto  8) <= S01P3(7 downto 0);
				VMD_OUT(7  downto  0) <= S01P2(7 downto 0);
			when "001000" =>
				VMD_OUT(15 downto  8) <= S01P1(7 downto 0);
				VMD_OUT(7  downto  0) <= S01P0(7 downto 0);
			when "001011" =>
				VMD_OUT(15 downto  8) <= S02P3(7 downto 0);
				VMD_OUT(7  downto  0) <= S02P2(7 downto 0);
			when "001010" =>
				VMD_OUT(15 downto  8) <= S02P1(7 downto 0);
				VMD_OUT(7  downto  0) <= S02P0(7 downto 0);
			when "001101" =>
				VMD_OUT(15 downto  8) <= S03P3(7 downto 0);
				VMD_OUT(7  downto  0) <= S03P2(7 downto 0);
			when "001100" =>
				VMD_OUT(15 downto  8) <= S03P1(7 downto 0);
				VMD_OUT(7  downto  0) <= S03P0(7 downto 0);
			when "001111" =>
				VMD_OUT(15 downto  8) <= S04P3(7 downto 0);
				VMD_OUT(7  downto  0) <= S04P2(7 downto 0);
			when "001110" =>
				VMD_OUT(15 downto  8) <= S04P1(7 downto 0);
				VMD_OUT(7  downto  0) <= S04P0(7 downto 0);
			when "010001" =>
				VMD_OUT(15 downto  8) <= S05P3(7 downto 0);
				VMD_OUT(7  downto  0) <= S05P2(7 downto 0);
			when "010000" =>
				VMD_OUT(15 downto  8) <= S05P1(7 downto 0);
				VMD_OUT(7  downto  0) <= S05P0(7 downto 0);
			when "010011" =>
				VMD_OUT(15 downto  8) <= S10P3(7 downto 0);
				VMD_OUT(7  downto  0) <= S10P2(7 downto 0);
			when "010010" =>
				VMD_OUT(15 downto  8) <= S10P1(7 downto 0);
				VMD_OUT(7  downto  0) <= S10P0(7 downto 0);
			when "010101" =>
				VMD_OUT(15 downto  8) <= S11P3(7 downto 0);
				VMD_OUT(7  downto  0) <= S11P2(7 downto 0);	
			when "010100" =>
				VMD_OUT(15 downto  8) <= S11P1(7 downto 0);
				VMD_OUT(7  downto  0) <= S11P0(7 downto 0);
			when "010111" =>
				VMD_OUT(15 downto  8) <= S12P3(7 downto 0);
				VMD_OUT(7  downto  0) <= S12P2(7 downto 0);
			when "010110" =>
				VMD_OUT(15 downto  8) <= S12P1(7 downto 0);
				VMD_OUT(7  downto  0) <= S12P0(7 downto 0);
			when "011001" =>
				VMD_OUT(15 downto  8) <= S13P3(7 downto 0);
				VMD_OUT(7  downto  0) <= S13P2(7 downto 0);
			when "011000" =>
				VMD_OUT(15 downto  8) <= S13P1(7 downto 0);
				VMD_OUT(7  downto  0) <= S13P0(7 downto 0);
			when "011011" =>
				VMD_OUT(15 downto  8) <= S14P3(7 downto 0);
				VMD_OUT(7  downto  0) <= S14P2(7 downto 0);
			when "011010" =>
				VMD_OUT(15 downto  8) <= S14P1(7 downto 0);
				VMD_OUT(7  downto  0) <= S14P0(7 downto 0);
			when "011101" =>
				VMD_OUT(15 downto  8) <= S15P3(7 downto 0);
				VMD_OUT(7  downto  0) <= S15P2(7 downto 0);
			when "011100" =>
				VMD_OUT(15 downto  8) <= S15P1(7 downto 0);
				VMD_OUT(7  downto  0) <= S15P0(7 downto 0);

			when "011111" =>
				VMD_OUT(15 downto  8) <= S00TD(7 downto 0);
				VMD_OUT(7  downto  0) <= S01TD(7 downto 0);
			when "011110" =>
				VMD_OUT(15 downto  8) <= S02TD(7 downto 0);
				VMD_OUT(7  downto  0) <= S03TD(7 downto 0);
			when "100001" =>
				VMD_OUT(15 downto  8) <= S04TD(7 downto 0);
				VMD_OUT(7  downto  0) <= S05TD(7 downto 0);
			when "100000" =>
				VMD_OUT(15 downto  8) <= S10TD(7 downto 0);
				VMD_OUT(7  downto  0) <= S11TD(7 downto 0);
			when "100011" =>
				VMD_OUT(15 downto  8) <= S12TD(7 downto 0);
				VMD_OUT(7  downto  0) <= S13TD(7 downto 0);
			when "100010" =>
				VMD_OUT(15 downto  8) <= S14TD(7 downto 0);
				VMD_OUT(7  downto  0) <= S15TD(7 downto 0);
			when "100100" =>
				VMD_OUT(15 downto  8) <= "00000000";
				VMD_OUT(7  downto  0) <= L1TES(7 downto 0);
			when others =>
				VMD_OUT <= (others => '0');
		end case;
	end process;
--------------------------------------------

-- Data acknowledge response (SysCLK ->)
--------------------------------------------
	process(nDS0, SysCLK, nDS_CNT, MOD_ACT)
	begin
		if (nDS0 = '1') then
			DAT_ACK <= '0';
		elsif (SysCLK'event and SysCLK = '1') then
			if (nDS_CNT = 4 and MOD_ACT = '1') then
				DAT_ACK <= '1';
			else
				null;
			end if;
		end if;
	end process;
--------------------------
	DTACK <= DAT_ACK;
--------------------------------------------

-- Bus error response (SysCLK ->)
--------------------------------------------
	process(nDS0, SysCLK, nDS_CNT, BAS_ADR, ACTION)
	begin
		if (nDS0 = '1') then
			BError <= '0';
		elsif (SysCLK'event and SysCLK = '1') then
			if (nDS_CNT = 3 and BAS_ADR = '1' and ACTION = '0') then
				BError <= '1';
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Buffering the raw data
--------------------------------------------
	process(RDstb, ID0_REG,
			TR1_REG, TR0_REG,
			PRO_A5, PRO_A4, PRO_A3,
			PRO_A2, PRO_A1, PRO_A0,
			S00P0, S00P1, S00P2, S00P3,
			S01P0, S01P1, S01P2, S01P3,
			S02P0, S02P1, S02P2, S02P3,
			S03P0, S03P1, S03P2, S03P3,
			S04P0, S04P1, S04P2, S04P3,
			S05P0, S05P1, S05P2, S05P3,
			S10P0, S10P1, S10P2, S10P3,
			S11P0, S11P1, S11P2, S11P3,
			S12P0, S12P1, S12P2, S12P3,
			S13P0, S13P1, S13P2, S13P3,
			S14P0, S14P1, S14P2, S14P3,
			S15P0, S15P1, S15P2, S15P3,
			S00TD, S01TD, S02TD, S03TD,
			S04TD, S05TD, S10TD, S11TD,
			S12TD, S13TD, S14TD, S15TD,
			L1TES)
	begin
		if (RDstb'event and RDstb = '0') then

			ID0_RGB <= ID0_REG;

			TR1_RGB <= TR1_REG;
			TR0_RGB <= TR0_REG;

			PRO_B5 <= PRO_A5;
			PRO_B4 <= PRO_A4;
			PRO_B3 <= PRO_A3;
			PRO_B2 <= PRO_A2;
			PRO_B1 <= PRO_A1;
			PRO_B0 <= PRO_A0;

			B00P0 <= S00P0;
			B00P1 <= S00P1;
			B00P2 <= S00P2;
			B00P3 <= S00P3;

			B01P0 <= S01P0;
			B01P1 <= S01P1;
			B01P2 <= S01P2;
			B01P3 <= S01P3;

			B02P0 <= S02P0;
			B02P1 <= S02P1;
			B02P2 <= S02P2;
			B02P3 <= S02P3;

			B03P0 <= S03P0;
			B03P1 <= S03P1;
			B03P2 <= S03P2;
			B03P3 <= S03P3;

			B04P0 <= S04P0;
			B04P1 <= S04P1;
			B04P2 <= S04P2;
			B04P3 <= S04P3;

			B05P0 <= S05P0;
			B05P1 <= S05P1;
			B05P2 <= S05P2;
			B05P3 <= S05P3;

			B10P0 <= S10P0;
			B10P1 <= S10P1;
			B10P2 <= S10P2;
			B10P3 <= S10P3;

			B11P0 <= S11P0;
			B11P1 <= S11P1;
			B11P2 <= S11P2;
			B11P3 <= S11P3;

			B12P0 <= S12P0;
			B12P1 <= S12P1;
			B12P2 <= S12P2;
			B12P3 <= S12P3;

			B13P0 <= S13P0;
			B13P1 <= S13P1;
			B13P2 <= S13P2;
			B13P3 <= S13P3;

			B14P0 <= S14P0;
			B14P1 <= S14P1;
			B14P2 <= S14P2;
			B14P3 <= S14P3;

			B15P0 <= S15P0;
			B15P1 <= S15P1;
			B15P2 <= S15P2;
			B15P3 <= S15P3;

			S00TB <= S00TD;
			S01TB <= S01TD;
			S02TB <= S02TD;
			S03TB <= S03TD;
			S04TB <= S04TD;
			S05TB <= S05TD;
			S10TB <= S10TD;
			S11TB <= S11TD;
			S12TB <= S12TD;
			S13TB <= S13TD;
			S14TB <= S14TD;
			S15TB <= S15TD;

			L1TER <= L1TES;
		end if;
	end process;
--------------------------------------------

-- Pipelining the raw data
--------------------------------------------
	process(RDstb, ID0_RGB,
			TR1_RGB, TR0_RGB,
			PRO_B5, PRO_B4, PRO_B3,
			PRO_B2, PRO_B1, PRO_B0,
			B00P3, B00P2, B00P1, B00P0,
			B01P3, B01P2, B01P1, B01P0,
			B02P3, B02P2, B02P1, B02P0,
			B03P3, B03P2, B03P1, B03P0,
			B04P3, B04P2, B04P1, B04P0,
			B05P3, B05P2, B05P1, B05P0,
			B10P3, B10P2, B10P1, B10P0,
			B11P3, B11P2, B11P1, B11P0,
			B12P3, B12P2, B12P1, B12P0,
			B13P3, B13P2, B13P1, B13P0,
			B14P3, B14P2, B14P1, B14P0,
			B15P3, B15P2, B15P1, B15P0,
			S00TB, S01TB, S02TB, S03TB,
			S04TB, S05TB, S10TB, S11TB,
			S12TB, S13TB, S14TB, S15TB,
			L1TER, Rdata)
	begin
		if (RDstb'event and RDstb = '1') then

			ID1_REG <= ID0_RGB;
			ID0_REG <= TR1_RGB;

			TR1_REG <= TR0_RGB;
			TR0_REG <= PRO_B5;

			PRO_A5 <= PRO_B4;
			PRO_A4 <= PRO_B3;
			PRO_A3 <= PRO_B2;
			PRO_A2 <= PRO_B1;
			PRO_A1 <= PRO_B0;
			PRO_A0 <= B00P3;

			S00P3 <= B00P2;
			S00P2 <= B00P1;
			S00P1 <= B00P0;
			S00P0 <= B01P3;

			S01P3 <= B01P2;
			S01P2 <= B01P1;
			S01P1 <= B01P0;
			S01P0 <= B02P3;

			S02P3 <= B02P2;
			S02P2 <= B02P1;
			S02P1 <= B02P0;
			S02P0 <= B03P3;

			S03P3 <= B03P2;
			S03P2 <= B03P1;
			S03P1 <= B03P0;
			S03P0 <= B04P3;

			S04P3 <= B04P2;
			S04P2 <= B04P1;
			S04P1 <= B04P0;
			S04P0 <= B05P3;

			S05P3 <= B05P2;
			S05P2 <= B05P1;
			S05P1 <= B05P0;
			S05P0 <= B10P3;

			S10P3 <= B10P2;
			S10P2 <= B10P1;
			S10P1 <= B10P0;
			S10P0 <= B11P3;

			S11P3 <= B11P2;
			S11P2 <= B11P1;
			S11P1 <= B11P0;
			S11P0 <= B12P3;

			S12P3 <= B12P2;
			S12P2 <= B12P1;
			S12P1 <= B12P0;
			S12P0 <= B13P3;

			S13P3 <= B13P2;
			S13P2 <= B13P1;
			S13P1 <= B13P0;
			S13P0 <= B14P3;

			S14P3 <= B14P2;
			S14P2 <= B14P1;
			S14P1 <= B14P0;
			S14P0 <= B15P3;

			S15P3 <= B15P2;
			S15P2 <= B15P1;
			S15P1 <= B15P0;
			S15P0 <= S00TB;

			S00TD <= S01TB;
			S01TD <= S02TB;
			S02TD <= S03TB;
			S03TD <= S04TB;
			S04TD <= S05TB;
			S05TD <= S10TB;
			S10TD <= S11TB;
			S11TD <= S12TB;
			S12TD <= S13TB;
			S13TD <= S14TB;
			S14TD <= S15TB;
			S15TD <= L1TER;

			L1TES <= Rdata;
		end if;
	end process;
--------------------------------------------

-- Power failure latch. The triggered
-- watchdog will be cleared after the
-- event readout.
--------------------------------------------
	process(P50_Ok, WDG_CLR)
	begin
		if (P50_Ok = '0') then
			PWR_REG(4) <= '0';
		elsif (WDG_CLR'event and WDG_CLR = '0') then
			PWR_REG(4) <= '1';
		end if;
	end process;
--------------------------
	process(P33_Ok, WDG_CLR)
	begin
		if (P33_Ok = '0') then
			PWR_REG(3) <= '0';
		elsif (WDG_CLR'event and WDG_CLR = '0') then
			PWR_REG(3) <= '1';
		end if;
	end process;
--------------------------
	process(P25_Ok, WDG_CLR)
	begin
		if (P25_Ok = '0') then
			PWR_REG(2) <= '0';
		elsif (WDG_CLR'event and WDG_CLR = '0') then
			PWR_REG(2) <= '1';
		end if;
	end process;
--------------------------
	process(P18_Ok, WDG_CLR)
	begin
		if (P18_Ok = '0') then
			PWR_REG(1) <= '0';
		elsif (WDG_CLR'event and WDG_CLR = '0') then
			PWR_REG(1) <= '1';
		end if;
	end process;
--------------------------
	process(N50_Ok, WDG_CLR)
	begin
		if (N50_Ok = '1') then
			PWR_REG(0) <= '0';
		elsif (WDG_CLR'event and WDG_CLR = '0') then
			PWR_REG(0) <= '1';
		end if;
	end process;
--------------------------------------------

-- Latch status before readout (SysCLK->)
--------------------------------------------
	process(SysCLK, nDS_CNT, MOD_ACT, nWrite,
			REG_ADR, PWR_REG, FERin, LAM1, LAM0)
	begin
		if (SysCLK'event and SysCLK = '1') then
			if (nDS_CNT = 3  and MOD_ACT = '1' and
				nWrite = '1' and REG_ADR = "000001") then
				Power <= PWR_REG(4) and PWR_REG(3) and PWR_REG(2) and
						 PWR_REG(1) and PWR_REG(0);
				ST1_REG(1 downto 0) <= FERin(1 downto 0);
				ST0_REG(5 downto 3) <= LAM1(2 downto 0);
				ST0_REG(2 downto 0) <= LAM0(2 downto 0);
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Clear power watchdogs (SysCLK ->)
--------------------------------------------
	process(nDS0, SysCLK, nDS_CNT, MOD_ACT, nWrite, REG_ADR)
	begin
		if (nDS0 = '1') then
			WDG_CLR <= '0';
		elsif (SysCLK'event and SysCLK = '1') then
			if (nDS_CNT = 3  and MOD_ACT = '1' and
				nWrite = '1' and REG_ADR = "000001") then
				WDG_CLR <= '1';
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Front-end ready:
--   LAM ENA STA
--    X   0   1
--    1   1   1
--    0   1   0
-- nSTA =   nLAM &   ENA
--  STA =  n(LAM || nENA)
--------------------------------------------
	STM_REG(0) <= not(LAM0(0) or not(TR0_REG(0) or TR0_REG(1)));
	STM_REG(1) <= not(LAM0(1) or not(TR0_REG(2) or TR0_REG(3)));
	STM_REG(2) <= not(LAM0(2) or not(TR0_REG(4) or TR0_REG(5)));
	STM_REG(3) <= not(LAM1(0) or not(TR1_REG(2) or TR1_REG(3)));
	STM_REG(4) <= not(LAM1(1) or not(TR1_REG(4) or TR1_REG(5)));
	STM_REG(5) <= not(LAM1(2) or not(TR1_REG(6) or TR1_REG(7)));
--------------------------
	Status <= STM_REG(0) and STM_REG(1) and STM_REG(2) and
			  STM_REG(3) and STM_REG(4) and STM_REG(5);
--------------------------
	FERout <= PWR_REG(4) and PWR_REG(3) and PWR_REG(2) and
			  PWR_REG(1) and PWR_REG(0) and Status and
			  FERin(1)   and FERin(0);
--------------------------------------------

end;