-- Synchronization and delay processor for control
-- signals "HERA clock", "Pipeline Enable" and
-- "Clear" of the H1 trigger system. Normally
-- these signals are received from the H1 central
-- trigger and provided via the backplane connector,
-- but they can be taken from the front pannel or
-- generated internally as well. The routing scheme:
--
--                                    ___ Front panel
--                                   /
--                    ___External___/
--                   /              \
--                  /                \___ Backplane
--                 /
--  Front-end ____/                 
--                \
--                 \                  ___ Auto clock
--                  \                /
--                   \___Internal___/
--                                  \
--                                   \___ Manual clock
--
-- Front-end = External ("EXT_SRC" is removed) / Internal    ("EXT_SRC" is set)
-- External = Backplane ("BCK_PAN" is removed) / Front panel ("BCK_PAN" is set)
-- Internal = Autoclock ("AUT_SEQ" is removed) / Pushbutton  ("AUT_SEQ" is set)
--
--   Jumpers (top view):
--      EXT_SRC  BCK_PAN  AUT_SEQ  Spare  Spare  CAB_INC  CAB_INC  CAB_INC
--
-- A signal "L1 Keep" is derived from the "Pipeline
-- Enable" and "Clear" and is sent to the front-end.
-- Its complementary signal "L1 Active" may start
-- earlier than the "Pipeline Enable" - that makes
-- the data possible to ripple through the memory.
-- 
-- Input receivers AM26LV32 drive high potentials
-- if the trigger cables are unplugged. Therefore
-- all signals passed via the trigger cables have
-- an inversed polarity (active = low). Without
-- these cables the pipeline is opened and the
-- "Clear" signals are absent.
-------------------------------------------- 

-- Copyright I.Tsurin, University of Antwerpen,
-- on behalf of DESY.
--------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;

--	OK. Here the entity starts...
--------------------------------------------
entity Clksync is

port(
	HCLK: in std_logic;		  					-- HERA clock frequency;
	GEN:  in std_logic;		  					-- Front panel "Clock" signal;

	LAM: in  std_logic_vector(2 downto 0);		-- "LAM" signal of the state machine;
	FER: out std_logic;							-- Power status of the trigger card;

	RUN: in std_logic;		  					-- H1 control signal "RUN";

	RUN_LED: out std_logic;	 					-- "RUN" front panel indicator;
	L1K_LED: out std_logic;	  					-- "L1Keep" front panel indicator;

	DLY_OUT: out std_logic;						-- TCLK or GEN multiplexed output;
	DLY_TAP: in  std_logic_vector(9 downto 0);	-- Delayed HERA clock pulses;

	TCLK: out std_logic_vector(2 downto 0);		-- Clock frequency for the front-end;
	TRES: out std_logic_vector(2 downto 0);		-- "Clear" signal for the front-end;
	TRH:  out std_logic_vector(2 downto 0);		-- "L1Keep" signal for the front-end;

	PEN:  in std_logic;							-- H1 control signal "Pipeline Enable";
	FCLR: in std_logic;							-- H1 control signal "Fast Clear";

	L2KPul:  in std_logic;						-- not used;
	nSetFER: in std_logic;						-- not used;

	N50_Ok: in std_logic;	-- Power watchdog for -5 volts ("Voltage ON" = '0');
	P33_Ok: in std_logic;	-- Power watchdog for +3.3 volts ("Voltage ON" = '1');
	P50_Ok: in std_logic;	-- Power watchdog for +5 volts ("Voltage ON" = '1');

	TSTB: out std_logic_vector(2 downto 0);		-- Write strobes for the PQZP data;

	TSTB_SW: in std_logic_vector(3 downto 0);	-- Delay adjustment switch;
	TRHR_SW: in std_logic_vector(3 downto 0);	-- Delay adjustment switch;
	TRHF_SW: in std_logic_vector(3 downto 0);	-- Delay adjustment switch;
	TCLK_SW: in std_logic_vector(3 downto 0);	-- Delay adjustment switch;

	CAB_INC: in std_logic_vector(2 downto 0);	-- "LAM" signal bypasses;

	Spare: in std_logic_vector(1 downto 0);		-- Spare signals;

	AUT_SEQ: in std_logic;						-- Single sequence option;
	BCK_PAN: in std_logic;						-- Backplane control option;
	EXT_SRC: in std_logic;						-- Select the source of controls:
												--   front or rear panel (jumper is removed);
												--   internal subroutine (jumper is set);

	Enable: in std_logic;						-- Front panel "Pipeline Enable" signal;
	Clear: in std_logic;						-- Front panel "Fast Clear" signal;

	Force: in std_logic							-- On-board "Clock" pushbutton for debugging
												-- (functional in the internal operating mode);
	);

	attribute pinnum: string;

	attribute pinnum of HCLK: signal is "7";
	attribute pinnum of GEN:  signal is "8";

	attribute pinnum of LAM: signal is "11,10,9";
	attribute pinnum of FER: signal is "13";

	attribute pinnum of RUN: signal is "17";

	attribute pinnum of RUN_LED: signal is "19";
	attribute pinnum of L1K_LED: signal is "20";

	attribute pinnum of DLY_OUT: signal is "22";
	attribute pinnum of DLY_TAP: signal is "36,33,32,31,30,29,28,27,26,23";

	attribute pinnum of TCLK: signal is "39,38,37";
	attribute pinnum of TRES: signal is "49,48,47";
	attribute pinnum of TRH:  signal is "65,64,63";

	attribute pinnum of TSTB: signal is "43,42,41";

	attribute pinnum of PEN:  signal is "46";
	attribute pinnum of FCLR: signal is "62";

	attribute pinnum of L2KPul:  signal is "67";
	attribute pinnum of nSetFER: signal is "68";

	attribute pinnum of N50_Ok: signal is "79";
	attribute pinnum of P33_Ok: signal is "80";
	attribute pinnum of P50_Ok: signal is "81";

	attribute pinnum of TSTB_SW: signal is "83,86,87,88";
	attribute pinnum of TRHR_SW: signal is "89,90,91,92";
	attribute pinnum of TRHF_SW: signal is "95,96,97,98";
	attribute pinnum of TCLK_SW: signal is "99,100,101,102";

	attribute pinnum of CAB_INC: signal is "109,110,111";

	attribute pinnum of Spare: signal is "112,113";

	attribute pinnum of AUT_SEQ: signal is "114";
	attribute pinnum of BCK_PAN: signal is "116";
	attribute pinnum of EXT_SRC: signal is "117";

	attribute pinnum of Enable: signal is "142";
	attribute pinnum of Clear: signal is "143";

	attribute pinnum of Force: signal is "144";

end;

architecture behavior of Clksync is

	signal SYN_SEL: std_logic;
	signal MAN_SEL: std_logic;
	signal PEN_SEL: std_logic;
	signal CLR_SEL: std_logic;

	signal SYN_BUF: std_logic;
	signal PEN_BUF: std_logic;
	signal CLR_BUF: std_logic;

	signal TCLK_SYN: Std_logic;
	signal MAN_SYN:  std_logic;

	signal TRHR_SYN: std_logic;
	signal TRHF_SYN: std_logic;

	signal TSTB_SYN: std_logic;
	signal TSTB_MAN: std_logic;

	signal TCLK_CNT: natural range 0 to 31;
	signal TRHR_CNT: natural range 0 to 31;
	signal TRHF_CNT: natural range 0 to 31;
	signal TSTB_CNT: natural range 0 to 31;

	signal TRHR_VAL: natural range 0 to 31;
	signal TRHF_VAL: natural range 0 to 31;
	signal TSTB_VAL: natural range 0 to 31;

	signal MAN_TL0: std_logic;
	signal MAN_TL1: std_logic;
	signal MAN_TL2: std_logic;
	signal MAN_TL3: std_logic;
	signal MAN_TL4: std_logic;
	signal MAN_TL5: std_logic;
	signal MAN_TL6: std_logic;
	signal MAN_TL7: std_logic;
	signal MAN_TL8: std_logic;
	signal MAN_TL9: std_logic;

	signal PEN_TL0: std_logic;
	signal PEN_TL1: std_logic;
	signal PEN_TL2: std_logic;
	signal PEN_TL3: std_logic;
	signal PEN_TL4: std_logic;
	signal PEN_TL5: std_logic;
	signal PEN_TL6: std_logic;
	signal PEN_TL7: std_logic;
	signal PEN_TL8: std_logic;
	signal PEN_TL9: std_logic;

	signal CLR_TL0: std_logic;
	signal CLR_TL1: std_logic;
	signal CLR_TL2: std_logic;
	signal CLR_TL3: std_logic;
	signal CLR_TL4: std_logic;
	signal CLR_TL5: std_logic;
	signal CLR_TL6: std_logic;
	signal CLR_TL7: std_logic;
	signal CLR_TL8: std_logic;
	signal CLR_TL9: std_logic;

	signal Gate: std_logic;
	signal L1Keep: std_logic;
	signal FED_CLK: std_logic;
		
	signal BUT_ENA: std_logic;
	signal BUT_CNT: natural range 0 to 131071;	-- 13 ms button hold time;

	signal PEN_SIM: std_logic;
	signal CLR_SIM: std_logic;
	signal PEN_CNT: natural range 0 to 31;		-- 2..21  b.c. - pipeline enable;
												-- 22..27 b.c. - raw data output;
												-- 28..0  b.c. - "free flying";
												--      1 b.c. - "fast reset".
	signal Oscillator: std_logic;
	signal Permission: std_logic;
	signal Fast_Reset: std_logic;

	signal Source: std_logic;
	signal Strobe: std_logic;

	signal STB_EN0: std_logic;
	signal STB_EN1: std_logic;
	signal STB_EN2: std_logic;

	signal PWR_REG: std_logic_vector(2 downto 0);

	signal RUN_CNT: natural range 0 to 8388607;	-- 0.7 Hz heartbeat;
	signal RUN_IND: std_logic;

begin

-- Permanent statements
--------------------------------------------
	DLY_OUT <= SYN_SEL;
--------------------------
	TCLK(0) <= not FED_CLK;
	TCLK(1) <= not FED_CLK;
	TCLK(2) <= not FED_CLK;
--------------------------
	TSTB(0) <= STB_EN0 and Strobe;
	TSTB(1) <= STB_EN1 and Strobe;
	TSTB(2) <= STB_EN2 and Strobe;
--------------------------
	TRH(0) <= not L1Keep;
	TRH(1) <= not L1Keep;
	TRH(2) <= not L1Keep;
--------------------------
	TRES(0) <= not TRHR_SYN;
	TRES(1) <= not TRHR_SYN;
	TRES(2) <= not TRHR_SYN;
--------------------------
	RUN_LED <= not RUN_IND;
	L1K_LED <= not L1Keep;
--------------------------------------------

-- Clock frequency with an external pulser.
-- It is useful when the H1 central trigger
-- is stopped and the default potential of
-- the HCLK signal is not known (thought to
-- be zero). The scheme allows running with
-- the "GEN" connector pluged or unpluged.
--------------------------------------------
	process(HCLK, GEN)
	begin
		case HCLK is
			when '1' =>
				Oscillator <= GEN;
			when others =>
				Oscillator <= not GEN;
			end case;
	end process;
--------------------------------------------

-- Combined "Pipeline Enable" signal
--------------------------------------------
	process(PEN, Enable)
	begin
		case PEN is
			when '1' =>
				Permission <= Enable;
			when others =>
				Permission <= not Enable;
			end case;
	end process;
--------------------------------------------

-- Combined "Fast clear" signal. It is also
-- used to shake a calibration pulse circuit
--------------------------------------------
	process(FCLR, Clear)
	begin
		case FCLR is
			when '1' =>
				Fast_Reset <= Clear;
			when others =>
				Fast_Reset <= not Clear;
			end case;
	end process;
--------------------------------------------

-- Selecting external controls between the
-- backplane and the front panel. The first
-- choice is needed when the card is operated
-- in H1 without control signals from the
-- central trigger, but the backplane signals
-- are well defined. The system will accept
-- external control automatically. The second
-- case is for the pure stand-alone operation
-- with external controls (the levels at the
-- backplane may oscillate).
--------------------------------------------
	process(BCK_PAN, Oscillator, Permission,
			Fast_Reset, GEN, Enable, Clear)
	begin
		case BCK_PAN is
			when '1' =>
				SYN_SEL <= Oscillator;	-- Clock from the backpl. / Fr. panel.;
				PEN_BUF <= Permission;	-- "Pipeline Enable" from the backpl.;
				CLR_BUF <= Fast_Reset;	-- H1 "Clear" from the backplane;
			when others =>
				SYN_SEL <= GEN;			-- "Clock" pulses (positive polarity);
				PEN_BUF <= Enable;		-- "Pipeline Enable" = ON when absent;
				CLR_BUF <= not Clear;	-- Inversed "Clear" = OFF when absent.
		end case;
	end process;
--------------------------------------------

-- Selecting between external and
-- internal controls, the clock has
-- to be external anyway (SYN_SEL)
--------------------------------------------
	process(EXT_SRC, PEN_BUF, CLR_BUF, PEN_SIM, CLR_SIM)
	begin
		case EXT_SRC is
			when '1' =>
				PEN_SEL <= PEN_BUF;
				CLR_SEL <= CLR_BUF;
			when others =>
				PEN_SEL <= PEN_SIM;
				CLR_SEL <= CLR_SIM;
		end case;
	end process;
--------------------------------------------

-- Selecting clock for the automatic
-- or manual internal controls
--------------------------------------------
	process(AUT_SEQ, SYN_SEL, MAN_SEL)
	begin
		case AUT_SEQ is
			when '1' =>
				Source <= SYN_SEL;
			when others =>
				Source <= MAN_SEL;
		end case;
	end process;
--------------------------------------------

-- Button hold (it's important
-- to use the "raw" frequency)
--------------------------------------------
	process(Force, SYN_SEL, BUT_CNT)
	begin
		if (Force = '1') then
			BUT_ENA <= '0';
		elsif (SYN_SEL'event and SYN_SEL = '1') then
			if (BUT_CNT = 131071) then
				BUT_ENA <= '0';
			else
				BUT_ENA <= '1';
			end if;
		end if;
	end process;
--------------------------------------------

-- Preventing button ringing. Signal
-- "Force" has an inversed polarity
--------------------------------------------
	process(Force, SYN_SEL, BUT_ENA)
	begin
		if (Force = '1') then
			BUT_CNT <= 0;
		elsif (SYN_SEL'event and SYN_SEL = '0') then
			if (BUT_ENA = '1') then
				BUT_CNT <= BUT_CNT + 1;
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Forming a single sequence
--------------------------------------------
	process(SYN_SEL, BUT_CNT)
	begin
		if (SYN_SEL'event and SYN_SEL = '1') then
			if (BUT_CNT = 131070) then
				MAN_SEL <= '1';
			else
				MAN_SEL <= '0';
			end if;
		end if;
	end process;
--------------------------------------------

-- Command counter
--------------------------------------------
	process(Source)
	begin
		if (Source'event and Source = '0') then
			PEN_CNT <= PEN_CNT + 1;
		end if;
	end process;
--------------------------------------------

-- Generator of "Pipeline Enable"
--------------------------------------------
	process(Source, PEN_CNT)
	begin
		if (Source'event and Source = '1') then
			case PEN_CNT is
				when 2 to 21 =>
					PEN_SIM <= '1';
				when others =>
					PEN_SIM <= '0';
			end case;
		end if;
	end process;
--------------------------------------------

-- Generator of "Fast Clear"
--------------------------------------------
	process(Source, PEN_CNT)
	begin
		if (Source'event and Source = '1') then
			case PEN_CNT is
				when 1 =>
					CLR_SIM <= '1';
				when others =>
					CLR_SIM <= '0';
			end case;
		end if;
	end process;
--------------------------------------------

-- Phase adjustment for TCLK.
-- For zero value of the TCLK switch the
-- clock will have a minimum delay of 10 ns
-- to be able to latch the control signals
-- (to prevent racing). For the undefined
-- position of this switch the original
-- clock frequency is selected.
--------------------------------------------
	process(TCLK_SW, DLY_TAP, SYN_SEL)
	begin
		case TCLK_SW is
			when "0110" =>
				TCLK_SYN <= DLY_TAP(9);
				TCLK_CNT <= 10;
			when "0111" =>
				TCLK_SYN <= DLY_TAP(8);
				TCLK_CNT <= 9;
			when "1000" =>
				TCLK_SYN <= DLY_TAP(7);
				TCLK_CNT <= 8;
			when "1001" =>
				TCLK_SYN <= DLY_TAP(6);
				TCLK_CNT <= 7;
			when "1010" =>
				TCLK_SYN <= DLY_TAP(5);
				TCLK_CNT <= 6;
			when "1011" =>
				TCLK_SYN <= DLY_TAP(4);
				TCLK_CNT <= 5;
			when "1100" =>
				TCLK_SYN <= DLY_TAP(3);
				TCLK_CNT <= 4;
			when "1101" =>
				TCLK_SYN <= DLY_TAP(2);
				TCLK_CNT <= 3;
			when "1110" =>
				TCLK_SYN <= DLY_TAP(1);
				TCLK_CNT <= 2;
			when "1111" =>
				TCLK_SYN <= DLY_TAP(0);
				TCLK_CNT <= 1;
			when others =>
				TCLK_SYN <= SYN_SEL;
				TCLK_CNT <= 0;
		end case;
	end process;
--------------------------------------------

-- Offset calc. for the rear edge of TRH.
-- For the undefined value of the TRHR switch
-- the transition of this signal will match
-- the clock rising edge.
--------------------------------------------
	process(TRHR_SW, TCLK_CNT)
	begin
		case TRHR_SW is
			when "0110" =>
				TRHR_CNT <= 9 + TCLK_CNT;
			when "0111" =>
				TRHR_CNT <= 8 + TCLK_CNT;
			when "1000" =>
				TRHR_CNT <= 7 + TCLK_CNT;
			when "1001" =>
				TRHR_CNT <= 6 + TCLK_CNT;
			when "1010" =>
				TRHR_CNT <= 5 + TCLK_CNT;
			when "1011" =>
				TRHR_CNT <= 4 + TCLK_CNT;
			when "1100" =>
				TRHR_CNT <= 3 + TCLK_CNT;
			when "1101" =>
				TRHR_CNT <= 2 + TCLK_CNT;
			when "1110" =>
				TRHR_CNT <= 1 + TCLK_CNT;
			when "1111" =>
				TRHR_CNT <= 0 + TCLK_CNT;
			when others =>
				TRHR_CNT <= 0 + TCLK_CNT;
		end case;
	end process;
--------------------------------------------

-- Periodic correction (excluding zero)
--------------------------------------------
	process(TRHR_CNT)
	begin
		case TRHR_CNT is
			when 0 to 10 =>
				TRHR_VAL <= TRHR_CNT;
			when others =>
				TRHR_VAL <= TRHR_CNT - 10;
		end case;
	end process;
--------------------------------------------

-- Offset calc. for the front edge of TRH.
-- For the undefined value of the TRHF switch
-- the transition of this signal will match
-- the clock rising edge.
--------------------------------------------
	process(TRHF_SW, TCLK_CNT)
	begin
		case TRHF_SW is
			when "0110" =>
				TRHF_CNT <= 9 + TCLK_CNT;
			when "0111" =>
				TRHF_CNT <= 8 + TCLK_CNT;
			when "1000" =>
				TRHF_CNT <= 7 + TCLK_CNT;
			when "1001" =>
				TRHF_CNT <= 6 + TCLK_CNT;
			when "1010" =>
				TRHF_CNT <= 5 + TCLK_CNT;
			when "1011" =>
				TRHF_CNT <= 4 + TCLK_CNT;
			when "1100" =>
				TRHF_CNT <= 3 + TCLK_CNT;
			when "1101" =>
				TRHF_CNT <= 2 + TCLK_CNT;
			when "1110" =>
				TRHF_CNT <= 1 + TCLK_CNT;
			when "1111" =>
				TRHF_CNT <= 0 + TCLK_CNT;
			when others =>
				TRHF_CNT <= 0 + TCLK_CNT;
		end case;
	end process;
--------------------------------------------

-- Periodic correction (excluding zero)
--------------------------------------------
	process(TRHF_CNT)
	begin
		case TRHF_CNT is
			when 0 to 10 =>
				TRHF_VAL <= TRHF_CNT;
			when others =>
				TRHF_VAL <= TRHF_CNT - 10;
		end case;
	end process;
--------------------------------------------

-- Offset calc. for TSTB pulses
-- For the undefined value of the TSTB switch
-- the transition of this signal will match
-- the clock rising edge.
--------------------------------------------
	process(TSTB_SW, TCLK_CNT)
	begin
		case TSTB_SW is
			when "0101" =>
				TSTB_CNT <= 9 + TCLK_CNT;
			when "0110" =>
				TSTB_CNT <= 8 + TCLK_CNT;
			when "0111" =>
				TSTB_CNT <= 7 + TCLK_CNT;
			when "1000" =>
				TSTB_CNT <= 6 + TCLK_CNT;
			when "1001" =>
				TSTB_CNT <= 5 + TCLK_CNT;
			when "1010" =>
				TSTB_CNT <= 4 + TCLK_CNT;
			when "1011" =>
				TSTB_CNT <= 3 + TCLK_CNT;
			when "1100" =>
				TSTB_CNT <= 2 + TCLK_CNT;
			when "1101" =>
				TSTB_CNT <= 1 + TCLK_CNT;
			when "1110" =>
				TSTB_CNT <= 0 + TCLK_CNT;
			when others =>
				TSTB_CNT <= 0 + TCLK_CNT;
		end case;
	end process;
--------------------------------------------

-- Periodic correction (excluding zero)
--------------------------------------------
	process(TSTB_CNT)
	begin
		case TSTB_CNT is
			when 0 to 10 =>
				TSTB_VAL <= TSTB_CNT;
			when others =>
				TSTB_VAL <= TSTB_CNT - 10;
		end case;
	end process;
--------------------------------------------

-- Manual clock telescope
--------------------------------------------
	process(DLY_TAP(0), MAN_SEL)
	begin
		if (DLY_TAP(0)'event and DLY_TAP(0) = '1') then
			MAN_TL0 <= MAN_SEL;
		end if;
	end process;
--------------------------
	process(DLY_TAP(1), MAN_TL0)
	begin
		if (DLY_TAP(1)'event and DLY_TAP(1) = '1') then
			MAN_TL1 <= MAN_TL0;
		end if;
	end process;
--------------------------
	process(DLY_TAP(2), MAN_TL1)
	begin
		if (DLY_TAP(2)'event and DLY_TAP(2) = '1') then
			MAN_TL2 <= MAN_TL1;
		end if;
	end process;
--------------------------
	process(DLY_TAP(3), MAN_TL2)
	begin
		if (DLY_TAP(3)'event and DLY_TAP(3) = '1') then
			MAN_TL3 <= MAN_TL2;
		end if;
	end process;
--------------------------
	process(DLY_TAP(4), MAN_TL3)
	begin
		if (DLY_TAP(4)'event and DLY_TAP(4) = '1') then
			MAN_TL4 <= MAN_TL3;
		end if;
	end process;
--------------------------
	process(DLY_TAP(5), MAN_TL4)
	begin
		if (DLY_TAP(5)'event and DLY_TAP(5) = '1') then
			MAN_TL5 <= MAN_TL4;
		end if;
	end process;
--------------------------
	process(DLY_TAP(6), MAN_TL5)
	begin
		if (DLY_TAP(6)'event and DLY_TAP(6) = '1') then
			MAN_TL6 <= MAN_TL5;
		end if;
	end process;
--------------------------
	process(DLY_TAP(7), MAN_TL6)
	begin
		if (DLY_TAP(7)'event and DLY_TAP(7) = '1') then
			MAN_TL7 <= MAN_TL6;
		end if;
	end process;
--------------------------
	process(DLY_TAP(8), MAN_TL7)
	begin
		if (DLY_TAP(8)'event and DLY_TAP(8) = '1') then
			MAN_TL8 <= MAN_TL7;
		end if;
	end process;
--------------------------
	process(DLY_TAP(9), MAN_TL8)
	begin
		if (DLY_TAP(9)'event and DLY_TAP(9) = '1') then
			MAN_TL9 <= MAN_TL8;
		end if;
	end process;
--------------------------------------------

-- Reset telescope
--------------------------------------------
	process(DLY_TAP(0), CLR_SEL)
	begin
		if (DLY_TAP(0)'event and DLY_TAP(0) = '1') then
			CLR_TL0 <= CLR_SEL;
		end if;
	end process;
--------------------------
	process(DLY_TAP(1), CLR_TL0)
	begin
		if (DLY_TAP(1)'event and DLY_TAP(1) = '1') then
			CLR_TL1 <= CLR_TL0;
		end if;
	end process;
--------------------------
	process(DLY_TAP(2), CLR_TL1)
	begin
		if (DLY_TAP(2)'event and DLY_TAP(2) = '1') then
			CLR_TL2 <= CLR_TL1;
		end if;
	end process;
--------------------------
	process(DLY_TAP(3), CLR_TL2)
	begin
		if (DLY_TAP(3)'event and DLY_TAP(3) = '1') then
			CLR_TL3 <= CLR_TL2;
		end if;
	end process;
--------------------------
	process(DLY_TAP(4), CLR_TL3)
	begin
		if (DLY_TAP(4)'event and DLY_TAP(4) = '1') then
			CLR_TL4 <= CLR_TL3;
		end if;
	end process;
--------------------------
	process(DLY_TAP(5), CLR_TL4)
	begin
		if (DLY_TAP(5)'event and DLY_TAP(5) = '1') then
			CLR_TL5 <= CLR_TL4;
		end if;
	end process;
--------------------------
	process(DLY_TAP(6), CLR_TL5)
	begin
		if (DLY_TAP(6)'event and DLY_TAP(6) = '1') then
			CLR_TL6 <= CLR_TL5;
		end if;
	end process;
--------------------------
	process(DLY_TAP(7), CLR_TL6)
	begin
		if (DLY_TAP(7)'event and DLY_TAP(7) = '1') then
			CLR_TL7 <= CLR_TL6;
		end if;
	end process;
--------------------------
	process(DLY_TAP(8), CLR_TL7)
	begin
		if (DLY_TAP(8)'event and DLY_TAP(8) = '1') then
			CLR_TL8 <= CLR_TL7;
		end if;
	end process;
--------------------------
	process(DLY_TAP(9), CLR_TL8)
	begin
		if (DLY_TAP(9)'event and DLY_TAP(9) = '1') then
			CLR_TL9 <= CLR_TL8;
		end if;
	end process;
--------------------------------------------

-- "Pipeline enable" telescope
--------------------------------------------
	process(DLY_TAP(0), PEN_SEL)
	begin
		if (DLY_TAP(0)'event and DLY_TAP(0) = '1') then
			PEN_TL0 <= PEN_SEL;
		end if;
	end process;
--------------------------
	process(DLY_TAP(1), PEN_TL0)
	begin
		if (DLY_TAP(1)'event and DLY_TAP(1) = '1') then
			PEN_TL1 <= PEN_TL0;
		end if;
	end process;
--------------------------
	process(DLY_TAP(2), PEN_TL1)
	begin
		if (DLY_TAP(2)'event and DLY_TAP(2) = '1') then
			PEN_TL2 <= PEN_TL1;
		end if;
	end process;
--------------------------
	process(DLY_TAP(3), PEN_TL2)
	begin
		if (DLY_TAP(3)'event and DLY_TAP(3) = '1') then
			PEN_TL3 <= PEN_TL2;
		end if;
	end process;
--------------------------
	process(DLY_TAP(4), PEN_TL3)
	begin
		if (DLY_TAP(4)'event and DLY_TAP(4) = '1') then
			PEN_TL4 <= PEN_TL3;
		end if;
	end process;
--------------------------
	process(DLY_TAP(5), PEN_TL4)
	begin
		if (DLY_TAP(5)'event and DLY_TAP(5) = '1') then
			PEN_TL5 <= PEN_TL4;
		end if;
	end process;
--------------------------
	process(DLY_TAP(6), PEN_TL5)
	begin
		if (DLY_TAP(6)'event and DLY_TAP(6) = '1') then
			PEN_TL6 <= PEN_TL5;
		end if;
	end process;
--------------------------
	process(DLY_TAP(7), PEN_TL6)
	begin
		if (DLY_TAP(7)'event and DLY_TAP(7) = '1') then
			PEN_TL7 <= PEN_TL6;
		end if;
	end process;
--------------------------
	process(DLY_TAP(8), PEN_TL7)
	begin
		if (DLY_TAP(8)'event and DLY_TAP(8) = '1') then
			PEN_TL8 <= PEN_TL7;
		end if;
	end process;
--------------------------
	process(DLY_TAP(9), PEN_TL8)
	begin
		if (DLY_TAP(9)'event and DLY_TAP(9) = '1') then
			PEN_TL9 <= PEN_TL8;
		end if;
	end process;
--------------------------------------------

-- Phase adjustment for the manual clock
--------------------------------------------
	process(TCLK_CNT, MAN_TL9, MAN_TL8, MAN_TL7,
			 MAN_TL6, MAN_TL5, MAN_TL4, MAN_TL3,
			 MAN_TL2, MAN_TL1, MAN_TL0, MAN_SEL)
	begin
		case TCLK_CNT is
			when 10 =>
				MAN_SYN <= MAN_TL9;
			when 9 =>
				MAN_SYN <= MAN_TL8;
			when 8 =>
				MAN_SYN <= MAN_TL7;
			when 7 =>
				MAN_SYN <= MAN_TL6;
			when 6 =>
				MAN_SYN <= MAN_TL5;
			when 5 =>
				MAN_SYN <= MAN_TL4;
			when 4 =>
				MAN_SYN <= MAN_TL3;
			when 3 =>
				MAN_SYN <= MAN_TL2;
			when 2 =>
				MAN_SYN <= MAN_TL1;
			when 1 =>
				MAN_SYN <= MAN_TL0;
			when others =>
				MAN_SYN <= MAN_SEL;
		end case;
	end process;
--------------------------------------------

-- Phase adjustment for the front edge of TRH
--------------------------------------------
	process(TRHF_VAL, PEN_TL9, PEN_TL8, PEN_TL7,
			PEN_TL6, PEN_TL5, PEN_TL4, PEN_TL3,
			PEN_TL2, PEN_TL1, PEN_TL0, PEN_SEL)
	begin
		case TRHF_VAL is
			when 10 =>
				TRHF_SYN <= PEN_TL9;
			when 9 =>
				TRHF_SYN <= PEN_TL8;
			when 8 =>
				TRHF_SYN <= PEN_TL7;
			when 7 =>
				TRHF_SYN <= PEN_TL6;
			when 6 =>
				TRHF_SYN <= PEN_TL5;
			when 5 =>
				TRHF_SYN <= PEN_TL4;
			when 4 =>
				TRHF_SYN <= PEN_TL3;
			when 3 =>
				TRHF_SYN <= PEN_TL2;
			when 2 =>
				TRHF_SYN <= PEN_TL1;
			when 1 =>
				TRHF_SYN <= PEN_TL0;
			when others =>
				TRHF_SYN <= PEN_SEL;
		end case;
	end process;
--------------------------------------------

-- Phase adjustment for the rear edge of TRH
--------------------------------------------
	process(TRHR_VAL, CLR_TL9, CLR_TL8, CLR_TL7,
			CLR_TL6, CLR_TL5, CLR_TL4, CLR_TL3,
			CLR_TL2, CLR_TL1, CLR_TL0, CLR_SEL)
	begin
		case TRHR_VAL is
			when 10 =>
				TRHR_SYN <= CLR_TL9;
			when 9 =>
				TRHR_SYN <= CLR_TL8;
			when 8 =>
				TRHR_SYN <= CLR_TL7;
			when 7 =>
				TRHR_SYN <= CLR_TL6;
			when 6 =>
				TRHR_SYN <= CLR_TL5;
			when 5 =>
				TRHR_SYN <= CLR_TL4;
			when 4 =>
				TRHR_SYN <= CLR_TL3;
			when 3 =>
				TRHR_SYN <= CLR_TL2;
			when 2 =>
				TRHR_SYN <= CLR_TL1;
			when 1 =>
				TRHR_SYN <= CLR_TL0;
			when others =>
				TRHR_SYN <= CLR_SEL;
		end case;
	end process;
--------------------------------------------

-- Phase shift adjustment for TSTB
--------------------------------------------
	process(TSTB_VAL, DLY_TAP, MAN_TL9, MAN_TL8,
			 MAN_TL7, MAN_TL6, MAN_TL5, MAN_TL4,
			 MAN_TL3, MAN_TL2, MAN_TL1, MAN_TL0,
			 SYN_SEL, MAN_SEL)
	begin
		case TSTB_VAL is
			when 10 =>
				TSTB_SYN <= DLY_TAP(9);
				TSTB_MAN <= MAN_TL9;
			when 9 =>
				TSTB_SYN <= DLY_TAP(8);
				TSTB_MAN <= MAN_TL8;
			when 8 =>
				TSTB_SYN <= DLY_TAP(7);
				TSTB_MAN <= MAN_TL7;
			when 7 =>
				TSTB_SYN <= DLY_TAP(6);
				TSTB_MAN <= MAN_TL6;
			when 6 =>
				TSTB_SYN <= DLY_TAP(5);
				TSTB_MAN <= MAN_TL5;
			when 5 =>
				TSTB_SYN <= DLY_TAP(4);
				TSTB_MAN <= MAN_TL4;
			when 4 =>
				TSTB_SYN <= DLY_TAP(3);
				TSTB_MAN <= MAN_TL3;
			when 3 =>
				TSTB_SYN <= DLY_TAP(2);
				TSTB_MAN <= MAN_TL2;
			when 2 =>
				TSTB_SYN <= DLY_TAP(1);
				TSTB_MAN <= MAN_TL1;
			when 1 =>
				TSTB_SYN <= DLY_TAP(0);
				TSTB_MAN <= MAN_TL0;
			when others =>
				TSTB_SYN <= SYN_SEL;
				TSTB_MAN <= MAN_SEL;
		end case;
	end process;
--------------------------------------------

-- Selecting the clock for the front-end
--------------------------------------------
	process(AUT_SEQ, TCLK_SYN, MAN_SYN)
	begin
		case AUT_SEQ is
			when '1' =>
				FED_CLK <= TCLK_SYN;
			when others =>
				FED_CLK <= MAN_SYN;
		end case;
	end process;
--------------------------------------------

-- Selecting the strobe for the H1 CT
--------------------------------------------
	process(AUT_SEQ, TSTB_SYN, TSTB_MAN)
	begin
		case AUT_SEQ is
			when '1' =>
				Strobe <= TSTB_SYN;
			when others =>
				Strobe <= TSTB_MAN;
		end case;
	end process;
--------------------------------------------

-- Enable the data strobe
--------------------------------------------
	process(LAM(0), CAB_INC(0))
	begin
		if (LAM(0) = '1' or CAB_INC(0) = '0') then
			STB_EN0 <= '1';
		else
			STB_EN0 <= '0';
		end if;
	end process;
--------------------------
	process(LAM(1), CAB_INC(1))
	begin
		if (LAM(1) = '1' or CAB_INC(1) = '0') then
			STB_EN1 <= '1';
		else
			STB_EN1 <= '0';
		end if;
	end process;
--------------------------
	process(LAM(2), CAB_INC(2))
	begin
		if (LAM(2) = '1' or CAB_INC(2) = '0') then
			STB_EN2 <= '1';
		else
			STB_EN2 <= '0';
		end if;
	end process;
--------------------------------------------

-- Starting the "L1Keep" signal
--------------------------------------------
	process(TRHR_SYN, TRHF_SYN)
	begin
		if (TRHR_SYN = '1') then
			Gate <= '0';
		elsif (TRHF_SYN'event and TRHF_SYN = '0') then
			Gate <= '1';
		end if;
	end process;
--------------------------------------------

-- Finishing the "L1Keep" signal
--------------------------------------------
	process(Gate, TRHR_SYN)
	begin
		if (Gate = '1') then
			L1Keep <= '1';
		elsif (TRHR_SYN'event and TRHR_SYN = '0') then
			L1Keep <= '0';
		end if;
	end process;
--------------------------------------------

-- Power failure latch. The triggered
-- watchdog will be cleared after the
-- event readout.
--------------------------------------------
	process(P50_Ok, CLR_SEL)
	begin
		if (P50_Ok = '0') then
			PWR_REG(2) <= '0';
		elsif (CLR_SEL'event and CLR_SEL = '0') then
			PWR_REG(2) <= '1';
		end if;
	end process;
--------------------------
	process(P33_Ok, CLR_SEL)
	begin
		if (P33_Ok = '0') then
			PWR_REG(1) <= '0';
		elsif (CLR_SEL'event and CLR_SEL = '0') then
			PWR_REG(1) <= '1';
		end if;
	end process;
--------------------------
	process(N50_Ok, CLR_SEL)
	begin
		if (N50_Ok = '1') then
			PWR_REG(0) <= '0';
		elsif (CLR_SEL'event and CLR_SEL = '0') then
			PWR_REG(0) <= '1';
		end if;
	end process;
--------------------------------------------

-- Forming up the FER signal 
--------------------------------------------
	FER <= PWR_REG(2) and PWR_REG(1) and PWR_REG(0);
--------------------------------------------

-- RUN indicator
--------------------------------------------
	process(RUN, SYN_SEL)
	begin
		if (RUN = '0') then
			RUN_CNT <= 0;
		elsif (SYN_SEL'event and SYN_SEL = '1') then
			RUN_CNT <= RUN_CNT + 1;
		end if;
	end process;
--------------------------
	process(RUN_CNT)
	begin
		case RUN_CNT is
			when 1 to 262143 =>
				RUN_IND <= '1';
			when others =>
				RUN_IND <= '0';
		end case;
	end process;
--------------------------------------------

end;