-- -- Output data format -------------------------------------------- -- Bit_0 - radiation monitor; -- -- Bit_1 \ Bit_7 = '1': Track projection onto the SpaCal plane -- Bit_2 | (corresponds to a certain SpaCal radius, or to some -- Bit_3 | range, because every mask allows the radius smearing); -- Bit_4 / Bit_7 = '0': Multiplicity of triggered pads (0...15), -- the value is cut on 15, if larger; -- -- Bit_5 - Calibration trigger for the horizontal tracks; -- Bit_6 - Veto flag for the high pad multiplicity ( > 6); -- Bit_7 - Track candidate (OR function of all 3x and 4x -- logical combinations of pads), to be used in -- anti-coincidence with the veto - locally or -- with a global BST veto signal; -- -- A truth table for Bit_7 and Bit_6 (entries are -- sorted accordingly to their descending priorities): -- -- Bit_7 Bit_6 Event class Bit_5...Bit_1 Purpose -- ----- ----- ---------------- ------------- ------- -- -- 1 0 Pure vertex track SpaCal radius Trigger -- 1 1 Contaminated track SpaCal radius Trig/Veto -- 0 1 Background only Multiplicity Veto -- 0 0 Empty detector Multiplicity -- -- -- The radiation monitor has a new concept: one silicon -- sensor is taken as a square unit to normalize the count -- rate. The maximum rate value among 8 sensors normalized -- onto N = 524287 counts or T ~50 ms time (whatever appears -- first) is sent out. -- The raw data package for T0 bunch crossing is sent out -- after the L1Keep acknowledge (T0 offset with respect to -- L1Keep is stored in 0x59), each sector transmits 5 bytes: -- -- 1. PRO/A load status (common for both sectors); -- 2. Plane 3 (Bit_7 = Ring_7 ... Bit_0 = Ring_0); -- 3. Plane 2; -- 4. Plane 1; -- 5. Plane 0; -- The radiation monitor is halted for that time -- and its rate is re-calculated. -------------------------------------------- -- 06.06.06 The signals TRES and TRH were swapped to -- use the latter to control the raw data transmissoin. -- The old TRH path was damaged by radiation. -- Copyright I.Tsurin, University of Antwerpen, -- on behalf of DESY. -------------------------------------------- -- Preparing to the low energy run: -- The serial data transmission was moved to the -- APEX chip. The ACEX memory 0x01...0x56 is being -- uccessed through a parellel inter-chip link. -- The new serial protocal is based on 27-bit messages, -- each bit lasts 0.8 us For the 16 MHz VME-transmitter -- (62.5 ns) the message length is equal to 350 clock -- periods (13 per bit), for the 10 MHz front-end receiver -- (96.0 ns) this corresponds to 230 clock periods (8.5 per -- bit). Messages may closely follow each other (no pause -- is required in between). The internal counters are reset -- after each word transmission, thus the errors due to -- the frequency mismatch do not accumulate. -- -- Bit_0 in the data package is a wake-up signal. Single -- event upsets can imitate beginning of the new frame, but -- the messages are protected against corruption by the code -- key 0x55 and by the parity bit. -- Data frame for the serial interface (the PCA82C250T CAN -- driver requires complementary signals) -------------------------------------------- -- Bit_26 - wake up (TX='0' -> CAN='1' -> RX='0'); -- -- Bit_25 - permanent 0; -- Bit_24 - permanent 1; -- Bit_23 - permanent 0; -- Bit_22 - permanent 1; -- Bit_21 - permanent 0; -- Bit_20 - permanent 1; -- Bit_19 - permanent 0; -- Bit_18 - permanent 1; -- -- The code key 0x55 assures -- validity of the next bit: -- -- Bit_17 - write flag = 1; -- -- Bit_16 - address Bit_6; -- Bit_15 - address Bit_5; -- Bit_14 - address Bit_4; -- Bit_13 - address Bit_3; -- Bit_12 - address Bit_2; -- Bit_11 - address Bit_1; -- Bit_10 - address Bit_0; -- -- Bit_9 - data Bit_7; -- Bit_8 - data Bit_6; -- Bit_7 - data Bit_5; -- Bit_6 - data Bit_4; -- Bit_5 - data Bit_3; -- Bit_4 - data Bit_2; -- Bit_3 - data Bit_1; -- Bit_2 - data Bit_0; -- -- Bit_1 - odd parity flag set by controller -- for bits 17...2 if the write flag = 1, -- otherwise the parity bit is set for -- bits 17...2 by the front-end; -- Bit_0 - end of package (off line: -- (TX='1' -> CAN='Z' -> RX='1') -- reset timers making the next -- wake-up possible without delay; -------------------------------------------- -- APEX steering registers: -------------------------------------------- -- 0x5A - T0 time slice for the raw data; -- The trigger channels are enabled by the PRO/A chip, -- the radiation monitor uses an additional set of maks -- loaded every time during the power-on initialization: -- 0x5C - sensor 00 gate for the RM; -- 0x5D - sensor 01 gate for the RM; -- 0x5E - sensor 02 gate for the RM; -- 0x5F - sensor 03 gate for the RM; -- 0x60 - sensor 10 gate for the RM; -- 0x61 - sensor 11 gate for the RM; -- 0x62 - sensor 12 gate for the RM; -- 0x63 - sensor 13 gate for the RM; -------------------------------------------- -- The radiation monitor uses the innermost -- four rings of the pad sensors - they have -- the lower noise and high particle occuancy -------------------------------------------- -- Changed on 18.02.07 by I.Tsurin, DESY Zeuthen -------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.numeric_std.all; -- OK. Here the entity starts... -------------------------------------------- entity NewTrig is port( Cglobal: out std_logic; -- enable comparators for calibration pulses; Tout00: in std_logic_vector(7 downto 0); -- | Detector trigger output signals; Tout01: in std_logic_vector(7 downto 0); -- | Tout02: in std_logic_vector(7 downto 0); -- | Tout03: in std_logic_vector(7 downto 0); -- | Tout10: in std_logic_vector(7 downto 0); -- | Detector trigger output signals; Tout11: in std_logic_vector(7 downto 0); -- | Tout12: in std_logic_vector(7 downto 0); -- | Tout13: in std_logic_vector(7 downto 0); -- | CalEv0: in std_logic_vector(3 downto 0); -- | Detector test output signals; CalEv1: in std_logic_vector(3 downto 0); -- | CalOd0: in std_logic_vector(3 downto 0); -- | Detector test output signals; CalOd1: in std_logic_vector(3 downto 0); -- | Tena00: out std_logic; Tena01: out std_logic; Tena02: out std_logic; Tena03: out std_logic; Tena10: out std_logic; Tena11: out std_logic; Tena12: out std_logic; Tena13: out std_logic; LAM_APX: in std_logic; -- slow control status; TCLK: in std_logic; -- HERA clock synchro-pulses; TRES: in std_logic; -- H1 trigger system reset; TRH: in std_logic; -- "L1 keep" trigger control; Mout0: out std_logic_vector(7 downto 0); -- | Mask number for the track; Mout1: out std_logic_vector(7 downto 0); -- | CalEn: in std_logic; -- Cal. pulse enable/disable = 1/0; CPul: out std_logic; -- Calibration pulse output; CPulR: out std_logic; -- CPul reserved output; TXD: out std_logic; -- Serial interface output; RXD: in std_logic; -- Serial interface input; ACX_DAT: inout std_logic_vector(7 downto 0); ACX_ADR: out std_logic_vector(6 downto 0); ACX_WRI: out std_logic; ACX_CLK: out std_logic ); attribute pinnum: string; attribute pinnum of Tout00: signal is "65,66,64,68,63,69,62,70"; attribute pinnum of Tout01: signal is "79,80,77,81,76,82,75,83"; attribute pinnum of Tout02: signal is "99,100,98,101,96,102,95,103"; attribute pinnum of Tout03: signal is "112,113,111,114,110,115,109,116"; attribute pinnum of Tout10: signal is "232,233,231,234,230,235,226,236"; attribute pinnum of Tout11: signal is "219,220,217,221,216,222,215,223"; attribute pinnum of Tout12: signal is "198,200,197,201,196,202,195,203"; attribute pinnum of Tout13: signal is "185,186,184,187,183,189,182,190"; attribute pinnum of CalEv0: signal is "117,104,84,71"; attribute pinnum of CalEv1: signal is "191,204,224,237"; attribute pinnum of CalOd0: signal is "118,105,85,74"; attribute pinnum of CalOd1: signal is "192,205,225,238"; attribute pinnum of Cglobal: signal is "156"; attribute pinnum of Tena00: signal is "61"; attribute pinnum of Tena01: signal is "88"; attribute pinnum of Tena02: signal is "94"; attribute pinnum of Tena03: signal is "119"; attribute pinnum of Tena10: signal is "239"; attribute pinnum of Tena11: signal is "212"; attribute pinnum of Tena12: signal is "207"; attribute pinnum of Tena13: signal is "206"; attribute pinnum of LAM_APX: signal is "48"; attribute pinnum of TCLK: signal is "31"; attribute pinnum of TRES: signal is "91"; attribute pinnum of TRH: signal is "209"; attribute pinnum of Mout0: signal is "121,123,124,125,126,129,130,131"; attribute pinnum of Mout1: signal is "169,170,171,172,173,174,178,180"; attribute pinnum of CalEn: signal is "166"; attribute pinnum of CPul: signal is "181"; attribute pinnum of CPulR: signal is "164"; attribute pinnum of TXD: signal is "161"; attribute pinnum of RXD: signal is "157"; attribute pinnum of ACX_DAT: signal is "163,133,134,135,136,138,143,160"; attribute pinnum of ACX_ADR: signal is "13,16,17,18,20,40,41"; attribute pinnum of ACX_WRI: signal is "43"; attribute pinnum of ACX_CLK: signal is "47"; end; architecture behavior of NewTrig is -- H1 central trigger controls -------------------------------------------- signal Clock: std_logic; signal Reset: std_logic; signal L1Keep: std_logic; -------------------------------------------- -- Initialization -------------------------------------------- signal DUM_RES: std_logic; signal RES_PUL: std_logic; signal RES_GTE: std_logic; signal INI_CNT: natural range 0 to 4194303; -------------------------------------------- -- Communication tools -------------------------------------------- signal FED_CNT: natural range 0 to 255; signal IAM_BSY: std_logic; signal FED_CLR: std_logic; signal FED_END: std_logic; signal Write: std_logic; signal COD_KEY: std_logic_vector(7 downto 0); signal INP_ADR: std_logic_vector(7 downto 0); signal INP_DAT: std_logic_vector(7 downto 0); signal REG_DAT: std_logic_vector(7 downto 0); signal PAR_INP: std_logic; signal PAR_OUT: std_logic; signal PAR_CMI: std_logic; signal DAT_STB: std_logic; signal ACX_GTE: std_logic; -------------------------------------------- -- Steering registers -------------------------------------------- signal APEX_T0: std_logic_vector(4 downto 0); signal D00_MSK: std_logic_vector(7 downto 0); signal D01_MSK: std_logic_vector(7 downto 0); signal D02_MSK: std_logic_vector(7 downto 0); signal D03_MSK: std_logic_vector(7 downto 0); signal D10_MSK: std_logic_vector(7 downto 0); signal D11_MSK: std_logic_vector(7 downto 0); signal D12_MSK: std_logic_vector(7 downto 0); signal D13_MSK: std_logic_vector(7 downto 0); -------------------------------------------- -- Synchronization scheme -------------------------------------------- signal Even_L0: std_logic_vector(31 downto 0); signal Even_L1: std_logic_vector(31 downto 0); signal Odd_L0: std_logic_vector(31 downto 0); signal Odd_L1: std_logic_vector(31 downto 0); signal Tdata0: std_logic_vector(31 downto 0); signal Tdata1: std_logic_vector(31 downto 0); signal TMP_CNT: natural range 0 to 1; signal TMP_DEL: natural range 0 to 1; signal CLR_EVE: std_logic; signal CLR_ODD: std_logic; -------------------------------------------- -- Trigger masks -------------------------------------------- signal Mask0: std_logic_vector(173 downto 0); signal Mask1: std_logic_vector(173 downto 0); -------------------------------------------- -- Data during "L1 active" -------------------------------------------- signal Thet_R0: std_logic_vector(14 downto 0); -- "Theta" range in sector 0; signal Thet_R1: std_logic_vector(14 downto 0); -- "Theta" range in sector 1; alias S0_ECH1: std_logic_vector(7 downto 0) is Thet_R0(7 downto 0); -- | "Theta" alias S1_ECH1: std_logic_vector(7 downto 0) is Thet_R1(7 downto 0); -- | subrange 1; alias S0_ECH2: std_logic_vector(3 downto 0) is Thet_R0(11 downto 8); -- | "Theta" alias S1_ECH2: std_logic_vector(3 downto 0) is Thet_R1(11 downto 8); -- | subrange 2; alias S0_ECH3: std_logic_vector(1 downto 0) is Thet_R0(13 downto 12); -- | "Theta" alias S1_ECH3: std_logic_vector(1 downto 0) is Thet_R1(13 downto 12); -- | subrange 3; signal PAD_NR0: natural range 0 to 15; -- Number of pads fired in sector 0; signal PAD_NR1: natural range 0 to 15; -- Number of pads fired in sector 1; -- (the value is cut on 15, if larger); signal MSK_RG0: std_logic_vector(3 downto 0); -- Encoded "Theta" in sector 0; signal MSK_RG1: std_logic_vector(3 downto 0); -- Encoded "Theta" in sector 1; signal ENC_DAT0: std_logic_vector(6 downto 0); -- Data for the TSCD trigger bank; signal ENC_DAT1: std_logic_vector(6 downto 0); -- Data for the TSCD trigger bank; signal DEL_BUF0: std_logic_vector(6 downto 0); -- Reliability improvement; signal DEL_BUF1: std_logic_vector(6 downto 0); -- Reliability improvement; signal TRG_DAT0: std_logic_vector(7 downto 0); -- Trigger data delayed by 1 b.c.; signal TRG_DAT1: std_logic_vector(7 downto 0); -- Trigger data delayed by 1 b.c.; -------------------------------------------- -- Raw data pipelining -------------------------------------------- signal PIP_CNT: natural range 0 to 31; -- Cycling pipeline address; signal PIP_SEL: natural range 0 to 31; -- Selected time slice to be read out; signal L1K_DEL: std_logic; signal PIP_OUT0: std_logic_vector(31 downto 0); signal PIP_OUT1: std_logic_vector(31 downto 0); signal CLS_CNT: natural range 0 to 7; signal CLS_GTE: std_logic; signal RAW_DAT0: std_logic_vector(7 downto 0); signal RAW_DAT1: std_logic_vector(7 downto 0); signal STA_REG: std_logic_vector(7 downto 0); signal STA_CNT: natural range 0 to 3; signal STA_PUL: std_logic; signal RDM_000: std_logic_vector(31 downto 0); signal RDM_001: std_logic_vector(31 downto 0); signal RDM_002: std_logic_vector(31 downto 0); signal RDM_003: std_logic_vector(31 downto 0); signal RDM_004: std_logic_vector(31 downto 0); signal RDM_005: std_logic_vector(31 downto 0); signal RDM_006: std_logic_vector(31 downto 0); signal RDM_007: std_logic_vector(31 downto 0); signal RDM_008: std_logic_vector(31 downto 0); signal RDM_009: std_logic_vector(31 downto 0); signal RDM_010: std_logic_vector(31 downto 0); signal RDM_011: std_logic_vector(31 downto 0); signal RDM_012: std_logic_vector(31 downto 0); signal RDM_013: std_logic_vector(31 downto 0); signal RDM_014: std_logic_vector(31 downto 0); signal RDM_015: std_logic_vector(31 downto 0); signal RDM_016: std_logic_vector(31 downto 0); signal RDM_017: std_logic_vector(31 downto 0); signal RDM_018: std_logic_vector(31 downto 0); signal RDM_019: std_logic_vector(31 downto 0); signal RDM_020: std_logic_vector(31 downto 0); signal RDM_021: std_logic_vector(31 downto 0); signal RDM_022: std_logic_vector(31 downto 0); signal RDM_023: std_logic_vector(31 downto 0); signal RDM_024: std_logic_vector(31 downto 0); signal RDM_025: std_logic_vector(31 downto 0); signal RDM_026: std_logic_vector(31 downto 0); signal RDM_027: std_logic_vector(31 downto 0); signal RDM_028: std_logic_vector(31 downto 0); signal RDM_029: std_logic_vector(31 downto 0); signal RDM_030: std_logic_vector(31 downto 0); signal RDM_031: std_logic_vector(31 downto 0); signal RDM_100: std_logic_vector(31 downto 0); signal RDM_101: std_logic_vector(31 downto 0); signal RDM_102: std_logic_vector(31 downto 0); signal RDM_103: std_logic_vector(31 downto 0); signal RDM_104: std_logic_vector(31 downto 0); signal RDM_105: std_logic_vector(31 downto 0); signal RDM_106: std_logic_vector(31 downto 0); signal RDM_107: std_logic_vector(31 downto 0); signal RDM_108: std_logic_vector(31 downto 0); signal RDM_109: std_logic_vector(31 downto 0); signal RDM_110: std_logic_vector(31 downto 0); signal RDM_111: std_logic_vector(31 downto 0); signal RDM_112: std_logic_vector(31 downto 0); signal RDM_113: std_logic_vector(31 downto 0); signal RDM_114: std_logic_vector(31 downto 0); signal RDM_115: std_logic_vector(31 downto 0); signal RDM_116: std_logic_vector(31 downto 0); signal RDM_117: std_logic_vector(31 downto 0); signal RDM_118: std_logic_vector(31 downto 0); signal RDM_119: std_logic_vector(31 downto 0); signal RDM_120: std_logic_vector(31 downto 0); signal RDM_121: std_logic_vector(31 downto 0); signal RDM_122: std_logic_vector(31 downto 0); signal RDM_123: std_logic_vector(31 downto 0); signal RDM_124: std_logic_vector(31 downto 0); signal RDM_125: std_logic_vector(31 downto 0); signal RDM_126: std_logic_vector(31 downto 0); signal RDM_127: std_logic_vector(31 downto 0); signal RDM_128: std_logic_vector(31 downto 0); signal RDM_129: std_logic_vector(31 downto 0); signal RDM_130: std_logic_vector(31 downto 0); signal RDM_131: std_logic_vector(31 downto 0); -------------------------------------------- -- Calibration pulse variables -------------------------------------------- signal CAL_CNT: natural range 0 to 8191; -- 10 us duration, 1 kHz rate; signal SAF_CNT: natural range 0 to 3; signal CAL_GTE: std_logic; signal SAF_GTE: std_logic; signal SAF_PUL: std_logic; -------------------------------------------- -- Radiation monitor variables -------------------------------------------- signal Sensor0: std_logic_vector(7 downto 0); signal Sensor2: std_logic_vector(7 downto 0); signal Sensor4: std_logic_vector(7 downto 0); signal Sensor6: std_logic_vector(7 downto 0); signal Sensor1: std_logic_vector(7 downto 0); signal Sensor3: std_logic_vector(7 downto 0); signal Sensor5: std_logic_vector(7 downto 0); signal Sensor7: std_logic_vector(7 downto 0); signal Shovel0: natural range 0 to 15; signal Shovel2: natural range 0 to 15; signal Shovel4: natural range 0 to 15; signal Shovel6: natural range 0 to 15; signal Shovel1: natural range 0 to 15; signal Shovel3: natural range 0 to 15; signal Shovel5: natural range 0 to 15; signal Shovel7: natural range 0 to 15; signal Basket0: natural range 0 to 524287; signal Basket2: natural range 0 to 524287; signal Basket4: natural range 0 to 524287; signal Basket6: natural range 0 to 524287; signal Basket1: natural range 0 to 524287; signal Basket3: natural range 0 to 524287; signal Basket5: natural range 0 to 524287; signal Basket7: natural range 0 to 524287; signal Overflow0: std_logic; signal Overflow2: std_logic; signal Overflow4: std_logic; signal Overflow6: std_logic; signal Overflow1: std_logic; signal Overflow3: std_logic; signal Overflow5: std_logic; signal Overflow7: std_logic; signal Push0: std_logic; signal Push1: std_logic; signal Door0: std_logic; signal Door1: std_logic; signal Timer0: natural range 0 to 524287; signal Timer1: natural range 0 to 524287; signal Gate0: std_logic; signal Gate1: std_logic; signal Collect0: std_logic; signal Collect1: std_logic; signal RM_Lock: std_logic; signal RML_DEL: std_logic; signal Firewood0: natural range 0 to 4194303; signal Firewood1: natural range 0 to 4194303; signal Oven0: natural range 0 to 4194303; signal Oven1: natural range 0 to 4194303; signal Tray0: natural range 0 to 4194303; signal Tray1: natural range 0 to 4194303; signal Limit: natural range 0 to 524287; constant Cut: natural:= 524287; signal RAD_MN0: std_logic; signal RAD_MN1: std_logic; -------------------------------------------- -- Output signals -------------------------------------------- signal Pre_M0: std_logic_vector(7 downto 0); signal Pre_M1: std_logic_vector(7 downto 0); -------------------------------------------- -- Function declaration: -------------------------- -- SUM_of_ONES_32 is used to count a number -- of pads triggered in one phi-sector. The -- result is cut on 15, if larger; -------------------------------------------- function SUM_of_ONES_32(TRIG_PAT: std_logic_vector(31 downto 0)) return natural is variable SUM_TOT: natural range 0 to 63; variable SUM_RES: natural range 0 to 15; begin SUM_TOT:= 0; for Index in TRIG_PAT'range loop if (TRIG_PAT(Index) = '1') then SUM_TOT:= SUM_TOT + 1; end if; end loop; if (15 <= SUM_TOT) then SUM_RES:= 15; else SUM_RES:= SUM_TOT; end if; return SUM_RES; end SUM_of_ONES_32; -------------------------------------------- -- SUM_of_ONES_8 is used to count a number -- of pads triggered in one silicon sensor -------------------------------------------- function SUM_of_ONES_8(TRIG_PAT: std_logic_vector(7 downto 0)) return natural is variable SUM_TOT: natural range 0 to 15; begin SUM_TOT:= 0; for Index in TRIG_PAT'range loop if (TRIG_PAT(Index) = '1') then SUM_TOT:= SUM_TOT + 1; end if; end loop; return SUM_TOT; end SUM_of_ONES_8; -------------------------------------------- -- Data type conversion: -- binary#5 -> natural -------------------------------------------- function BIT5_to_NUM(BIT_ARR: std_logic_vector(4 downto 0)) return natural is variable TEMP: natural range 0 to 31; begin TEMP:=0; for I in BIT_ARR'range loop TEMP:= TEMP * 2; if (BIT_ARR(I) = '1') then TEMP:= TEMP + 1; else null; end if; end loop; return TEMP; end BIT5_to_NUM; -------------------------------------------- -- Odd parity bit (making odd -- the entire number of ones) -------------------------------------------- function ODD_PAR(BIT_ARR: std_logic_vector(7 downto 0)) return std_logic is variable TEMP: std_logic; begin TEMP:= '1'; for I in BIT_ARR'range loop if (BIT_ARR(I) = '1') then TEMP:= not TEMP; else null; end if; end loop; return TEMP; end ODD_PAR; -------------------------------------------- begin -- Permanent statements -------------------------------------------- Clock <= not TCLK; L1Keep <= not TRH; Reset <= not TRES; -------------------------- DUM_RES <= '0'; -------------------------- Write <= INP_ADR(7); ACX_WRI <= INP_ADR(7) and ACX_GTE; -------------------------- Limit <= Cut; -------------------------- CPulR <= '0'; -------------------------- Tena00 <= not LAM_APX; Tena01 <= not LAM_APX; Tena02 <= not LAM_APX; Tena03 <= not LAM_APX; Tena10 <= not LAM_APX; Tena11 <= not LAM_APX; Tena12 <= not LAM_APX; Tena13 <= not LAM_APX; Cglobal <= not (LAM_APX and CalEn); -------------------------------------------- -- Latch PRO/A load status from ACEX -- with some delay to let the interchip -- data to stabilize -------------------------------------------- process(Clock, STA_PUL) begin if (Clock'event and Clock = '1') then if (STA_PUL = '1') then STA_CNT <= STA_CNT + 1; else STA_CNT <= 0; end if; end if; end process; -------------------------- process(LAM_APX, Clock, STA_CNT) begin if (LAM_APX = '0') then STA_PUL <= '1'; elsif (Clock'event and Clock = '0') then if (STA_CNT = 3) then STA_PUL <= '0'; else null; end if; end if; end process; -------------------------- process(STA_PUL, ACX_DAT) begin if (STA_PUL'event and STA_PUL = '0') then STA_REG <= ACX_DAT; end if; end process; -------------------------------------------- -- Start-up counter (Clock <-) -------------------------------------------- process(DUM_RES, Clock, RES_GTE) begin if (DUM_RES = '1') then INI_CNT <= 0; elsif (Clock'event and Clock = '0') then if (RES_GTE = '1') then INI_CNT <= INI_CNT + 1; else null; end if; end if; end process; -------------------------------------------- -- Start-up gate (Clock ->) -------------------------------------------- process(DUM_RES, INI_CNT, Clock) begin if (DUM_RES = '1') then RES_GTE <= '1'; elsif (Clock'event and Clock = '1') then if (INI_CNT = 4194303) then RES_GTE <= '0'; else RES_GTE <= '1'; end if; end if; end process; -------------------------------------------- -- Start-up reset pulse (Clock <-) -------------------------------------------- process(RES_GTE, Clock) begin if (RES_GTE = '0') then RES_PUL <= '0'; elsif (Clock'event and Clock = '0') then RES_PUL <= '1'; end if; end process; -------------------------------------------- -- Wake up - set busy, blocked by -- the state machine when running -------------------------------------------- process(RES_PUL, FED_CLR, FED_END, RXD, LAM_APX) begin if (RES_PUL = '1' or FED_CLR = '1' or FED_END = '1') then IAM_BSY <= '0'; elsif (RXD'event and RXD = '0') then if (LAM_APX = '1') then IAM_BSY <= '1'; else null; end if; end if; end process; -------------------------------------------- -- Frame counter (Clock <-) -------------------------------------------- process(Clock, IAM_BSY) begin if (Clock'event and Clock = '0') then if (IAM_BSY = '1') then FED_CNT <= FED_CNT + 1; else FED_CNT <= 0; end if; end if; end process; -------------------------------------------- -- Clear frame signal (Clock ->) -- if code key validation fails -- after the 77'th clock period -------------------------------------------- process(FED_CNT, Clock, COD_KEY) begin if (FED_CNT /= 77) then FED_CLR <= '0'; elsif (Clock'event and Clock = '1') then if (COD_KEY /= "01010101") then FED_CLR <= '1'; else null; end if; end if; end process; -------------------------------------------- -- End of frame signal (Clock ->) -------------------------------------------- process(FED_CNT, COD_KEY, Clock) begin if (FED_CNT /= 230) then FED_END <= '0'; elsif (Clock'event and Clock = '1') then FED_END <= '1'; end if; end process; -------------------------------------------- -- Latching serial address and data (Clock ->) -------------------------------------------- process(Clock, FED_CNT, RXD) begin if (Clock'event and Clock = '1') then case FED_CNT is when 13 => -- +8 COD_KEY(7) <= not RXD; when 22 => -- +9 COD_KEY(6) <= not RXD; when 30 => -- +8 COD_KEY(5) <= not RXD; when 39 => -- +9 COD_KEY(4) <= not RXD; when 47 => -- +8 COD_KEY(3) <= not RXD; when 56 => -- +9 COD_KEY(2) <= not RXD; when 64 => -- +8 COD_KEY(1) <= not RXD; when 73 => -- +9 COD_KEY(0) <= not RXD; when 81 => -- +8 INP_ADR(7) <= not RXD; when 90 => -- +9 INP_ADR(6) <= not RXD; when 98 => -- +8 INP_ADR(5) <= not RXD; when 107 => -- +9 INP_ADR(4) <= not RXD; when 115 => -- +8 INP_ADR(3) <= not RXD; when 124 => -- +9 INP_ADR(2) <= not RXD; when 132 => -- +8 INP_ADR(1) <= not RXD; when 141 => -- +9 INP_ADR(0) <= not RXD; when 149 => -- +8 INP_DAT(7) <= not RXD; when 158 => -- +9 INP_DAT(6) <= not RXD; when 166 => -- +8 INP_DAT(5) <= not RXD; when 175 => -- +9 INP_DAT(4) <= not RXD; when 183 => -- +8 INP_DAT(3) <= not RXD; when 192 => -- +9 INP_DAT(2) <= not RXD; when 200 => -- +8 INP_DAT(1) <= not RXD; when 209 => -- +9 INP_DAT(0) <= not RXD; when 217 => -- +8 PAR_INP <= not RXD; when others => null; end case; end if; end process; -------------------------------------------- -- Pushing out serial data (Clock ->) -------------------------------------------- process(Write, Clock, FED_CNT, REG_DAT, PAR_OUT) begin if (Write = '1') then TXD <= '1'; elsif (Clock'event and Clock = '1') then case FED_CNT is when 1 => TXD <= '1'; when 145 => -- +8 TXD <= not REG_DAT(7); when 154 => -- +9 TXD <= not REG_DAT(6); when 162 => -- +8 TXD <= not REG_DAT(5); when 171 => -- +9 TXD <= not REG_DAT(4); when 179 => -- +8 TXD <= not REG_DAT(3); when 188 => -- +9 TXD <= not REG_DAT(2); when 196 => -- +8 TXD <= not REG_DAT(1); when 205 => -- +9 TXD <= not REG_DAT(0); when 213 => -- +8 TXD <= not PAR_OUT; when 222 => -- +9 TXD <= '1'; when others => null; end case; end if; end process; -------------------------------------------- -- Monitoring parities -------------------------------------------- PAR_OUT <= ODD_PAR(INP_ADR) xnor ODD_PAR(REG_DAT); PAR_CMI <= ODD_PAR(INP_ADR) xnor ODD_PAR(INP_DAT); -------------------------------------------- -- Data write strobe for ACEX -- when the parity bit matches -------------------------------------------- process(FED_CNT, Clock, Write, PAR_INP, PAR_CMI) begin if (FED_CNT /= 222) then DAT_STB <= '0'; elsif (Clock'event and Clock = '1') then if (Write = '1' and PAR_INP = PAR_CMI) then DAT_STB <= '1'; else null; end if; end if; end process; -------------------------- process(DAT_STB, Clock) begin if (DAT_STB = '0') then ACX_CLK <= '0'; elsif (Clock'event and Clock = '0') then ACX_CLK <= '1'; end if; end process; -------------------------------------------- -- Assign the APEX steerings -- MSB of the INP_ADR register = 'Write' -------------------------------------------- process(RES_PUL, DAT_STB, INP_ADR, INP_DAT) begin if (RES_PUL = '1') then APEX_T0 <= "11011"; -- 27 dec; D00_MSK <= "00001111"; D01_MSK <= "00001111"; D02_MSK <= "00001111"; D03_MSK <= "00001111"; D10_MSK <= "00001111"; D11_MSK <= "00001111"; D12_MSK <= "00001111"; D13_MSK <= "00001111"; elsif (DAT_STB'event and DAT_STB = '1') then case INP_ADR is when "11011010" => APEX_T0 <= INP_DAT(4 downto 0); when "11011100" => D00_MSK <= INP_DAT; when "11011101" => D01_MSK <= INP_DAT; when "11011110" => D02_MSK <= INP_DAT; when "11011111" => D03_MSK <= INP_DAT; when "11100000" => D10_MSK <= INP_DAT; when "11100001" => D11_MSK <= INP_DAT; when "11100010" => D12_MSK <= INP_DAT; when "11100011" => D13_MSK <= INP_DAT; when others => null; end case; end if; end process; -------------------------------------------- -- ACEX access -------------------------------------------- process(RES_PUL, Clock, FED_CNT) begin if (RES_PUL = '1') then ACX_GTE <= '0'; elsif (Clock'event and Clock = '1') then case FED_CNT is when 141 => ACX_GTE <= '1'; when 230 => ACX_GTE <= '0'; when others => null; end case; end if; end process; -------------------------------------------- -- ACEX address -------------------------------------------- process(ACX_GTE, INP_ADR) begin if (ACX_GTE = '1') then ACX_ADR <= INP_ADR(6 downto 0); else ACX_ADR <= "0000010"; end if; end process; -------------------------------------------- -- Multiplexing readout data -------------------------------------------- process(INP_ADR, APEX_T0, D00_MSK, D01_MSK, D02_MSK, D03_MSK, D10_MSK, D11_MSK, D12_MSK, D13_MSK, ACX_DAT) begin case INP_ADR is when "01011010" => REG_DAT(7 downto 5) <= "000"; REG_DAT(4 downto 0) <= APEX_T0; when "01011100" => REG_DAT <= D00_MSK; when "01011101" => REG_DAT <= D01_MSK; when "01011110" => REG_DAT <= D02_MSK; when "01011111" => REG_DAT <= D03_MSK; when "01100000" => REG_DAT <= D10_MSK; when "01100001" => REG_DAT <= D11_MSK; when "01100010" => REG_DAT <= D12_MSK; when "01100011" => REG_DAT <= D13_MSK; when others => REG_DAT <= ACX_DAT; end case; end process; -------------------------------------------- -- Bi-directional port -------------------------------------------- process(Write, ACX_GTE, INP_DAT) begin if (Write = '1' and ACX_GTE = '1') then ACX_DAT <= INP_DAT; else ACX_DAT <= (others => 'Z'); end if; end process; -------------------------------------------- -- 2x32 Latches for input signals (this idea -- doesn't work as a subroutine and has to be -- written for every process separately) -------------------------- -- sector "0", detector "0", -- ring "0", even timeslice -------------------------- process(Tout00(0), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(0) <= '0'; elsif (Tout00(0)'event and Tout00(0) = '0') then Even_L0(0) <= '1'; end if; end process; -------------------------- -- sector "0", detector "0", -- ring "0", odd timeslice -------------------------- process(Tout00(0), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(0) <= '0'; elsif (Tout00(0)'event and Tout00(0) = '0') then Odd_L0(0) <= '1'; end if; end process; -------------------------- -- sector "0", detector "0", -- ring "1", even timeslice -------------------------- process(Tout00(1), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(1) <= '0'; elsif (Tout00(1)'event and Tout00(1) = '0') then Even_L0(1) <= '1'; end if; end process; -------------------------- -- sector "0", detector "0", -- ring "1", odd timeslice -------------------------- process(Tout00(1), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(1) <= '0'; elsif (Tout00(1)'event and Tout00(1) = '0') then Odd_L0(1) <= '1'; end if; end process; -------------------------- -- sector "0", detector "0", -- ring "2", even timeslice -------------------------- process(Tout00(2), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(2) <= '0'; elsif (Tout00(2)'event and Tout00(2) = '0') then Even_L0(2) <= '1'; end if; end process; -------------------------- -- sector "0", detector "0", -- ring "2", odd timeslice -------------------------- process(Tout00(2), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(2) <= '0'; elsif (Tout00(2)'event and Tout00(2) = '0') then Odd_L0(2) <= '1'; end if; end process; -------------------------- -- sector "0", detector "0", -- ring "3", even timeslice -------------------------- process(Tout00(3), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(3) <= '0'; elsif (Tout00(3)'event and Tout00(3) = '0') then Even_L0(3) <= '1'; end if; end process; -------------------------- -- sector "0", detector "0", -- ring "3", odd timeslice -------------------------- process(Tout00(3), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(3) <= '0'; elsif (Tout00(3)'event and Tout00(3) = '0') then Odd_L0(3) <= '1'; end if; end process; -------------------------- -- sector "0", detector "0", -- ring "4", even timeslice -------------------------- process(Tout00(4), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(4) <= '0'; elsif (Tout00(4)'event and Tout00(4) = '0') then Even_L0(4) <= '1'; end if; end process; -------------------------- -- sector "0", detector "0", -- ring "4", odd timeslice -------------------------- process(Tout00(4), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(4) <= '0'; elsif (Tout00(4)'event and Tout00(4) = '0') then Odd_L0(4) <= '1'; end if; end process; -------------------------- -- sector "0", detector "0", -- ring "5", even timeslice -------------------------- process(Tout00(5), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(5) <= '0'; elsif (Tout00(5)'event and Tout00(5) = '0') then Even_L0(5) <= '1'; end if; end process; -------------------------- -- sector "0", detector "0", -- ring "5", odd timeslice -------------------------- process(Tout00(5), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(5) <= '0'; elsif (Tout00(5)'event and Tout00(5) = '0') then Odd_L0(5) <= '1'; end if; end process; -------------------------- -- sector "0", detector "0", -- ring "6", even timeslice -------------------------- process(Tout00(6), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(6) <= '0'; elsif (Tout00(6)'event and Tout00(6) = '0') then Even_L0(6) <= '1'; end if; end process; -------------------------- -- sector "0", detector "0", -- ring "6", odd timeslice -------------------------- process(Tout00(6), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(6) <= '0'; elsif (Tout00(6)'event and Tout00(6) = '0') then Odd_L0(6) <= '1'; end if; end process; -------------------------- -- sector "0", detector "0", -- ring "7", even timeslice -------------------------- process(Tout00(7), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(7) <= '0'; elsif (Tout00(7)'event and Tout00(7) = '0') then Even_L0(7) <= '1'; end if; end process; -------------------------- -- sector "0", detector "0", -- ring "7", odd timeslice -------------------------- process(Tout00(7), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(7) <= '0'; elsif (Tout00(7)'event and Tout00(7) = '0') then Odd_L0(7) <= '1'; end if; end process; -------------------------- -- sector "0", detector "1", -- ring "0", even timeslice -------------------------- process(Tout01(0), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(8) <= '0'; elsif (Tout01(0)'event and Tout01(0) = '0') then Even_L0(8) <= '1'; end if; end process; -------------------------- -- sector "0", detector "1", -- ring "0", odd timeslice -------------------------- process(Tout01(0), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(8) <= '0'; elsif (Tout01(0)'event and Tout01(0) = '0') then Odd_L0(8) <= '1'; end if; end process; -------------------------- -- sector "0", detector "1", -- ring "1", even timeslice -------------------------- process(Tout01(1), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(9) <= '0'; elsif (Tout01(1)'event and Tout01(1) = '0') then Even_L0(9) <= '1'; end if; end process; -------------------------- -- sector "0", detector "1", -- ring "1", odd timeslice -------------------------- process(Tout01(1), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(9) <= '0'; elsif (Tout01(1)'event and Tout01(1) = '0') then Odd_L0(9) <= '1'; end if; end process; -------------------------- -- sector "0", detector "1", -- ring "2", even timeslice -------------------------- process(Tout01(2), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(10) <= '0'; elsif (Tout01(2)'event and Tout01(2) = '0') then Even_L0(10) <= '1'; end if; end process; -------------------------- -- sector "0", detector "1", -- ring "2", odd timeslice -------------------------- process(Tout01(2), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(10) <= '0'; elsif (Tout01(2)'event and Tout01(2) = '0') then Odd_L0(10) <= '1'; end if; end process; -------------------------- -- sector "0", detector "1", -- ring "3", even timeslice -------------------------- process(Tout01(3), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(11) <= '0'; elsif (Tout01(3)'event and Tout01(3) = '0') then Even_L0(11) <= '1'; end if; end process; -------------------------- -- sector "0", detector "1", -- ring "3", odd timeslice -------------------------- process(Tout01(3), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(11) <= '0'; elsif (Tout01(3)'event and Tout01(3) = '0') then Odd_L0(11) <= '1'; end if; end process; -------------------------- -- sector "0", detector "1", -- ring "4", even timeslice -------------------------- process(Tout01(4), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(12) <= '0'; elsif (Tout01(4)'event and Tout01(4) = '0') then Even_L0(12) <= '1'; end if; end process; -------------------------- -- sector "0", detector "1", -- ring "4", odd timeslice -------------------------- process(Tout01(4), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(12) <= '0'; elsif (Tout01(4)'event and Tout01(4) = '0') then Odd_L0(12) <= '1'; end if; end process; -------------------------- -- sector "0", detector "1", -- ring "5", even timeslice -------------------------- process(Tout01(5), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(13) <= '0'; elsif (Tout01(5)'event and Tout01(5) = '0') then Even_L0(13) <= '1'; end if; end process; -------------------------- -- sector "0", detector "1", -- ring "5", odd timeslice -------------------------- process(Tout01(5), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(13) <= '0'; elsif (Tout01(5)'event and Tout01(5) = '0') then Odd_L0(13) <= '1'; end if; end process; -------------------------- -- sector "0", detector "1", -- ring "6", even timeslice -------------------------- process(Tout01(6), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(14) <= '0'; elsif (Tout01(6)'event and Tout01(6) = '0') then Even_L0(14) <= '1'; end if; end process; -------------------------- -- sector "0", detector "1", -- ring "6", odd timeslice -------------------------- process(Tout01(6), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(14) <= '0'; elsif (Tout01(6)'event and Tout01(6) = '0') then Odd_L0(14) <= '1'; end if; end process; -------------------------- -- sector "0", detector "1", -- ring "7", even timeslice -------------------------- process(Tout01(7), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(15) <= '0'; elsif (Tout01(7)'event and Tout01(7) = '0') then Even_L0(15) <= '1'; end if; end process; -------------------------- -- sector "0", detector "1", -- ring "7", odd timeslice -------------------------- process(Tout01(7), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(15) <= '0'; elsif (Tout01(7)'event and Tout01(7) = '0') then Odd_L0(15) <= '1'; end if; end process; -------------------------- -- sector "0", detector "2", -- ring "0", even timeslice -------------------------- process(Tout02(0), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(16) <= '0'; elsif (Tout02(0)'event and Tout02(0) = '0') then Even_L0(16) <= '1'; end if; end process; -------------------------- -- sector "0", detector "2", -- ring "0", odd timeslice -------------------------- process(Tout02(0), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(16) <= '0'; elsif (Tout02(0)'event and Tout02(0) = '0') then Odd_L0(16) <= '1'; end if; end process; -------------------------- -- sector "0", detector "2", -- ring "1", even timeslice -------------------------- process(Tout02(1), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(17) <= '0'; elsif (Tout02(1)'event and Tout02(1) = '0') then Even_L0(17) <= '1'; end if; end process; -------------------------- -- sector "0", detector "2", -- ring "1", odd timeslice -------------------------- process(Tout02(1), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(17) <= '0'; elsif (Tout02(1)'event and Tout02(1) = '0') then Odd_L0(17) <= '1'; end if; end process; -------------------------- -- sector "0", detector "2", -- ring "2", even timeslice -------------------------- process(Tout02(2), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(18) <= '0'; elsif (Tout02(2)'event and Tout02(2) = '0') then Even_L0(18) <= '1'; end if; end process; -------------------------- -- sector "0", detector "2", -- ring "2", odd timeslice -------------------------- process(Tout02(2), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(18) <= '0'; elsif (Tout02(2)'event and Tout02(2) = '0') then Odd_L0(18) <= '1'; end if; end process; -------------------------- -- sector "0", detector "2", -- ring "3", even timeslice -------------------------- process(Tout02(3), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(19) <= '0'; elsif (Tout02(3)'event and Tout02(3) = '0') then Even_L0(19) <= '1'; end if; end process; -------------------------- -- sector "0", detector "2", -- ring "3", odd timeslice -------------------------- process(Tout02(3), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(19) <= '0'; elsif (Tout02(3)'event and Tout02(3) = '0') then Odd_L0(19) <= '1'; end if; end process; -------------------------- -- sector "0", detector "2", -- ring "4", even timeslice -------------------------- process(Tout02(4), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(20) <= '0'; elsif (Tout02(4)'event and Tout02(4) = '0') then Even_L0(20) <= '1'; end if; end process; -------------------------- -- sector "0", detector "2", -- ring "4", odd timeslice -------------------------- process(Tout02(4), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(20) <= '0'; elsif (Tout02(4)'event and Tout02(4) = '0') then Odd_L0(20) <= '1'; end if; end process; -------------------------- -- sector "0", detector "2", -- ring "5", even timeslice -------------------------- process(Tout02(5), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(21) <= '0'; elsif (Tout02(5)'event and Tout02(5) = '0') then Even_L0(21) <= '1'; end if; end process; -------------------------- -- sector "0", detector "2", -- ring "5", odd timeslice -------------------------- process(Tout02(5), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(21) <= '0'; elsif (Tout02(5)'event and Tout02(5) = '0') then Odd_L0(21) <= '1'; end if; end process; -------------------------- -- sector "0", detector "2", -- ring "6", even timeslice -------------------------- process(Tout02(6), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(22) <= '0'; elsif (Tout02(6)'event and Tout02(6) = '0') then Even_L0(22) <= '1'; end if; end process; -------------------------- -- sector "0", detector "2", -- ring "6", odd timeslice -------------------------- process(Tout02(6), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(22) <= '0'; elsif (Tout02(6)'event and Tout02(6) = '0') then Odd_L0(22) <= '1'; end if; end process; -------------------------- -- sector "0", detector "2", -- ring "7", even timeslice -------------------------- process(Tout02(7), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(23) <= '0'; elsif (Tout02(7)'event and Tout02(7) = '0') then Even_L0(23) <= '1'; end if; end process; -------------------------- -- sector "0", detector "2", -- ring "7", odd timeslice -------------------------- process(Tout02(7), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(23) <= '0'; elsif (Tout02(7)'event and Tout02(7) = '0') then Odd_L0(23) <= '1'; end if; end process; -------------------------- -- sector "0", detector "3", -- ring "0", even timeslice -------------------------- process(Tout03(0), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(24) <= '0'; elsif (Tout03(0)'event and Tout03(0) = '0') then Even_L0(24) <= '1'; end if; end process; -------------------------- -- sector "0", detector "3", -- ring "0", odd timeslice -------------------------- process(Tout03(0), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(24) <= '0'; elsif (Tout03(0)'event and Tout03(0) = '0') then Odd_L0(24) <= '1'; end if; end process; -------------------------- -- sector "0", detector "3", -- ring "1", even timeslice -------------------------- process(Tout03(1), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(25) <= '0'; elsif (Tout03(1)'event and Tout03(1) = '0') then Even_L0(25) <= '1'; end if; end process; -------------------------- -- sector "0", detector "3", -- ring "1", odd timeslice -------------------------- process(Tout03(1), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(25) <= '0'; elsif (Tout03(1)'event and Tout03(1) = '0') then Odd_L0(25) <= '1'; end if; end process; -------------------------- -- sector "0", detector "3", -- ring "2", even timeslice -------------------------- process(Tout03(2), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(26) <= '0'; elsif (Tout03(2)'event and Tout03(2) = '0') then Even_L0(26) <= '1'; end if; end process; -------------------------- -- sector "0", detector "3", -- ring "2", odd timeslice -------------------------- process(Tout03(2), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(26) <= '0'; elsif (Tout03(2)'event and Tout03(2) = '0') then Odd_L0(26) <= '1'; end if; end process; -------------------------- -- sector "0", detector "3", -- ring "3", even timeslice -------------------------- process(Tout03(3), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(27) <= '0'; elsif (Tout03(3)'event and Tout03(3) = '0') then Even_L0(27) <= '1'; end if; end process; -------------------------- -- sector "0", detector "3", -- ring "3", odd timeslice -------------------------- process(Tout03(3), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(27) <= '0'; elsif (Tout03(3)'event and Tout03(3) = '0') then Odd_L0(27) <= '1'; end if; end process; -------------------------- -- sector "0", detector "3", -- ring "4", even timeslice -------------------------- process(Tout03(4), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(28) <= '0'; elsif (Tout03(4)'event and Tout03(4) = '0') then Even_L0(28) <= '1'; end if; end process; -------------------------- -- sector "0", detector "3", -- ring "4", odd timeslice -------------------------- process(Tout03(4), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(28) <= '0'; elsif (Tout03(4)'event and Tout03(4) = '0') then Odd_L0(28) <= '1'; end if; end process; -------------------------- -- sector "0", detector "3", -- ring "5", even timeslice -------------------------- process(Tout03(5), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(29) <= '0'; elsif (Tout03(5)'event and Tout03(5) = '0') then Even_L0(29) <= '1'; end if; end process; -------------------------- -- sector "0", detector "3", -- ring "5", odd timeslice -------------------------- process(Tout03(5), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(29) <= '0'; elsif (Tout03(5)'event and Tout03(5) = '0') then Odd_L0(29) <= '1'; end if; end process; -------------------------- -- sector "0", detector "3", -- ring "6", even timeslice -------------------------- process(Tout03(6), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(30) <= '0'; elsif (Tout03(6)'event and Tout03(6) = '0') then Even_L0(30) <= '1'; end if; end process; -------------------------- -- sector "0", detector "3", -- ring "6", odd timeslice -------------------------- process(Tout03(6), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(30) <= '0'; elsif (Tout03(6)'event and Tout03(6) = '0') then Odd_L0(30) <= '1'; end if; end process; -------------------------- -- sector "0", detector "3", -- ring "7", even timeslice -------------------------- process(Tout03(7), CLR_EVE) begin if (CLR_EVE = '1') then Even_L0(31) <= '0'; elsif (Tout03(7)'event and Tout03(7) = '0') then Even_L0(31) <= '1'; end if; end process; -------------------------- -- sector "0", detector "3", -- ring "7", odd timeslice -------------------------- process(Tout03(7), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L0(31) <= '0'; elsif (Tout03(7)'event and Tout03(7) = '0') then Odd_L0(31) <= '1'; end if; end process; -------------------------- -- sector "1", detector "0", -- ring "0", even timeslice -------------------------- process(Tout10(0), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(0) <= '0'; elsif (Tout10(0)'event and Tout10(0) = '0') then Even_L1(0) <= '1'; end if; end process; -------------------------- -- sector "1", detector "0", -- ring "0", odd timeslice -------------------------- process(Tout10(0), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(0) <= '0'; elsif (Tout10(0)'event and Tout10(0) = '0') then Odd_L1(0) <= '1'; end if; end process; -------------------------- -- sector "1", detector "0", -- ring "1", even timeslice -------------------------- process(Tout10(1), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(1) <= '0'; elsif (Tout10(1)'event and Tout10(1) = '0') then Even_L1(1) <= '1'; end if; end process; -------------------------- -- sector "1", detector "0", -- ring "1", odd timeslice -------------------------- process(Tout10(1), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(1) <= '0'; elsif (Tout10(1)'event and Tout10(1) = '0') then Odd_L1(1) <= '1'; end if; end process; -------------------------- -- sector "1", detector "0", -- ring "2", even timeslice -------------------------- process(Tout10(2), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(2) <= '0'; elsif (Tout10(2)'event and Tout10(2) = '0') then Even_L1(2) <= '1'; end if; end process; -------------------------- -- sector "1", detector "0", -- ring "2", odd timeslice -------------------------- process(Tout10(2), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(2) <= '0'; elsif (Tout10(2)'event and Tout10(2) = '0') then Odd_L1(2) <= '1'; end if; end process; -------------------------- -- sector "1", detector "0", -- ring "3", even timeslice -------------------------- process(Tout10(3), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(3) <= '0'; elsif (Tout10(3)'event and Tout10(3) = '0') then Even_L1(3) <= '1'; end if; end process; -------------------------- -- sector "1", detector "0", -- ring "3", odd timeslice -------------------------- process(Tout10(3), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(3) <= '0'; elsif (Tout10(3)'event and Tout10(3) = '0') then Odd_L1(3) <= '1'; end if; end process; -------------------------- -- sector "1", detector "0", -- ring "4", even timeslice -------------------------- process(Tout10(4), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(4) <= '0'; elsif (Tout10(4)'event and Tout10(4) = '0') then Even_L1(4) <= '1'; end if; end process; -------------------------- -- sector "1", detector "0", -- ring "4", odd timeslice -------------------------- process(Tout10(4), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(4) <= '0'; elsif (Tout10(4)'event and Tout10(4) = '0') then Odd_L1(4) <= '1'; end if; end process; -------------------------- -- sector "1", detector "0", -- ring "5", even timeslice -------------------------- process(Tout10(5), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(5) <= '0'; elsif (Tout10(5)'event and Tout10(5) = '0') then Even_L1(5) <= '1'; end if; end process; -------------------------- -- sector "1", detector "0", -- ring "5", odd timeslice -------------------------- process(Tout10(5), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(5) <= '0'; elsif (Tout10(5)'event and Tout10(5) = '0') then Odd_L1(5) <= '1'; end if; end process; -------------------------- -- sector "1", detector "0", -- ring "6", even timeslice -------------------------- process(Tout10(6), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(6) <= '0'; elsif (Tout10(6)'event and Tout10(6) = '0') then Even_L1(6) <= '1'; end if; end process; -------------------------- -- sector "1", detector "0", -- ring "6", odd timeslice -------------------------- process(Tout10(6), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(6) <= '0'; elsif (Tout10(6)'event and Tout10(6) = '0') then Odd_L1(6) <= '1'; end if; end process; -------------------------- -- sector "1", detector "0", -- ring "7", even timeslice -------------------------- process(Tout10(7), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(7) <= '0'; elsif (Tout10(7)'event and Tout10(7) = '0') then Even_L1(7) <= '1'; end if; end process; -------------------------- -- sector "1", detector "0", -- ring "7", odd timeslice -------------------------- process(Tout10(7), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(7) <= '0'; elsif (Tout10(7)'event and Tout10(7) = '0') then Odd_L1(7) <= '1'; end if; end process; -------------------------- -- sector "1", detector "1", -- ring "0", even timeslice -------------------------- process(Tout11(0), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(8) <= '0'; elsif (Tout11(0)'event and Tout11(0) = '0') then Even_L1(8) <= '1'; end if; end process; -------------------------- -- sector "1", detector "1", -- ring "0", odd timeslice -------------------------- process(Tout11(0), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(8) <= '0'; elsif (Tout11(0)'event and Tout11(0) = '0') then Odd_L1(8) <= '1'; end if; end process; -------------------------- -- sector "1", detector "1", -- ring "1", even timeslice -------------------------- process(Tout11(1), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(9) <= '0'; elsif (Tout11(1)'event and Tout11(1) = '0') then Even_L1(9) <= '1'; end if; end process; -------------------------- -- sector "1", detector "1", -- ring "1", odd timeslice -------------------------- process(Tout11(1), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(9) <= '0'; elsif (Tout11(1)'event and Tout11(1) = '0') then Odd_L1(9) <= '1'; end if; end process; -------------------------- -- sector "1", detector "1", -- ring "2", even timeslice -------------------------- process(Tout11(2), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(10) <= '0'; elsif (Tout11(2)'event and Tout11(2) = '0') then Even_L1(10) <= '1'; end if; end process; -------------------------- -- sector "1", detector "1", -- ring "2", odd timeslice -------------------------- process(Tout11(2), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(10) <= '0'; elsif (Tout11(2)'event and Tout11(2) = '0') then Odd_L1(10) <= '1'; end if; end process; -------------------------- -- sector "1", detector "1", -- ring "3", even timeslice -------------------------- process(Tout11(3), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(11) <= '0'; elsif (Tout11(3)'event and Tout11(3) = '0') then Even_L1(11) <= '1'; end if; end process; -------------------------- -- sector "1", detector "1", -- ring "3", odd timeslice -------------------------- process(Tout11(3), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(11) <= '0'; elsif (Tout11(3)'event and Tout11(3) = '0') then Odd_L1(11) <= '1'; end if; end process; -------------------------- -- sector "1", detector "1", -- ring "4", even timeslice -------------------------- process(Tout11(4), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(12) <= '0'; elsif (Tout11(4)'event and Tout11(4) = '0') then Even_L1(12) <= '1'; end if; end process; -------------------------- -- sector "1", detector "1", -- ring "4", odd timeslice -------------------------- process(Tout11(4), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(12) <= '0'; elsif (Tout11(4)'event and Tout11(4) = '0') then Odd_L1(12) <= '1'; end if; end process; -------------------------- -- sector "1", detector "1", -- ring "5", even timeslice -------------------------- process(Tout11(5), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(13) <= '0'; elsif (Tout11(5)'event and Tout11(5) = '0') then Even_L1(13) <= '1'; end if; end process; -------------------------- -- sector "1", detector "1", -- ring "5", odd timeslice -------------------------- process(Tout11(5), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(13) <= '0'; elsif (Tout11(5)'event and Tout11(5) = '0') then Odd_L1(13) <= '1'; end if; end process; -------------------------- -- sector "1", detector "1", -- ring "6", even timeslice -------------------------- process(Tout11(6), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(14) <= '0'; elsif (Tout11(6)'event and Tout11(6) = '0') then Even_L1(14) <= '1'; end if; end process; -------------------------- -- sector "1", detector "1", -- ring "6", odd timeslice -------------------------- process(Tout11(6), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(14) <= '0'; elsif (Tout11(6)'event and Tout11(6) = '0') then Odd_L1(14) <= '1'; end if; end process; -------------------------- -- sector "1", detector "1", -- ring "7", even timeslice -------------------------- process(Tout11(7), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(15) <= '0'; elsif (Tout11(7)'event and Tout11(7) = '0') then Even_L1(15) <= '1'; end if; end process; -------------------------- -- sector "1", detector "1", -- ring "7", odd timeslice -------------------------- process(Tout11(7), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(15) <= '0'; elsif (Tout11(7)'event and Tout11(7) = '0') then Odd_L1(15) <= '1'; end if; end process; -------------------------- -- sector "1", detector "2", -- ring "0", even timeslice -------------------------- process(Tout12(0), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(16) <= '0'; elsif (Tout12(0)'event and Tout12(0) = '0') then Even_L1(16) <= '1'; end if; end process; -------------------------- -- sector "1", detector "2", -- ring "0", odd timeslice -------------------------- process(Tout12(0), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(16) <= '0'; elsif (Tout12(0)'event and Tout12(0) = '0') then Odd_L1(16) <= '1'; end if; end process; -------------------------- -- sector "1", detector "2", -- ring "1", even timeslice -------------------------- process(Tout12(1), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(17) <= '0'; elsif (Tout12(1)'event and Tout12(1) = '0') then Even_L1(17) <= '1'; end if; end process; -------------------------- -- sector "1", detector "2", -- ring "1", odd timeslice -------------------------- process(Tout12(1), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(17) <= '0'; elsif (Tout12(1)'event and Tout12(1) = '0') then Odd_L1(17) <= '1'; end if; end process; -------------------------- -- sector "1", detector "2", -- ring "2", even timeslice -------------------------- process(Tout12(2), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(18) <= '0'; elsif (Tout12(2)'event and Tout12(2) = '0') then Even_L1(18) <= '1'; end if; end process; -------------------------- -- sector "1", detector "2", -- ring "2", odd timeslice -------------------------- process(Tout12(2), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(18) <= '0'; elsif (Tout12(2)'event and Tout12(2) = '0') then Odd_L1(18) <= '1'; end if; end process; -------------------------- -- sector "1", detector "2", -- ring "3", even timeslice -------------------------- process(Tout12(3), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(19) <= '0'; elsif (Tout12(3)'event and Tout12(3) = '0') then Even_L1(19) <= '1'; end if; end process; -------------------------- -- sector "1", detector "2", -- ring "3", odd timeslice -------------------------- process(Tout12(3), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(19) <= '0'; elsif (Tout12(3)'event and Tout12(3) = '0') then Odd_L1(19) <= '1'; end if; end process; -------------------------- -- sector "1", detector "2", -- ring "4", even timeslice -------------------------- process(Tout12(4), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(20) <= '0'; elsif (Tout12(4)'event and Tout12(4) = '0') then Even_L1(20) <= '1'; end if; end process; -------------------------- -- sector "1", detector "2", -- ring "4", odd timeslice -------------------------- process(Tout12(4), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(20) <= '0'; elsif (Tout12(4)'event and Tout12(4) = '0') then Odd_L1(20) <= '1'; end if; end process; -------------------------- -- sector "1", detector "2", -- ring "5", even timeslice -------------------------- process(Tout12(5), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(21) <= '0'; elsif (Tout12(5)'event and Tout12(5) = '0') then Even_L1(21) <= '1'; end if; end process; -------------------------- -- sector "1", detector "2", -- ring "5", odd timeslice -------------------------- process(Tout12(5), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(21) <= '0'; elsif (Tout12(5)'event and Tout12(5) = '0') then Odd_L1(21) <= '1'; end if; end process; -------------------------- -- sector "1", detector "2", -- ring "6", even timeslice -------------------------- process(Tout12(6), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(22) <= '0'; elsif (Tout12(6)'event and Tout12(6) = '0') then Even_L1(22) <= '1'; end if; end process; -------------------------- -- sector "1", detector "2", -- ring "6", odd timeslice -------------------------- process(Tout12(6), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(22) <= '0'; elsif (Tout12(6)'event and Tout12(6) = '0') then Odd_L1(22) <= '1'; end if; end process; -------------------------- -- sector "1", detector "2", -- ring "7", even timeslice -------------------------- process(Tout12(7), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(23) <= '0'; elsif (Tout12(7)'event and Tout12(7) = '0') then Even_L1(23) <= '1'; end if; end process; -------------------------- -- sector "1", detector "2", -- ring "7", odd timeslice -------------------------- process(Tout12(7), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(23) <= '0'; elsif (Tout12(7)'event and Tout12(7) = '0') then Odd_L1(23) <= '1'; end if; end process; -------------------------- -- sector "1", detector "3", -- ring "0", even timeslice -------------------------- process(Tout13(0), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(24) <= '0'; elsif (Tout13(0)'event and Tout13(0) = '0') then Even_L1(24) <= '1'; end if; end process; -------------------------- -- sector "1", detector "3", -- ring "0", odd timeslice -------------------------- process(Tout13(0), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(24) <= '0'; elsif (Tout13(0)'event and Tout13(0) = '0') then Odd_L1(24) <= '1'; end if; end process; -------------------------- -- sector "1", detector "3", -- ring "1", even timeslice -------------------------- process(Tout13(1), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(25) <= '0'; elsif (Tout13(1)'event and Tout13(1) = '0') then Even_L1(25) <= '1'; end if; end process; -------------------------- -- sector "1", detector "3", -- ring "1", odd timeslice -------------------------- process(Tout13(1), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(25) <= '0'; elsif (Tout13(1)'event and Tout13(1) = '0') then Odd_L1(25) <= '1'; end if; end process; -------------------------- -- sector "1", detector "3", -- ring "2", even timeslice -------------------------- process(Tout13(2), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(26) <= '0'; elsif (Tout13(2)'event and Tout13(2) = '0') then Even_L1(26) <= '1'; end if; end process; -------------------------- -- sector "1", detector "3", -- ring "2", odd timeslice -------------------------- process(Tout13(2), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(26) <= '0'; elsif (Tout13(2)'event and Tout13(2) = '0') then Odd_L1(26) <= '1'; end if; end process; -------------------------- -- sector "1", detector "3", -- ring "3", even timeslice -------------------------- process(Tout13(3), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(27) <= '0'; elsif (Tout13(3)'event and Tout13(3) = '0') then Even_L1(27) <= '1'; end if; end process; -------------------------- -- sector "1", detector "3", -- ring "3", odd timeslice -------------------------- process(Tout13(3), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(27) <= '0'; elsif (Tout13(3)'event and Tout13(3) = '0') then Odd_L1(27) <= '1'; end if; end process; -------------------------- -- sector "1", detector "3", -- ring "4", even timeslice -------------------------- process(Tout13(4), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(28) <= '0'; elsif (Tout13(4)'event and Tout13(4) = '0') then Even_L1(28) <= '1'; end if; end process; -------------------------- -- sector "1", detector "3", -- ring "4", odd timeslice -------------------------- process(Tout13(4), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(28) <= '0'; elsif (Tout13(4)'event and Tout13(4) = '0') then Odd_L1(28) <= '1'; end if; end process; -------------------------- -- sector "1", detector "3", -- ring "5", even timeslice -------------------------- process(Tout13(5), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(29) <= '0'; elsif (Tout13(5)'event and Tout13(5) = '0') then Even_L1(29) <= '1'; end if; end process; -------------------------- -- sector "1", detector "3", -- ring "5", odd timeslice -------------------------- process(Tout13(5), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(29) <= '0'; elsif (Tout13(5)'event and Tout13(5) = '0') then Odd_L1(29) <= '1'; end if; end process; -------------------------- -- sector "1", detector "3", -- ring "6", even timeslice -------------------------- process(Tout13(6), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(30) <= '0'; elsif (Tout13(6)'event and Tout13(6) = '0') then Even_L1(30) <= '1'; end if; end process; -------------------------- -- sector "1", detector "3", -- ring "6", odd timeslice -------------------------- process(Tout13(6), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(30) <= '0'; elsif (Tout13(6)'event and Tout13(6) = '0') then Odd_L1(30) <= '1'; end if; end process; -------------------------- -- sector "1", detector "3", -- ring "7", even timeslice -------------------------- process(Tout13(7), CLR_EVE) begin if (CLR_EVE = '1') then Even_L1(31) <= '0'; elsif (Tout13(7)'event and Tout13(7) = '0') then Even_L1(31) <= '1'; end if; end process; -------------------------- -- sector "1", detector "3", -- ring "7", odd timeslice -------------------------- process(Tout13(7), CLR_ODD) begin if (CLR_ODD = '1') then Odd_L1(31) <= '0'; elsif (Tout13(7)'event and Tout13(7) = '0') then Odd_L1(31) <= '1'; end if; end process; -------------------------------------------- -- Time slice counter -------------------------------------------- process(Clock) begin if (Clock'event and Clock = '0') then TMP_CNT <= TMP_CNT + 1; end if; end process; -------------------------- process(Clock, TMP_CNT) begin if (Clock'event and Clock ='1') then TMP_DEL <= TMP_CNT; end if; end process; -------------------------------------------- -- Merge data from even and odd -- clock periods (Clock ->) -------------------------------------------- process(Clock, TMP_CNT, Even_L0, Even_L1, Odd_L0, Odd_L1) begin if (Clock'event and Clock = '1') then if (TMP_CNT = 1) then Tdata0 <= Even_L0; Tdata1 <= Even_L1; else Tdata0 <= Odd_L0; Tdata1 <= Odd_L1; end if; end if; end process; -------------------------------------------- -- Clear even time slice (Clock <-) -------------------------------------------- process(TMP_DEL, Clock) begin if (TMP_DEL = 0) then CLR_EVE <= '0'; elsif (Clock'event and Clock = '0') then CLR_EVE <= '1'; end if; end process; -------------------------------------------- -- Clear odd time slice (Clock <-) -------------------------------------------- process(TMP_DEL, Clock) begin if (TMP_DEL = 1) then CLR_ODD <= '0'; elsif (Clock'event and Clock = '0') then CLR_ODD <= '1'; end if; end process; -------------------------------------------- -- Trigger combinatorics -------------------------------------------- -- soft masks for sector 0 -------------------------- Mask0(0) <= Tdata0(25) and Tdata0(16) and Tdata0(8); Mask0(3) <= Tdata0(26) and Tdata0(17) and Tdata0(8); Mask0(6) <= Tdata0(28) and Tdata0(19) and Tdata0(10) and Tdata0(1); Mask0(7) <= Tdata0(28) and Tdata0(10) and Tdata0(1); Mask0(8) <= Tdata0(28) and Tdata0(19) and Tdata0(1); Mask0(10) <= Tdata0(19) and Tdata0(10) and Tdata0(1); Mask0(12) <= Tdata0(28) and Tdata0(19) and Tdata0(10); Mask0(17) <= Tdata0(26) and Tdata0(17) and Tdata0(8) and Tdata0(0); Mask0(18) <= Tdata0(17) and Tdata0(8) and Tdata0(0); Mask0(19) <= Tdata0(26) and Tdata0(18) and Tdata0(9) and Tdata0(0); Mask0(20) <= Tdata0(26) and Tdata0(18) and Tdata0(9); Mask0(21) <= Tdata0(26) and Tdata0(8) and Tdata0(0); Mask0(23) <= Tdata0(26) and Tdata0(18) and Tdata0(0); Mask0(26) <= Tdata0(26) and Tdata0(17) and Tdata0(0); Mask0(28) <= Tdata0(26) and Tdata0(9) and Tdata0(0); Mask0(30) <= Tdata0(27) and Tdata0(17) and Tdata0(8); Mask0(33) <= Tdata0(27) and Tdata0(18) and Tdata0(8); Mask0(35) <= Tdata0(26) and Tdata0(17) and Tdata0(9) and Tdata0(0); Mask0(36) <= Tdata0(26) and Tdata0(17) and Tdata0(9); Mask0(37) <= Tdata0(17) and Tdata0(9) and Tdata0(0); Mask0(41) <= Tdata0(18) and Tdata0(9) and Tdata0(0); Mask0(43) <= Tdata0(27) and Tdata0(18) and Tdata0(0); Mask0(44) <= Tdata0(27) and Tdata0(18) and Tdata0(9) and Tdata0(0); Mask0(45) <= Tdata0(27) and Tdata0(9) and Tdata0(0); Mask0(48) <= Tdata0(27) and Tdata0(18) and Tdata0(9); Mask0(51) <= Tdata0(27) and Tdata0(18) and Tdata0(1); Mask0(52) <= Tdata0(27) and Tdata0(10) and Tdata0(1); Mask0(54) <= Tdata0(27) and Tdata0(18) and Tdata0(9) and Tdata0(1); Mask0(55) <= Tdata0(18) and Tdata0(9) and Tdata0(1); Mask0(57) <= Tdata0(27) and Tdata0(9) and Tdata0(1); Mask0(58) <= Tdata0(27) and Tdata0(19) and Tdata0(10) and Tdata0(1); Mask0(59) <= Tdata0(27) and Tdata0(19) and Tdata0(10); Mask0(61) <= Tdata0(27) and Tdata0(19) and Tdata0(1); Mask0(63) <= Tdata0(31) and Tdata0(22) and Tdata0(12) and Tdata0(3); Mask0(64) <= Tdata0(22) and Tdata0(12) and Tdata0(3); Mask0(66) <= Tdata0(31) and Tdata0(22) and Tdata0(3); Mask0(67) <= Tdata0(31) and Tdata0(23) and Tdata0(14) and Tdata0(5); Mask0(68) <= Tdata0(31) and Tdata0(23) and Tdata0(14); Mask0(69) <= Tdata0(31) and Tdata0(23) and Tdata0(5); Mask0(72) <= Tdata0(28) and Tdata0(19) and Tdata0(2); Mask0(74) <= Tdata0(28) and Tdata0(11) and Tdata0(2); Mask0(77) <= Tdata0(28) and Tdata0(19) and Tdata0(10) and Tdata0(2); Mask0(78) <= Tdata0(28) and Tdata0(10) and Tdata0(2); Mask0(79) <= Tdata0(19) and Tdata0(10) and Tdata0(2); Mask0(82) <= Tdata0(20) and Tdata0(11) and Tdata0(2); Mask0(85) <= Tdata0(31) and Tdata0(12) and Tdata0(3); Mask0(88) <= Tdata0(29) and Tdata0(10) and Tdata0(1); Mask0(89) <= Tdata0(31) and Tdata0(22) and Tdata0(12); Mask0(91) <= Tdata0(29) and Tdata0(20) and Tdata0(11); Mask0(94) <= Tdata0(29) and Tdata0(20) and Tdata0(11) and Tdata0(2); Mask0(95) <= Tdata0(29) and Tdata0(11) and Tdata0(2); Mask0(96) <= Tdata0(29) and Tdata0(20) and Tdata0(2); Mask0(99) <= Tdata0(29) and Tdata0(20) and Tdata0(1); Mask0(100) <= Tdata0(29) and Tdata0(20) and Tdata0(10); Mask0(103) <= Tdata0(31) and Tdata0(14) and Tdata0(5); Mask0(104) <= Tdata0(29) and Tdata0(20) and Tdata0(3); Mask0(105) <= Tdata0(29) and Tdata0(12) and Tdata0(3); Mask0(108) <= Tdata0(29) and Tdata0(20) and Tdata0(11) and Tdata0(3); Mask0(109) <= Tdata0(29) and Tdata0(11) and Tdata0(3); Mask0(110) <= Tdata0(20) and Tdata0(11) and Tdata0(3); Mask0(111) <= Tdata0(29) and Tdata0(21) and Tdata0(12) and Tdata0(3); Mask0(112) <= Tdata0(29) and Tdata0(21) and Tdata0(12); Mask0(113) <= Tdata0(29) and Tdata0(21) and Tdata0(3); Mask0(118) <= Tdata0(21) and Tdata0(12) and Tdata0(3); Mask0(121) <= Tdata0(30) and Tdata0(21) and Tdata0(3); Mask0(122) <= Tdata0(30) and Tdata0(12) and Tdata0(3); Mask0(123) <= Tdata0(30) and Tdata0(21) and Tdata0(12) and Tdata0(3); Mask0(125) <= Tdata0(30) and Tdata0(21) and Tdata0(12); Mask0(129) <= Tdata0(30) and Tdata0(13) and Tdata0(4); Mask0(131) <= Tdata0(30) and Tdata0(21) and Tdata0(4); Mask0(134) <= Tdata0(30) and Tdata0(21) and Tdata0(12) and Tdata0(4); Mask0(135) <= Tdata0(21) and Tdata0(12) and Tdata0(4); Mask0(136) <= Tdata0(30) and Tdata0(12) and Tdata0(4); Mask0(141) <= Tdata0(22) and Tdata0(13) and Tdata0(4); Mask0(142) <= Tdata0(31) and Tdata0(22) and Tdata0(4); Mask0(144) <= Tdata0(31) and Tdata0(13) and Tdata0(4); Mask0(145) <= Tdata0(31) and Tdata0(22) and Tdata0(13) and Tdata0(4); Mask0(147) <= Tdata0(31) and Tdata0(22) and Tdata0(13); Mask0(149) <= Tdata0(22) and Tdata0(13) and Tdata0(5); Mask0(152) <= Tdata0(31) and Tdata0(22) and Tdata0(13) and Tdata0(5); Mask0(153) <= Tdata0(31) and Tdata0(13) and Tdata0(5); Mask0(154) <= Tdata0(31) and Tdata0(22) and Tdata0(5); Mask0(158) <= Tdata0(23) and Tdata0(13) and Tdata0(4); Mask0(161) <= Tdata0(23) and Tdata0(14) and Tdata0(5); Mask0(163) <= Tdata0(23) and Tdata0(15) and Tdata0(6); Mask0(168) <= Tdata0(23) and Tdata0(14) and Tdata0(6); Mask0(169) <= Tdata0(20) and Tdata0(12) and Tdata0(3); Mask0(173) <= Tdata0(25) and Tdata0(17) and Tdata0(8); -- soft masks for sector 1 -------------------------- Mask1(0) <= Tdata1(25) and Tdata1(16) and Tdata1(8); Mask1(3) <= Tdata1(26) and Tdata1(17) and Tdata1(8); Mask1(6) <= Tdata1(28) and Tdata1(19) and Tdata1(10) and Tdata1(1); Mask1(7) <= Tdata1(28) and Tdata1(10) and Tdata1(1); Mask1(8) <= Tdata1(28) and Tdata1(19) and Tdata1(1); Mask1(10) <= Tdata1(19) and Tdata1(10) and Tdata1(1); Mask1(12) <= Tdata1(28) and Tdata1(19) and Tdata1(10); Mask1(17) <= Tdata1(26) and Tdata1(17) and Tdata1(8) and Tdata1(0); Mask1(18) <= Tdata1(17) and Tdata1(8) and Tdata1(0); Mask1(19) <= Tdata1(26) and Tdata1(18) and Tdata1(9) and Tdata1(0); Mask1(20) <= Tdata1(26) and Tdata1(18) and Tdata1(9); Mask1(21) <= Tdata1(26) and Tdata1(8) and Tdata1(0); Mask1(23) <= Tdata1(26) and Tdata1(18) and Tdata1(0); Mask1(26) <= Tdata1(26) and Tdata1(17) and Tdata1(0); Mask1(28) <= Tdata1(26) and Tdata1(9) and Tdata1(0); Mask1(30) <= Tdata1(27) and Tdata1(17) and Tdata1(8); Mask1(33) <= Tdata1(27) and Tdata1(18) and Tdata1(8); Mask1(35) <= Tdata1(26) and Tdata1(17) and Tdata1(9) and Tdata1(0); Mask1(36) <= Tdata1(26) and Tdata1(17) and Tdata1(9); Mask1(37) <= Tdata1(17) and Tdata1(9) and Tdata1(0); Mask1(41) <= Tdata1(18) and Tdata1(9) and Tdata1(0); Mask1(43) <= Tdata1(27) and Tdata1(18) and Tdata1(0); Mask1(44) <= Tdata1(27) and Tdata1(18) and Tdata1(9) and Tdata1(0); Mask1(45) <= Tdata1(27) and Tdata1(9) and Tdata1(0); Mask1(48) <= Tdata1(27) and Tdata1(18) and Tdata1(9); Mask1(51) <= Tdata1(27) and Tdata1(18) and Tdata1(1); Mask1(52) <= Tdata1(27) and Tdata1(10) and Tdata1(1); Mask1(54) <= Tdata1(27) and Tdata1(18) and Tdata1(9) and Tdata1(1); Mask1(55) <= Tdata1(18) and Tdata1(9) and Tdata1(1); Mask1(57) <= Tdata1(27) and Tdata1(9) and Tdata1(1); Mask1(58) <= Tdata1(27) and Tdata1(19) and Tdata1(10) and Tdata1(1); Mask1(59) <= Tdata1(27) and Tdata1(19) and Tdata1(10); Mask1(61) <= Tdata1(27) and Tdata1(19) and Tdata1(1); Mask1(63) <= Tdata1(31) and Tdata1(22) and Tdata1(12) and Tdata1(3); Mask1(64) <= Tdata1(22) and Tdata1(12) and Tdata1(3); Mask1(66) <= Tdata1(31) and Tdata1(22) and Tdata1(3); Mask1(67) <= Tdata1(31) and Tdata1(23) and Tdata1(14) and Tdata1(5); Mask1(68) <= Tdata1(31) and Tdata1(23) and Tdata1(14); Mask1(69) <= Tdata1(31) and Tdata1(23) and Tdata1(5); Mask1(72) <= Tdata1(28) and Tdata1(19) and Tdata1(2); Mask1(74) <= Tdata1(28) and Tdata1(11) and Tdata1(2); Mask1(77) <= Tdata1(28) and Tdata1(19) and Tdata1(10) and Tdata1(2); Mask1(78) <= Tdata1(28) and Tdata1(10) and Tdata1(2); Mask1(79) <= Tdata1(19) and Tdata1(10) and Tdata1(2); Mask1(82) <= Tdata1(20) and Tdata1(11) and Tdata1(2); Mask1(85) <= Tdata1(31) and Tdata1(12) and Tdata1(3); Mask1(88) <= Tdata1(29) and Tdata1(10) and Tdata1(1); Mask1(89) <= Tdata1(31) and Tdata1(22) and Tdata1(12); Mask1(91) <= Tdata1(29) and Tdata1(20) and Tdata1(11); Mask1(94) <= Tdata1(29) and Tdata1(20) and Tdata1(11) and Tdata1(2); Mask1(95) <= Tdata1(29) and Tdata1(11) and Tdata1(2); Mask1(96) <= Tdata1(29) and Tdata1(20) and Tdata1(2); Mask1(99) <= Tdata1(29) and Tdata1(20) and Tdata1(1); Mask1(100) <= Tdata1(29) and Tdata1(20) and Tdata1(10); Mask1(103) <= Tdata1(31) and Tdata1(14) and Tdata1(5); Mask1(104) <= Tdata1(29) and Tdata1(20) and Tdata1(3); Mask1(105) <= Tdata1(29) and Tdata1(12) and Tdata1(3); Mask1(108) <= Tdata1(29) and Tdata1(20) and Tdata1(11) and Tdata1(3); Mask1(109) <= Tdata1(29) and Tdata1(11) and Tdata1(3); Mask1(110) <= Tdata1(20) and Tdata1(11) and Tdata1(3); Mask1(111) <= Tdata1(29) and Tdata1(21) and Tdata1(12) and Tdata1(3); Mask1(112) <= Tdata1(29) and Tdata1(21) and Tdata1(12); Mask1(113) <= Tdata1(29) and Tdata1(21) and Tdata1(3); Mask1(118) <= Tdata1(21) and Tdata1(12) and Tdata1(3); Mask1(121) <= Tdata1(30) and Tdata1(21) and Tdata1(3); Mask1(122) <= Tdata1(30) and Tdata1(12) and Tdata1(3); Mask1(123) <= Tdata1(30) and Tdata1(21) and Tdata1(12) and Tdata1(3); Mask1(125) <= Tdata1(30) and Tdata1(21) and Tdata1(12); Mask1(129) <= Tdata1(30) and Tdata1(13) and Tdata1(4); Mask1(131) <= Tdata1(30) and Tdata1(21) and Tdata1(4); Mask1(134) <= Tdata1(30) and Tdata1(21) and Tdata1(12) and Tdata1(4); Mask1(135) <= Tdata1(21) and Tdata1(12) and Tdata1(4); Mask1(136) <= Tdata1(30) and Tdata1(12) and Tdata1(4); Mask1(141) <= Tdata1(22) and Tdata1(13) and Tdata1(4); Mask1(142) <= Tdata1(31) and Tdata1(22) and Tdata1(4); Mask1(144) <= Tdata1(31) and Tdata1(13) and Tdata1(4); Mask1(145) <= Tdata1(31) and Tdata1(22) and Tdata1(13) and Tdata1(4); Mask1(147) <= Tdata1(31) and Tdata1(22) and Tdata1(13); Mask1(149) <= Tdata1(22) and Tdata1(13) and Tdata1(5); Mask1(152) <= Tdata1(31) and Tdata1(22) and Tdata1(13) and Tdata1(5); Mask1(153) <= Tdata1(31) and Tdata1(13) and Tdata1(5); Mask1(154) <= Tdata1(31) and Tdata1(22) and Tdata1(5); Mask1(158) <= Tdata1(23) and Tdata1(13) and Tdata1(4); Mask1(161) <= Tdata1(23) and Tdata1(14) and Tdata1(5); Mask1(163) <= Tdata1(23) and Tdata1(15) and Tdata1(6); Mask1(168) <= Tdata1(23) and Tdata1(14) and Tdata1(6); Mask1(169) <= Tdata1(20) and Tdata1(12) and Tdata1(3); Mask1(173) <= Tdata1(25) and Tdata1(17) and Tdata1(8); -- firm masks for sector 0 -------------------------- Mask0(1) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(2) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(4) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(5) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(9) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and Tdata0(1) and not Tdata0(0); Mask0(11) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and Tdata0(1) and not Tdata0(0); Mask0(13) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(14) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(15) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and Tdata0(1) and not Tdata0(0); Mask0(16) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(22) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and Tdata0(0); Mask0(24) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(25) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and Tdata0(0); Mask0(27) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and Tdata0(0); Mask0(29) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(31) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(32) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(34) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(38) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(39) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and Tdata0(0); Mask0(40) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and Tdata0(0); Mask0(42) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and Tdata0(0); Mask0(46) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(47) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(49) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(50) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and Tdata0(1) and not Tdata0(0); Mask0(53) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(56) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and Tdata0(1) and not Tdata0(0); Mask0(60) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and Tdata0(1) and not Tdata0(0); Mask0(62) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(65) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(70) <= Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(71) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(73) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(75) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(76) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(80) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(81) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(83) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(84) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(86) <= Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(87) <= not Tdata0(31) and not Tdata0(30) and Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and Tdata0(1) and not Tdata0(0); Mask0(90) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(92) <= not Tdata0(31) and not Tdata0(30) and Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(93) <= not Tdata0(31) and not Tdata0(30) and Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(97) <= not Tdata0(31) and not Tdata0(30) and Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(98) <= not Tdata0(31) and not Tdata0(30) and Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(101) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(102) <= Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(106) <= not Tdata0(31) and not Tdata0(30) and Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(107) <= not Tdata0(31) and not Tdata0(30) and Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(114) <= not Tdata0(31) and not Tdata0(30) and Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(115) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(116) <= Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(117) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(119) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(120) <= not Tdata0(31) and Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(124) <= not Tdata0(31) and Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(126) <= not Tdata0(31) and Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(127) <= Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(128) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(130) <= not Tdata0(31) and Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(132) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(133) <= not Tdata0(31) and Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(137) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(138) <= Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(139) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(140) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(143) <= Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(146) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(148) <= Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(150) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(151) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(155) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(156) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(157) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(159) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(160) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(162) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(164) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(165) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(166) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(167) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(170) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and not Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(171) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and not Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); Mask0(172) <= not Tdata0(31) and not Tdata0(30) and not Tdata0(29) and not Tdata0(28) and not Tdata0(27) and not Tdata0(26) and Tdata0(25) and not Tdata0(24) and not Tdata0(23) and not Tdata0(22) and not Tdata0(21) and not Tdata0(20) and not Tdata0(19) and not Tdata0(18) and Tdata0(17) and not Tdata0(16) and not Tdata0(15) and not Tdata0(14) and not Tdata0(13) and not Tdata0(12) and not Tdata0(11) and not Tdata0(10) and not Tdata0(9) and not Tdata0(8) and not Tdata0(7) and not Tdata0(6) and not Tdata0(5) and not Tdata0(4) and not Tdata0(3) and not Tdata0(2) and not Tdata0(1) and not Tdata0(0); -- firm masks for sector 1 -------------------------- Mask1(1) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(2) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(4) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(5) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(9) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and Tdata1(1) and not Tdata1(0); Mask1(11) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and Tdata1(1) and not Tdata1(0); Mask1(13) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(14) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(15) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and Tdata1(1) and not Tdata1(0); Mask1(16) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(22) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and Tdata1(0); Mask1(24) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(25) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and Tdata1(0); Mask1(27) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and Tdata1(0); Mask1(29) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(31) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(32) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(34) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(38) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(39) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and Tdata1(0); Mask1(40) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and Tdata1(0); Mask1(42) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and Tdata1(0); Mask1(46) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(47) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(49) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(50) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and Tdata1(1) and not Tdata1(0); Mask1(53) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(56) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and Tdata1(1) and not Tdata1(0); Mask1(60) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and Tdata1(1) and not Tdata1(0); Mask1(62) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(65) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(70) <= Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(71) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(73) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(75) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(76) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(80) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(81) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(83) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(84) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(86) <= Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(87) <= not Tdata1(31) and not Tdata1(30) and Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and Tdata1(1) and not Tdata1(0); Mask1(90) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(92) <= not Tdata1(31) and not Tdata1(30) and Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(93) <= not Tdata1(31) and not Tdata1(30) and Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(97) <= not Tdata1(31) and not Tdata1(30) and Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(98) <= not Tdata1(31) and not Tdata1(30) and Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(101) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(102) <= Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(106) <= not Tdata1(31) and not Tdata1(30) and Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(107) <= not Tdata1(31) and not Tdata1(30) and Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(114) <= not Tdata1(31) and not Tdata1(30) and Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(115) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(116) <= Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(117) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(119) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(120) <= not Tdata1(31) and Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(124) <= not Tdata1(31) and Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(126) <= not Tdata1(31) and Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(127) <= Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(128) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(130) <= not Tdata1(31) and Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(132) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(133) <= not Tdata1(31) and Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(137) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(138) <= Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(139) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(140) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(143) <= Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(146) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(148) <= Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(150) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(151) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(155) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(156) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(157) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(159) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(160) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(162) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(164) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(165) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(166) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(167) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(170) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and not Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(171) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and not Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); Mask1(172) <= not Tdata1(31) and not Tdata1(30) and not Tdata1(29) and not Tdata1(28) and not Tdata1(27) and not Tdata1(26) and Tdata1(25) and not Tdata1(24) and not Tdata1(23) and not Tdata1(22) and not Tdata1(21) and not Tdata1(20) and not Tdata1(19) and not Tdata1(18) and Tdata1(17) and not Tdata1(16) and not Tdata1(15) and not Tdata1(14) and not Tdata1(13) and not Tdata1(12) and not Tdata1(11) and not Tdata1(10) and not Tdata1(9) and not Tdata1(8) and not Tdata1(7) and not Tdata1(6) and not Tdata1(5) and not Tdata1(4) and not Tdata1(3) and not Tdata1(2) and not Tdata1(1) and not Tdata1(0); -------------------------------------------- -- Alignment masks (parallel to the beampipe) -------------------------------------------- process(Tdata0) begin case Tdata0 is when "00000001000000010000000100000001" => ENC_DAT0(4) <= '1'; when "00000001000000010000000100000000" => ENC_DAT0(4) <= '1'; when "00000001000000010000000000000001" => ENC_DAT0(4) <= '1'; when "00000001000000000000000100000001" => ENC_DAT0(4) <= '1'; when "00000000000000010000000100000001" => ENC_DAT0(4) <= '1'; when "00000010000000100000001000000010" => ENC_DAT0(4) <= '1'; when "00000010000000100000001000000000" => ENC_DAT0(4) <= '1'; when "00000010000000100000000000000010" => ENC_DAT0(4) <= '1'; when "00000010000000000000001000000010" => ENC_DAT0(4) <= '1'; when "00000000000000100000001000000010" => ENC_DAT0(4) <= '1'; when "00000100000001000000010000000100" => ENC_DAT0(4) <= '1'; when "00000100000001000000010000000000" => ENC_DAT0(4) <= '1'; when "00000100000001000000000000000100" => ENC_DAT0(4) <= '1'; when "00000100000000000000010000000100" => ENC_DAT0(4) <= '1'; when "00000000000001000000010000000100" => ENC_DAT0(4) <= '1'; when "00001000000010000000100000001000" => ENC_DAT0(4) <= '1'; when "00001000000010000000100000000000" => ENC_DAT0(4) <= '1'; when "00001000000010000000000000001000" => ENC_DAT0(4) <= '1'; when "00001000000000000000100000001000" => ENC_DAT0(4) <= '1'; when "00000000000010000000100000001000" => ENC_DAT0(4) <= '1'; when "00010000000100000001000000010000" => ENC_DAT0(4) <= '1'; when "00010000000100000001000000000000" => ENC_DAT0(4) <= '1'; when "00010000000100000000000000010000" => ENC_DAT0(4) <= '1'; when "00010000000000000001000000010000" => ENC_DAT0(4) <= '1'; when "00000000000100000001000000010000" => ENC_DAT0(4) <= '1'; when "00100000001000000010000000100000" => ENC_DAT0(4) <= '1'; when "00100000001000000010000000000000" => ENC_DAT0(4) <= '1'; when "00100000001000000000000000100000" => ENC_DAT0(4) <= '1'; when "00100000000000000010000000100000" => ENC_DAT0(4) <= '1'; when "00000000001000000010000000100000" => ENC_DAT0(4) <= '1'; when "01000000010000000100000001000000" => ENC_DAT0(4) <= '1'; when "01000000010000000100000000000000" => ENC_DAT0(4) <= '1'; when "01000000010000000000000001000000" => ENC_DAT0(4) <= '1'; when "01000000000000000100000001000000" => ENC_DAT0(4) <= '1'; when "00000000010000000100000001000000" => ENC_DAT0(4) <= '1'; when "10000000100000001000000010000000" => ENC_DAT0(4) <= '1'; when "10000000100000001000000000000000" => ENC_DAT0(4) <= '1'; when "10000000100000000000000010000000" => ENC_DAT0(4) <= '1'; when "10000000000000001000000010000000" => ENC_DAT0(4) <= '1'; when "00000000100000001000000010000000" => ENC_DAT0(4) <= '1'; when others => ENC_DAT0(4) <= '0'; end case; end process; -------------------------------------------- process(Tdata1) begin case Tdata1 is when "00000001000000010000000100000001" => ENC_DAT1(4) <= '1'; when "00000001000000010000000100000000" => ENC_DAT1(4) <= '1'; when "00000001000000010000000000000001" => ENC_DAT1(4) <= '1'; when "00000001000000000000000100000001" => ENC_DAT1(4) <= '1'; when "00000000000000010000000100000001" => ENC_DAT1(4) <= '1'; when "00000010000000100000001000000010" => ENC_DAT1(4) <= '1'; when "00000010000000100000001000000000" => ENC_DAT1(4) <= '1'; when "00000010000000100000000000000010" => ENC_DAT1(4) <= '1'; when "00000010000000000000001000000010" => ENC_DAT1(4) <= '1'; when "00000000000000100000001000000010" => ENC_DAT1(4) <= '1'; when "00000100000001000000010000000100" => ENC_DAT1(4) <= '1'; when "00000100000001000000010000000000" => ENC_DAT1(4) <= '1'; when "00000100000001000000000000000100" => ENC_DAT1(4) <= '1'; when "00000100000000000000010000000100" => ENC_DAT1(4) <= '1'; when "00000000000001000000010000000100" => ENC_DAT1(4) <= '1'; when "00001000000010000000100000001000" => ENC_DAT1(4) <= '1'; when "00001000000010000000100000000000" => ENC_DAT1(4) <= '1'; when "00001000000010000000000000001000" => ENC_DAT1(4) <= '1'; when "00001000000000000000100000001000" => ENC_DAT1(4) <= '1'; when "00000000000010000000100000001000" => ENC_DAT1(4) <= '1'; when "00010000000100000001000000010000" => ENC_DAT1(4) <= '1'; when "00010000000100000001000000000000" => ENC_DAT1(4) <= '1'; when "00010000000100000000000000010000" => ENC_DAT1(4) <= '1'; when "00010000000000000001000000010000" => ENC_DAT1(4) <= '1'; when "00000000000100000001000000010000" => ENC_DAT1(4) <= '1'; when "00100000001000000010000000100000" => ENC_DAT1(4) <= '1'; when "00100000001000000010000000000000" => ENC_DAT1(4) <= '1'; when "00100000001000000000000000100000" => ENC_DAT1(4) <= '1'; when "00100000000000000010000000100000" => ENC_DAT1(4) <= '1'; when "00000000001000000010000000100000" => ENC_DAT1(4) <= '1'; when "01000000010000000100000001000000" => ENC_DAT1(4) <= '1'; when "01000000010000000100000000000000" => ENC_DAT1(4) <= '1'; when "01000000010000000000000001000000" => ENC_DAT1(4) <= '1'; when "01000000000000000100000001000000" => ENC_DAT1(4) <= '1'; when "00000000010000000100000001000000" => ENC_DAT1(4) <= '1'; when "10000000100000001000000010000000" => ENC_DAT1(4) <= '1'; when "10000000100000001000000000000000" => ENC_DAT1(4) <= '1'; when "10000000100000000000000010000000" => ENC_DAT1(4) <= '1'; when "10000000000000001000000010000000" => ENC_DAT1(4) <= '1'; when "00000000100000001000000010000000" => ENC_DAT1(4) <= '1'; when others => ENC_DAT1(4) <= '0'; end case; end process; -------------------------------------------- -- Clustering trigger masks -------------------------------------------- -- 1st theta range, sector "0" -------------------------- Thet_R0(0) <= Mask0(0) or Mask0(1) or Mask0(2) or Mask0(3) or Mask0(4) or Mask0(5) or Mask0(6) or Mask0(7) or Mask0(8) or Mask0(9) or Mask0(10) or Mask0(11) or Mask0(12) or Mask0(13) or Mask0(14) or Mask0(15) or Mask0(16) or Mask0(17) or Mask0(18) or Mask0(19) or Mask0(20) or Mask0(21); -------------------------- Thet_R0(1) <= Mask0(22) or Mask0(23) or Mask0(24) or Mask0(25) or Mask0(26) or Mask0(27) or Mask0(28) or Mask0(29) or Mask0(30) or Mask0(31) or Mask0(32) or Mask0(33) or Mask0(34) or Mask0(35) or Mask0(36) or Mask0(37) or Mask0(38) or Mask0(39) or Mask0(40) or Mask0(41) or Mask0(42) or Mask0(43); -------------------------- Thet_R0(2) <= Mask0(44) or Mask0(45) or Mask0(46) or Mask0(47) or Mask0(48) or Mask0(49) or Mask0(50) or Mask0(51) or Mask0(52) or Mask0(53) or Mask0(54) or Mask0(55) or Mask0(56) or Mask0(57) or Mask0(58) or Mask0(59) or Mask0(60) or Mask0(61) or Mask0(62) or Mask0(63) or Mask0(64) or Mask0(65); -------------------------- Thet_R0(3) <= Mask0(66) or Mask0(67) or Mask0(68) or Mask0(69) or Mask0(70) or Mask0(71) or Mask0(72) or Mask0(73) or Mask0(74) or Mask0(75) or Mask0(76) or Mask0(77) or Mask0(78) or Mask0(79) or Mask0(80) or Mask0(81) or Mask0(82) or Mask0(83) or Mask0(84) or Mask0(85) or Mask0(86) or Mask0(87); -------------------------- Thet_R0(4) <= Mask0(88) or Mask0(89) or Mask0(90) or Mask0(91) or Mask0(92) or Mask0(93) or Mask0(94) or Mask0(95) or Mask0(96) or Mask0(97) or Mask0(98) or Mask0(99) or Mask0(100) or Mask0(101) or Mask0(102) or Mask0(103) or Mask0(104) or Mask0(105) or Mask0(106) or Mask0(107) or Mask0(108) or Mask0(109); -------------------------- Thet_R0(5) <= Mask0(110) or Mask0(111) or Mask0(112) or Mask0(113) or Mask0(114) or Mask0(115) or Mask0(116) or Mask0(117) or Mask0(118) or Mask0(119) or Mask0(120) or Mask0(121) or Mask0(122) or Mask0(123) or Mask0(124) or Mask0(125) or Mask0(126) or Mask0(127) or Mask0(128) or Mask0(129) or Mask0(130) or Mask0(131); -------------------------- Thet_R0(6) <= Mask0(132) or Mask0(133) or Mask0(134) or Mask0(135) or Mask0(136) or Mask0(137) or Mask0(138) or Mask0(139) or Mask0(140) or Mask0(141) or Mask0(142) or Mask0(143) or Mask0(144) or Mask0(145) or Mask0(146) or Mask0(147) or Mask0(148) or Mask0(149) or Mask0(150) or Mask0(151) or Mask0(152) or Mask0(153); -------------------------- Thet_R0(7) <= Mask0(154) or Mask0(155) or Mask0(156) or Mask0(157) or Mask0(158) or Mask0(159) or Mask0(160) or Mask0(161) or Mask0(162) or Mask0(163) or Mask0(164) or Mask0(165) or Mask0(166) or Mask0(167) or Mask0(168) or Mask0(169) or Mask0(170) or Mask0(171) or Mask0(172) or Mask0(173); -------------------------- -- 1st theta range, sector "1" -------------------------- Thet_R1(0) <= Mask1(0) or Mask1(1) or Mask1(2) or Mask1(3) or Mask1(4) or Mask1(5) or Mask1(6) or Mask1(7) or Mask1(8) or Mask1(9) or Mask1(10) or Mask1(11) or Mask1(12) or Mask1(13) or Mask1(14) or Mask1(15) or Mask1(16) or Mask1(17) or Mask1(18) or Mask1(19) or Mask1(20) or Mask1(21); -------------------------- Thet_R1(1) <= Mask1(22) or Mask1(23) or Mask1(24) or Mask1(25) or Mask1(26) or Mask1(27) or Mask1(28) or Mask1(29) or Mask1(30) or Mask1(31) or Mask1(32) or Mask1(33) or Mask1(34) or Mask1(35) or Mask1(36) or Mask1(37) or Mask1(38) or Mask1(39) or Mask1(40) or Mask1(41) or Mask1(42) or Mask1(43); -------------------------- Thet_R1(2) <= Mask1(44) or Mask1(45) or Mask1(46) or Mask1(47) or Mask1(48) or Mask1(49) or Mask1(50) or Mask1(51) or Mask1(52) or Mask1(53) or Mask1(54) or Mask1(55) or Mask1(56) or Mask1(57) or Mask1(58) or Mask1(59) or Mask1(60) or Mask1(61) or Mask1(62) or Mask1(63) or Mask1(64) or Mask1(65); -------------------------- Thet_R1(3) <= Mask1(66) or Mask1(67) or Mask1(68) or Mask1(69) or Mask1(70) or Mask1(71) or Mask1(72) or Mask1(73) or Mask1(74) or Mask1(75) or Mask1(76) or Mask1(77) or Mask1(78) or Mask1(79) or Mask1(80) or Mask1(81) or Mask1(82) or Mask1(83) or Mask1(84) or Mask1(85) or Mask1(86) or Mask1(87); -------------------------- Thet_R1(4) <= Mask1(88) or Mask1(89) or Mask1(90) or Mask1(91) or Mask1(92) or Mask1(93) or Mask1(94) or Mask1(95) or Mask1(96) or Mask1(97) or Mask1(98) or Mask1(99) or Mask1(100) or Mask1(101) or Mask1(102) or Mask1(103) or Mask1(104) or Mask1(105) or Mask1(106) or Mask1(107) or Mask1(108) or Mask1(109); -------------------------- Thet_R1(5) <= Mask1(110) or Mask1(111) or Mask1(112) or Mask1(113) or Mask1(114) or Mask1(115) or Mask1(116) or Mask1(117) or Mask1(118) or Mask1(119) or Mask1(120) or Mask1(121) or Mask1(122) or Mask1(123) or Mask1(124) or Mask1(125) or Mask1(126) or Mask1(127) or Mask1(128) or Mask1(129) or Mask1(130) or Mask1(131); -------------------------- Thet_R1(6) <= Mask1(132) or Mask1(133) or Mask1(134) or Mask1(135) or Mask1(136) or Mask1(137) or Mask1(138) or Mask1(139) or Mask1(140) or Mask1(141) or Mask1(142) or Mask1(143) or Mask1(144) or Mask1(145) or Mask1(146) or Mask1(147) or Mask1(148) or Mask1(149) or Mask1(150) or Mask1(151) or Mask1(152) or Mask1(153); -------------------------- Thet_R1(7) <= Mask1(154) or Mask1(155) or Mask1(156) or Mask1(157) or Mask1(158) or Mask1(159) or Mask1(160) or Mask1(161) or Mask1(162) or Mask1(163) or Mask1(164) or Mask1(165) or Mask1(166) or Mask1(167) or Mask1(168) or Mask1(169) or Mask1(170) or Mask1(171) or Mask1(172) or Mask1(173); -------------------------- -- 2nd theta range, sector "0" -------------------------- Thet_R0(8) <= Thet_R0(0) or Thet_R0(1); Thet_R0(9) <= Thet_R0(2) or Thet_R0(3); Thet_R0(10) <= Thet_R0(4) or Thet_R0(5); Thet_R0(11) <= Thet_R0(6) or Thet_R0(7); -------------------------- -- 2nd theta range, sector "1" -------------------------- Thet_R1(8) <= Thet_R1(0) or Thet_R1(1); Thet_R1(9) <= Thet_R1(2) or Thet_R1(3); Thet_R1(10) <= Thet_R1(4) or Thet_R1(5); Thet_R1(11) <= Thet_R1(6) or Thet_R1(7); -------------------------- -- 3rd theta range, sector "0" -------------------------- Thet_R0(12) <= Thet_R0(8) or Thet_R0(9); Thet_R0(13) <= Thet_R0(10) or Thet_R0(11); -------------------------- -- 3rd theta range, sector "1" -------------------------- Thet_R1(12) <= Thet_R1(8) or Thet_R1(9); Thet_R1(13) <= Thet_R1(10) or Thet_R1(11); -------------------------- -- whole acceptance, sector "0" -------------------------- Thet_R0(14) <= Thet_R0(12) or Thet_R0(13); -------------------------- -- whole acceptance, sector "1" -------------------------- Thet_R1(14) <= Thet_R1(12) or Thet_R1(13); -------------------------------------------- -- Computing the number of pads fired -------------------------------------------- PAD_NR0 <= SUM_of_ONES_32(Tdata0); PAD_NR1 <= SUM_of_ONES_32(Tdata1); -------------------------------------------- -- "Theta" range encoding in sector "0" -------------------------------------------- process(S0_ECH1, S0_ECH2, S0_ECH3) begin -------------------------- -- No tracks at all -------------------------- if (S0_ECH1 = "00000000") then MSK_RG0 <= "0000"; -------------------------- -- High angular resolution -------------------------- elsif (S0_ECH1 = "00000001") then MSK_RG0 <= "0001"; elsif (S0_ECH1 = "00000010") then MSK_RG0 <= "0010"; elsif (S0_ECH1 = "00000100") then MSK_RG0 <= "0011"; elsif (S0_ECH1 = "00001000") then MSK_RG0 <= "0100"; elsif (S0_ECH1 = "00010000") then MSK_RG0 <= "0101"; elsif (S0_ECH1 = "00100000") then MSK_RG0 <= "0110"; elsif (S0_ECH1 = "01000000") then MSK_RG0 <= "0111"; elsif (S0_ECH1 = "10000000") then MSK_RG0 <= "1000"; -------------------------- -- Medium angular resolution -------------------------- elsif (S0_ECH2 = "0001") then MSK_RG0 <= "1001"; elsif (S0_ECH2 = "0010") then MSK_RG0 <= "1010"; elsif (S0_ECH2 = "0100") then MSK_RG0 <= "1011"; elsif (S0_ECH2 = "1000") then MSK_RG0 <= "1100"; -------------------------- -- Poor angular resolution -------------------------- elsif (S0_ECH3 = "01") then MSK_RG0 <= "1101"; elsif (S0_ECH3 = "10") then MSK_RG0 <= "1110"; else -------------------------- -- Not resolved tracks -------------------------- MSK_RG0 <= "1111"; end if; end process; -------------------------- -- "Theta" range encoding in sector "1" -------------------------------------------- process(S1_ECH1, S1_ECH2, S1_ECH3) begin -------------------------- -- No tracks at all -------------------------- if (S1_ECH1 = "00000000") then MSK_RG1 <= "0000"; -------------------------- -- High angular resolution -------------------------- elsif (S1_ECH1 = "00000001") then MSK_RG1 <= "0001"; elsif (S1_ECH1 = "00000010") then MSK_RG1 <= "0010"; elsif (S1_ECH1 = "00000100") then MSK_RG1 <= "0011"; elsif (S1_ECH1 = "00001000") then MSK_RG1 <= "0100"; elsif (S1_ECH1 = "00010000") then MSK_RG1 <= "0101"; elsif (S1_ECH1 = "00100000") then MSK_RG1 <= "0110"; elsif (S1_ECH1 = "01000000") then MSK_RG1 <= "0111"; elsif (S1_ECH1 = "10000000") then MSK_RG1 <= "1000"; -------------------------- -- Medium angular resolution -------------------------- elsif (S1_ECH2 = "0001") then MSK_RG1 <= "1001"; elsif (S1_ECH2 = "0010") then MSK_RG1 <= "1010"; elsif (S1_ECH2 = "0100") then MSK_RG1 <= "1011"; elsif (S1_ECH2 = "1000") then MSK_RG1 <= "1100"; -------------------------- -- Poor angular resolution -------------------------- elsif (S1_ECH3 = "01") then MSK_RG1 <= "1101"; elsif (S1_ECH3 = "10") then MSK_RG1 <= "1110"; else -------------------------- -- Not resolved tracks -------------------------- MSK_RG1 <= "1111"; end if; end process; -------------------------------------------- -- Forming the L2 data during "Pipeline enable": -------------------------------------------- process(Thet_R0(14), MSK_RG0, PAD_NR0) begin if (Thet_R0(14) = '1') then ENC_DAT0(6) <= '1'; ENC_DAT0(3 downto 0) <= MSK_RG0; else ENC_DAT0(6) <= '0'; ENC_DAT0(3 downto 0) <= conv_std_logic_vector(PAD_NR0, 4); end if; end process; -------------------------- process(PAD_NR0) begin if (7 <= PAD_NR0) then ENC_DAT0(5) <= '1'; else ENC_DAT0(5) <= '0'; end if; end process; -------------------------------------------- process(Thet_R1(14), MSK_RG1, PAD_NR1) begin if (Thet_R1(14) = '1') then ENC_DAT1(6) <= '1'; ENC_DAT1(3 downto 0) <= MSK_RG1; else ENC_DAT1(6) <= '0'; ENC_DAT1(3 downto 0) <= conv_std_logic_vector(PAD_NR1, 4); end if; end process; -------------------------- process(PAD_NR1) begin if (7 <= PAD_NR1) then ENC_DAT1(5) <= '1'; else ENC_DAT1(5) <= '0'; end if; end process; -------------------------------------------- -- Synchronizing all trigger signals -- after their individual delays (Clock <-) -------------------------------------------- process(Clock, ENC_DAT0, ENC_DAT1) begin if (Clock'event and Clock = '0') then DEL_BUF0 <= ENC_DAT0; DEL_BUF1 <= ENC_DAT1; end if; end process; -------------------------------------------- -- Forming the output data (Clock ->) -------------------------------------------- process(Clock, DEL_BUF0, DEL_BUF1) begin if (Clock'event and Clock = '1') then TRG_DAT0(7 downto 1) <= DEL_BUF0; TRG_DAT1(7 downto 1) <= DEL_BUF1; end if; end process; -------------------------- TRG_DAT0(0) <= RAD_MN0; TRG_DAT1(0) <= RAD_MN1; -------------------------------------------- -- Delay the L1Keep signal to match -- the synchronization phase and to -- increment the pipeline address -- by one after event announcement -- to point to the earliest time -- slice in the data history (Clock <-) -------------------------------------------- process(Clock, L1Keep) begin if (Clock'event and Clock = '0') then L1K_DEL <= L1Keep; end if; end process; -------------------------------------------- -- Pipeline counter - incremented by one -- and blocked after event announcement (Clock ->) -------------------------------------------- process(Clock, L1K_DEL) begin if (Clock'event and Clock = '1') then if (L1K_DEL = '0') then PIP_CNT <= PIP_CNT + 1; else null; end if; end if; end process; -------------------------------------------- -- Latch raw data only during -- pipeline enable (Clock <-) -------------------------------------------- process(Clock, L1Keep, PIP_CNT, Tdata0, Tdata1) begin if (Clock'event and Clock = '0') then if (L1Keep = '0') then case PIP_CNT is when 0 => RDM_000 <= Tdata0; RDM_100 <= Tdata1; when 1 => RDM_001 <= Tdata0; RDM_101 <= Tdata1; when 2 => RDM_002 <= Tdata0; RDM_102 <= Tdata1; when 3 => RDM_003 <= Tdata0; RDM_103 <= Tdata1; when 4 => RDM_004 <= Tdata0; RDM_104 <= Tdata1; when 5 => RDM_005 <= Tdata0; RDM_105 <= Tdata1; when 6 => RDM_006 <= Tdata0; RDM_106 <= Tdata1; when 7 => RDM_007 <= Tdata0; RDM_107 <= Tdata1; when 8 => RDM_008 <= Tdata0; RDM_108 <= Tdata1; when 9 => RDM_009 <= Tdata0; RDM_109 <= Tdata1; when 10 => RDM_010 <= Tdata0; RDM_110 <= Tdata1; when 11 => RDM_011 <= Tdata0; RDM_111 <= Tdata1; when 12 => RDM_012 <= Tdata0; RDM_112 <= Tdata1; when 13 => RDM_013 <= Tdata0; RDM_113 <= Tdata1; when 14 => RDM_014 <= Tdata0; RDM_114 <= Tdata1; when 15 => RDM_015 <= Tdata0; RDM_115 <= Tdata1; when 16 => RDM_016 <= Tdata0; RDM_116 <= Tdata1; when 17 => RDM_017 <= Tdata0; RDM_117 <= Tdata1; when 18 => RDM_018 <= Tdata0; RDM_118 <= Tdata1; when 19 => RDM_019 <= Tdata0; RDM_119 <= Tdata1; when 20 => RDM_020 <= Tdata0; RDM_120 <= Tdata1; when 21 => RDM_021 <= Tdata0; RDM_121 <= Tdata1; when 22 => RDM_022 <= Tdata0; RDM_122 <= Tdata1; when 23 => RDM_023 <= Tdata0; RDM_123 <= Tdata1; when 24 => RDM_024 <= Tdata0; RDM_124 <= Tdata1; when 25 => RDM_025 <= Tdata0; RDM_125 <= Tdata1; when 26 => RDM_026 <= Tdata0; RDM_126 <= Tdata1; when 27 => RDM_027 <= Tdata0; RDM_127 <= Tdata1; when 28 => RDM_028 <= Tdata0; RDM_128 <= Tdata1; when 29 => RDM_029 <= Tdata0; RDM_129 <= Tdata1; when 30 => RDM_030 <= Tdata0; RDM_130 <= Tdata1; when others => RDM_031 <= Tdata0; RDM_131 <= Tdata1; end case; else null; end if; end if; end process; -------------------------------------------- -- Looking back into history -------------------------------------------- PIP_SEL <= PIP_CNT - BIT5_to_NUM(APEX_T0); -------------------------------------------- -- Select output data (Clock ->) -------------------------------------------- process(PIP_SEL, RDM_000, RDM_001, RDM_002, RDM_003, RDM_004, RDM_005, RDM_006, RDM_007, RDM_008, RDM_009, RDM_010, RDM_011, RDM_012, RDM_013, RDM_014, RDM_015, RDM_016, RDM_017, RDM_018, RDM_019, RDM_020, RDM_021, RDM_022, RDM_023, RDM_024, RDM_025, RDM_026, RDM_027, RDM_028, RDM_029, RDM_030, RDM_031, RDM_100, RDM_101, RDM_102, RDM_103, RDM_104, RDM_105, RDM_106, RDM_107, RDM_108, RDM_109, RDM_110, RDM_111, RDM_112, RDM_113, RDM_114, RDM_115, RDM_116, RDM_117, RDM_118, RDM_119, RDM_120, RDM_121, RDM_122, RDM_123, RDM_124, RDM_125, RDM_126, RDM_127, RDM_128, RDM_129, RDM_130, RDM_131) begin case PIP_SEL is when 0 => PIP_OUT0 <= RDM_000; PIP_OUT1 <= RDM_100; when 1 => PIP_OUT0 <= RDM_001; PIP_OUT1 <= RDM_101; when 2 => PIP_OUT0 <= RDM_002; PIP_OUT1 <= RDM_102; when 3 => PIP_OUT0 <= RDM_003; PIP_OUT1 <= RDM_103; when 4 => PIP_OUT0 <= RDM_004; PIP_OUT1 <= RDM_104; when 5 => PIP_OUT0 <= RDM_005; PIP_OUT1 <= RDM_105; when 6 => PIP_OUT0 <= RDM_006; PIP_OUT1 <= RDM_106; when 7 => PIP_OUT0 <= RDM_007; PIP_OUT1 <= RDM_107; when 8 => PIP_OUT0 <= RDM_008; PIP_OUT1 <= RDM_108; when 9 => PIP_OUT0 <= RDM_009; PIP_OUT1 <= RDM_109; when 10 => PIP_OUT0 <= RDM_010; PIP_OUT1 <= RDM_110; when 11 => PIP_OUT0 <= RDM_011; PIP_OUT1 <= RDM_111; when 12 => PIP_OUT0 <= RDM_012; PIP_OUT1 <= RDM_112; when 13 => PIP_OUT0 <= RDM_013; PIP_OUT1 <= RDM_113; when 14 => PIP_OUT0 <= RDM_014; PIP_OUT1 <= RDM_114; when 15 => PIP_OUT0 <= RDM_015; PIP_OUT1 <= RDM_115; when 16 => PIP_OUT0 <= RDM_016; PIP_OUT1 <= RDM_116; when 17 => PIP_OUT0 <= RDM_017; PIP_OUT1 <= RDM_117; when 18 => PIP_OUT0 <= RDM_018; PIP_OUT1 <= RDM_118; when 19 => PIP_OUT0 <= RDM_019; PIP_OUT1 <= RDM_119; when 20 => PIP_OUT0 <= RDM_020; PIP_OUT1 <= RDM_120; when 21 => PIP_OUT0 <= RDM_021; PIP_OUT1 <= RDM_121; when 22 => PIP_OUT0 <= RDM_022; PIP_OUT1 <= RDM_122; when 23 => PIP_OUT0 <= RDM_023; PIP_OUT1 <= RDM_123; when 24 => PIP_OUT0 <= RDM_024; PIP_OUT1 <= RDM_124; when 25 => PIP_OUT0 <= RDM_025; PIP_OUT1 <= RDM_125; when 26 => PIP_OUT0 <= RDM_026; PIP_OUT1 <= RDM_126; when 27 => PIP_OUT0 <= RDM_027; PIP_OUT1 <= RDM_127; when 28 => PIP_OUT0 <= RDM_028; PIP_OUT1 <= RDM_128; when 29 => PIP_OUT0 <= RDM_029; PIP_OUT1 <= RDM_129; when 30 => PIP_OUT0 <= RDM_030; PIP_OUT1 <= RDM_130; when others => PIP_OUT0 <= RDM_031; PIP_OUT1 <= RDM_131; end case; end process; -------------------------------------------- -- Readout cluster counter - it is reset for -- rejected events, the raw data readout is -- terminated. -------------------------------------------- process(Clock, L1Keep, CLS_GTE) begin if (Clock'event and Clock = '0') then if (L1Keep = '0') then CLS_CNT <= 0; elsif (CLS_GTE = '1') then CLS_CNT <= CLS_CNT + 1; else null; end if; end if; end process; -------------------------------------------- -- Gate for the cluster counter (Clock ->) -- After the interrupted readout the gate -- remains active until the next event. -------------------------------------------- process(Clock, CLS_CNT) begin if (Clock'event and Clock = '1') then if (CLS_CNT = 7) then CLS_GTE <= '0'; else CLS_GTE <= '1'; end if; end if; end process; -------------------------------------------- -- Filling the cluster (Clock ->) -------------------------------------------- process(Clock, CLS_CNT, STA_REG, PIP_OUT0, PIP_OUT1) begin if (Clock'event and Clock = '1') then case CLS_CNT is when 1 => RAW_DAT0 <= STA_REG; RAW_DAT1 <= STA_REG; RM_Lock <= '1'; when 2 => RAW_DAT0 <= PIP_OUT0(31 downto 24); RAW_DAT1 <= PIP_OUT1(31 downto 24); RM_Lock <= '1'; when 3 => RAW_DAT0 <= PIP_OUT0(23 downto 16); RAW_DAT1 <= PIP_OUT1(23 downto 16); RM_Lock <= '1'; when 4 => RAW_DAT0 <= PIP_OUT0(15 downto 8); RAW_DAT1 <= PIP_OUT1(15 downto 8); RM_Lock <= '1'; when 5 => RAW_DAT0 <= PIP_OUT0(7 downto 0); RAW_DAT1 <= PIP_OUT1(7 downto 0); RM_Lock <= '1'; when others => RAW_DAT0 <= "00000000"; RAW_DAT1 <= "00000000"; RM_Lock <= '0'; end case; end if; end process; -------------------------------------------- -- Trigger / Raw data output -------------------------------------------- process(RM_Lock, TRG_DAT0, TRG_DAT1, RAW_DAT0, RAW_DAT1) begin case RM_Lock is when '0' => Pre_M0 <= TRG_DAT0; Pre_M1 <= TRG_DAT1; when others => Pre_M0 <= RAW_DAT0; Pre_M1 <= RAW_DAT1; end case; end process; -------------------------------------------- -- Gate for the calibration counter (Clock ->) -------------------------------------------- process(Clock, L1K_DEL) begin if (Clock'event and Clock = '1') then CAL_GTE <= not L1K_DEL; end if; end process; -------------------------------------------- -- Synchronizing the calibration circuitry -- to the "Pipeline Enable" control signal. -- It provides a guaranteed delay for the -- system relaxation after opening the -- pipeline. The stand-alone operation of -- the repeater card enables the calibration -- pulse as this card drives a permanent "PEN" -- signal. It helps also to measure an exact -- delay of the Pad system with respect to -- the reference strobe (Clock <-) -------------------------------------------- process(Clock, CalEn, L1Keep, CAL_GTE) begin if (Clock'event and Clock = '0') then if (CalEn = '0') then CAL_CNT <= 0; elsif (L1Keep = '0' and CAL_GTE = '0') then CAL_CNT <= 0; else CAL_CNT <= CAL_CNT + 1; end if; end if; end process; -------------------------------------------- -- Gate for the safety counter (Clock <-) -------------------------------------------- process(Clock, SAF_CNT) begin if (Clock'event and Clock = '0') then case SAF_CNT is when 0 => SAF_GTE <= '1'; when 2 => SAF_GTE <= '0'; when others => null; end case; end if; end process; -------------------------------------------- -- Safety counter (Clock <-) -------------------------------------------- process(Clock, CAL_CNT, SAF_GTE) begin if (Clock'event and Clock = '1') then if (1 <= CAL_CNT) then SAF_CNT <= 0; elsif (SAF_GTE = '1') then SAF_CNT <= SAF_CNT + 1; else null; end if; end if; end process; -------------------------------------------- -- Safety pulse (Clock <-) -------------------------------------------- process(Clock, SAF_CNT) begin if (Clock'event and Clock = '0') then if (SAF_CNT = 1) then SAF_PUL <= '1'; else SAF_PUL <= '0'; end if; end if; end process; -------------------------------------------- -- Generating the calibration pulse -------------------------------------------- process(Clock, SAF_PUL, CAL_CNT) begin if (Clock'event and Clock = '1') then if (SAF_PUL = '1') then CPul <= '0'; elsif (CAL_CNT = 10) then CPul <= '1'; elsif (Cal_CNT = 138) then CPul <= '0'; else null; end if; end if; end process; -------------------------------------------- -- Radiation monitor -------------------------------------------- -- Mask channels -------------------------- Sensor0(7) <= Tdata0(7) and D00_MSK(7); Sensor0(6) <= Tdata0(6) and D00_MSK(6); Sensor0(5) <= Tdata0(5) and D00_MSK(5); Sensor0(4) <= Tdata0(4) and D00_MSK(4); Sensor0(3) <= Tdata0(3) and D00_MSK(3); Sensor0(2) <= Tdata0(2) and D00_MSK(2); Sensor0(1) <= Tdata0(1) and D00_MSK(1); Sensor0(0) <= Tdata0(0) and D00_MSK(0); Sensor2(7) <= Tdata0(15) and D01_MSK(7); Sensor2(6) <= Tdata0(14) and D01_MSK(6); Sensor2(5) <= Tdata0(13) and D01_MSK(5); Sensor2(4) <= Tdata0(12) and D01_MSK(4); Sensor2(3) <= Tdata0(11) and D01_MSK(3); Sensor2(2) <= Tdata0(10) and D01_MSK(2); Sensor2(1) <= Tdata0(9) and D01_MSK(1); Sensor2(0) <= Tdata0(8) and D01_MSK(0); Sensor4(7) <= Tdata0(23) and D02_MSK(7); Sensor4(6) <= Tdata0(22) and D02_MSK(6); Sensor4(5) <= Tdata0(21) and D02_MSK(5); Sensor4(4) <= Tdata0(20) and D02_MSK(4); Sensor4(3) <= Tdata0(19) and D02_MSK(3); Sensor4(2) <= Tdata0(18) and D02_MSK(2); Sensor4(1) <= Tdata0(17) and D02_MSK(1); Sensor4(0) <= Tdata0(16) and D02_MSK(0); Sensor6(7) <= Tdata0(31) and D03_MSK(7); Sensor6(6) <= Tdata0(30) and D03_MSK(6); Sensor6(5) <= Tdata0(29) and D03_MSK(5); Sensor6(4) <= Tdata0(28) and D03_MSK(4); Sensor6(3) <= Tdata0(27) and D03_MSK(3); Sensor6(2) <= Tdata0(26) and D03_MSK(2); Sensor6(1) <= Tdata0(25) and D03_MSK(1); Sensor6(0) <= Tdata0(24) and D03_MSK(0); Sensor1(7) <= Tdata1(7) and D10_MSK(7); Sensor1(6) <= Tdata1(6) and D10_MSK(6); Sensor1(5) <= Tdata1(5) and D10_MSK(5); Sensor1(4) <= Tdata1(4) and D10_MSK(4); Sensor1(3) <= Tdata1(3) and D10_MSK(3); Sensor1(2) <= Tdata1(2) and D10_MSK(2); Sensor1(1) <= Tdata1(1) and D10_MSK(1); Sensor1(0) <= Tdata1(0) and D10_MSK(0); Sensor3(7) <= Tdata1(15) and D11_MSK(7); Sensor3(6) <= Tdata1(14) and D11_MSK(6); Sensor3(5) <= Tdata1(13) and D11_MSK(5); Sensor3(4) <= Tdata1(12) and D11_MSK(4); Sensor3(3) <= Tdata1(11) and D11_MSK(3); Sensor3(2) <= Tdata1(10) and D11_MSK(2); Sensor3(1) <= Tdata1(9) and D11_MSK(1); Sensor3(0) <= Tdata1(8) and D11_MSK(0); Sensor5(7) <= Tdata1(23) and D12_MSK(7); Sensor5(6) <= Tdata1(22) and D12_MSK(6); Sensor5(5) <= Tdata1(21) and D12_MSK(5); Sensor5(4) <= Tdata1(20) and D12_MSK(4); Sensor5(3) <= Tdata1(19) and D12_MSK(3); Sensor5(2) <= Tdata1(18) and D12_MSK(2); Sensor5(1) <= Tdata1(17) and D12_MSK(1); Sensor5(0) <= Tdata1(16) and D12_MSK(0); Sensor7(7) <= Tdata1(31) and D13_MSK(7); Sensor7(6) <= Tdata1(30) and D13_MSK(6); Sensor7(5) <= Tdata1(29) and D13_MSK(5); Sensor7(4) <= Tdata1(28) and D13_MSK(4); Sensor7(3) <= Tdata1(27) and D13_MSK(3); Sensor7(2) <= Tdata1(26) and D13_MSK(2); Sensor7(1) <= Tdata1(25) and D13_MSK(1); Sensor7(0) <= Tdata1(24) and D13_MSK(0); -------------------------- -- Convert units -------------------------- Shovel0 <= SUM_of_ONES_8(Sensor0); Shovel2 <= SUM_of_ONES_8(Sensor2); Shovel4 <= SUM_of_ONES_8(Sensor4); Shovel6 <= SUM_of_ONES_8(Sensor6); Shovel1 <= SUM_of_ONES_8(Sensor1); Shovel3 <= SUM_of_ONES_8(Sensor3); Shovel5 <= SUM_of_ONES_8(Sensor5); Shovel7 <= SUM_of_ONES_8(Sensor7); -------------------------------------------- -- Loop over the total number of pads -- for one silicon sensor (Clock <-) -------------------------------------------- process(Clock, Gate0, Shovel0, Collect0) begin if (Clock'event and Clock = '0') then if (Gate0 = '0') then Basket0 <= 0; elsif (Collect0 = '1') then Basket0 <= Basket0 + Shovel0; else null; end if; end if; end process; -------------------------- process(Clock, Gate0, Shovel2, Collect0) begin if (Clock'event and Clock = '0') then if (Gate0 = '0') then Basket2 <= 0; elsif (Collect0 = '1') then Basket2 <= Basket2 + Shovel2; else null; end if; end if; end process; -------------------------- process(Clock, Gate0, Shovel4, Collect0) begin if (Clock'event and Clock = '0') then if (Gate0 = '0') then Basket4 <= 0; elsif (Collect0 = '1') then Basket4 <= Basket4 + Shovel4; else null; end if; end if; end process; -------------------------- process(Clock, Gate0, Shovel6, Collect0) begin if (Clock'event and Clock = '0') then if (Gate0 = '0') then Basket6 <= 0; elsif (Collect0 = '1') then Basket6 <= Basket6 + Shovel6; else null; end if; end if; end process; -------------------------- -------------------------- process(Clock, Gate1, Shovel1, Collect1) begin if (Clock'event and Clock = '0') then if (Gate1 = '0') then Basket1 <= 0; elsif (Collect1 = '1') then Basket1 <= Basket1 + Shovel1; else null; end if; end if; end process; -------------------------- process(Clock, Gate1, Shovel3, Collect1) begin if (Clock'event and Clock = '0') then if (Gate1 = '0') then Basket3 <= 0; elsif (Collect1 = '1') then Basket3 <= Basket3 + Shovel3; else null; end if; end if; end process; -------------------------- process(Clock, Gate1, Shovel5, Collect1) begin if (Clock'event and Clock = '0') then if (Gate1 = '0') then Basket5 <= 0; elsif (Collect1 = '1') then Basket5 <= Basket5 + Shovel5; else null; end if; end if; end process; -------------------------- process(Clock, Gate1, Shovel7, Collect1) begin if (Clock'event and Clock = '0') then if (Gate1 = '0') then Basket7 <= 0; elsif (Collect1 = '1') then Basket7 <= Basket7 + Shovel7; else null; end if; end if; end process; -------------------------------------------- -- Counter overflow -------------------------------------------- process(Clock, Limit, Basket0) begin if (Clock'event and Clock = '1') then if ((Limit - 7) <= Basket0) then Overflow0 <= '1'; else Overflow0 <= '0'; end if; end if; end process; -------------------------- process(Clock, Limit, Basket2) begin if (Clock'event and Clock = '1') then if ((Limit - 7) <= Basket2) then Overflow2 <= '1'; else Overflow2 <= '0'; end if; end if; end process; -------------------------- process(Clock, Limit, Basket4) begin if (Clock'event and Clock = '1') then if ((Limit - 7) <= Basket4) then Overflow4 <= '1'; else Overflow4 <= '0'; end if; end if; end process; -------------------------- process(Clock, Limit, Basket6) begin if (Clock'event and Clock = '1') then if ((Limit - 7) <= Basket6) then Overflow6 <= '1'; else Overflow6 <= '0'; end if; end if; end process; -------------------------- -------------------------- process(Clock, Limit, Basket1) begin if (Clock'event and Clock = '1') then if ((Limit - 7) <= Basket1) then Overflow1 <= '1'; else Overflow1 <= '0'; end if; end if; end process; -------------------------- process(Clock, Limit, Basket3) begin if (Clock'event and Clock = '1') then if ((Limit - 7) <= Basket3) then Overflow3 <= '1'; else Overflow3 <= '0'; end if; end if; end process; -------------------------- process(Clock, Limit, Basket5) begin if (Clock'event and Clock = '1') then if ((Limit - 7) <= Basket5) then Overflow5 <= '1'; else Overflow5 <= '0'; end if; end if; end process; -------------------------- process(Clock, Limit, Basket7) begin if (Clock'event and Clock = '1') then if ((Limit - 7) <= Basket7) then Overflow7 <= '1'; else Overflow7 <= '0'; end if; end if; end process; -------------------------------------------- -- The maximum rate among all -- "Counter overflow" events -------------------------------------------- Push0 <= Overflow0 or Overflow2 or Overflow4 or Overflow6; Push1 <= Overflow1 or Overflow3 or Overflow5 or Overflow7; -------------------------------------------- -- Standard pulse (1 b.c.) after the overflow -- while "Push" could be longer (Clock ->) -------------------------------------------- process(Gate0, Push0) begin if (Gate0 = '0') then Door0 <= '0'; elsif(Push0'event and Push0 = '1') then Door0 <= '1'; end if; end process; -------------------------- process(Gate1, Push1) begin if (Gate1 = '0') then Door1 <= '0'; elsif(Push1'event and Push1 = '1') then Door1 <= '1'; end if; end process; -------------------------------------------- -- Normalizing interval ~50 ms. -------------------------------------------- process(Clock, Door0, Limit) begin if (Clock'event and Clock = '0') then if (Door0 = '1') then Timer0 <= Limit; else Timer0 <= Timer0 + 1; end if; end if; end process; -------------------------- process(Clock, Door1, Limit) begin if (Clock'event and Clock = '0') then if (Door1 = '1') then Timer1 <= Limit; else Timer1 <= Timer1 + 1; end if; end if; end process; -------------------------------------------- -- Accumulator is ready (Clock ->) -------------------------------------------- process(Clock, Timer0, Limit) begin if (Clock'event and Clock = '1') then if (Timer0 = Limit) then Gate0 <= '0'; elsif (Timer0 = 0) then Gate0 <= '1'; else null; end if; end if; end process; -------------------------- process(Clock, Timer1, Limit) begin if (Clock'event and Clock = '1') then if (Timer1 = Limit) then Gate1 <= '0'; elsif (Timer1 = 0) then Gate1 <= '1'; else null; end if; end if; end process; -------------------------------------------- -- Enable data collection (Clock ->) -------------------------------------------- process(Push0, Gate0) begin if (Push0 = '1') then Collect0 <= '0'; elsif (Gate0'event and Gate0 = '1') then Collect0 <= '1'; end if; end process; -------------------------- process(Push1, Gate1) begin if (Push1 = '1') then Collect1 <= '0'; elsif (Gate1'event and Gate1 = '1') then Collect1 <= '1'; end if; end process; -------------------------------------------- -- Maximum event rate (Clock <-) -------------------------------------------- process(Basket0, Basket2, Basket4, Basket6, Tray0) variable TEMP: natural range 0 to Cut; begin TEMP:= Basket0; if (TEMP <= Basket2) then TEMP:= Basket2; end if; if (TEMP <= Basket4) then TEMP:= Basket4; end if; if (TEMP <= Basket6) then TEMP:= Basket6; end if; Firewood0 <= TEMP + Tray0; end process; -------------------------- process(Basket1, Basket3, Basket5, Basket7, Tray1) variable TEMP: natural range 0 to Cut; begin TEMP:= Basket1; if (TEMP <= Basket3) then TEMP:= Basket3; end if; if (TEMP <= Basket5) then TEMP:= Basket5; end if; if (TEMP <= Basket7) then TEMP:= Basket7; end if; Firewood1 <= TEMP + Tray1; end process; -------------------------------------------- -- Phasing the lock signal -------------------------------------------- process(Clock, RM_Lock) begin if (Clock'event and Clock = '0') then RML_DEL <= RM_Lock; end if; end process; -------------------------------------------- -- Pulse number modulation (Clock ->) -------------------------------------------- process(Clock, Timer0, Limit, Firewood0, Tray0, RML_DEL) begin if (Clock'event and Clock = '1') then if (Timer0 = Limit) then Oven0 <= Firewood0; elsif (1 <= Tray0 and RML_DEL = '0') then Oven0 <= Oven0 - 1; else null; end if; end if; end process; -------------------------- process(Clock, Timer1, Limit, Firewood1, Tray1, RML_DEL) begin if (Clock'event and Clock = '1') then if (Timer1 = Limit) then Oven1 <= Firewood1; elsif (1 <= Tray1 and RML_DEL = '0') then Oven1 <= Oven1 - 1; else null; end if; end if; end process; -------------------------------------------- -- Phase shift for the PNM -------------------------------------------- process(Clock, Gate0, Oven0) begin if (Clock'event and Clock = '0') then if (Gate0 = '1') then Tray0 <= Oven0; else null; end if; end if; end process; -------------------------- process(Clock, Gate1, Oven1) begin if (Clock'event and Clock = '0') then if (Gate1 = '1') then Tray1 <= Oven1; else null; end if; end if; end process; -------------------------------------------- -- Radiation monitor -------------------------------------------- process(Tray0, Clock) begin if (1 <= Tray0) then RAD_MN0 <= Clock; else RAD_MN0 <= '0'; end if; end process; -------------------------- process(Tray1, Clock) begin if (1 <= Tray1) then RAD_MN1 <= Clock; else RAD_MN1 <= '0'; end if; end process; -------------------------------------------- -- Output word (16 bit) -------------------------------------------- Mout0(0) <= not Pre_M0(0); Mout0(1) <= not Pre_M0(1); Mout0(2) <= not Pre_M0(2); Mout0(3) <= not Pre_M0(3); Mout0(4) <= not Pre_M0(4); Mout0(5) <= not Pre_M0(5); Mout0(6) <= not Pre_M0(6); Mout0(7) <= not Pre_M0(7); -------------------------- Mout1(0) <= not Pre_M1(0); Mout1(1) <= not Pre_M1(1); Mout1(2) <= not Pre_M1(2); Mout1(3) <= not Pre_M1(3); Mout1(4) <= not Pre_M1(4); Mout1(5) <= not Pre_M1(5); Mout1(6) <= not Pre_M1(6); Mout1(7) <= not Pre_M1(7); -------------------------------------------- end;