-- The new version of the Pad slow control processor
-- in BST-2003 design after the radiation damage rapair.
-- It includes now the serial interface instead of the
-- former CAN system and the ASICs power supply manager
-- with the reset option. The thresholds are generated
-- by the charge pump driven through the ALTERA chip
-- which generates 100ns pulses with a duty cycle 1/2
-- to 1/256. The values (-1 mV / count) become active
-- immediately after assignment (no need for extra
-- load command).

-- The register 0x55 access with a write permission
-- re-activates the default "power-on" settings.

-- Functions of the state machine are defined via the
-- control register 0x56. Writing data to it launches
-- the commands encoded by the combination of bits.

-- Address allocation:
--------------------------------------------

-- Indicators
--------------------------
-- 0x01 - supply watchdogs	(read only);
-- 0x02 - PRO/A load status	(read only);

-- Thresholds:
--------------------------
-- 0x03 - Threshold 00;
-- 0x04 - Threshold 01;
-- 0x05 - Threshold 02;
-- 0x06 - Threshold 03;
-- 0x07 - Threshold 10;
-- 0x08 - Threshold 11;
-- 0x09 - Threshold 12;
-- 0x0A - Threshold 13;

-- PRO/A settings:
--------------------------
-- 0x0C - test enable pad 03;
-- 0x0D - test enable pad 02;
-- 0x0E - test enable pad 01;
-- 0x0F - test enable pad 00;
-- 0x10 - test enable pad 23;
-- 0x11 - test enable pad 22;
-- 0x12 - test enable pad 21;
-- 0x13 - test enable pad 20;
-- 0x14 - test enable pad 43;
-- 0x15 - test enable pad 42;
-- 0x16 - test enable pad 41;
-- 0x17 - test enable pad 40;
-- 0x18 - test enable pad 63;
-- 0x19 - test enable pad 62;
-- 0x1A - test enable pad 61;
-- 0x1B - test enable pad 60;

-- 0x1C - test enable pad 70;
-- 0x1D - test enable pad 71;
-- 0x1E - test enable pad 72;
-- 0x1F - test enable pad 73;
-- 0x20 - test enable pad 50;
-- 0x21 - test enable pad 51;
-- 0x22 - test enable pad 52;
-- 0x23 - test enable pad 53;
-- 0x24 - test enable pad 30;
-- 0x25 - test enable pad 31;
-- 0x26 - test enable pad 32;
-- 0x27 - test enable pad 33;
-- 0x28 - test enable pad 10;
-- 0x29 - test enable pad 11;
-- 0x2A - test enable pad 12;
-- 0x2B - test enable pad 13;
--
-- 0x2C - output disable pad 03;
-- 0x2D - output disable pad 02;
-- 0x2E - output disable pad 01;
-- 0x2F - output disable pad 00;
-- 0x30 - output disable pad 23;
-- 0x31 - output disable pad 22;
-- 0x32 - output disable pad 21;
-- 0x33 - output disable pad 20;
-- 0x34 - output disable pad 43;
-- 0x35 - output disable pad 42;
-- 0x36 - output disable pad 41;
-- 0x37 - output disable pad 40;
-- 0x38 - output disable pad 63;
-- 0x39 - output disable pad 62;
-- 0x3A - output disable pad 61;
-- 0x3B - output disable pad 60;

-- 0x3C - output disable pad 70;
-- 0x3D - output disable pad 71;
-- 0x3E - output disable pad 72;
-- 0x3F - output disable pad 73;
-- 0x40 - output disable pad 50;
-- 0x41 - output disable pad 51;
-- 0x42 - output disable pad 52;
-- 0x43 - output disable pad 53;
-- 0x44 - output disable pad 30;
-- 0x45 - output disable pad 31;
-- 0x46 - output disable pad 32;
-- 0x47 - output disable pad 33;
-- 0x48 - output disable pad 10;
-- 0x49 - output disable pad 11;
-- 0x4A - output disable pad 12;
-- 0x4B - output disable pad 13;

-- 0x4C - enable calibration mode;
-- 0x4D - enable current compensation;
-- 0x4E - gain selection bit_0;
-- 0x4F - gain selection bit_1;
-- 0x50 - enable analog output;
-- 0x51 - enable individual mode;
-- 0x52 - negative signal;
-- 0x53 - time-over-threshold;

-- System pre-set
--------------------------
-- 0x55 - activate default (power-on) settings;

-- Control register
--------------------------
-- 0x56 - control register which defines a
--       sequence of commands, load PRO/A;
--------------------------------------------

-- Gain encoding:
--------------------------------------------
-- GS0  GS1  C_fb
--  0    0   1.0 pF  Default
--  0    1   0.3 pF  High
--  1    0   1.3 pF  Low
--  1    1   0.7 pF  Medium
--------------------------------------------

-- Data format:
--------------------------------------------

-- Control register
--------------------------
-- Bit_0 - reset PRO/A power;
-- Bit_1 - load  PRO/A;
-- Bit_2 - read  PRO/A;

-- Power supply watchdogs:
--------------------------
-- Bit_7 - +5.0 V. serial interface buffer;
-- Bit_6 - +3.3 V. ACEX / APEX shell;
-- Bit_5 - +2.5 V. ACEX core;
-- Bit_4 - +1.8 V. APEX core;
-- Bit_3 - -2.0 V. PRO/A digital;
-- Bit_2 - +2.0 V. PRO/A digital;
-- Bit_1 - -2.0 V. PRO/A analog;
-- Bit_0 - +2.0 V. PRO/A analog;

-- PRO/A settings and status
--------------------------
-- Bit_7 - Pro/A 13 = Sector_1, Plane 3;
-- Bit_6 - Pro/A 12 = Sector_1, Plane 2;
-- Bit_5 - Pro/A 11 = Sector_1, Plane 1;
-- Bit_4 - Pro/A 10 = Sector_1, Plane 0;

-- Bit_3 - Pro/A 03 = Sector_0, Plane 3;
-- Bit_2 - Pro/A 02 = Sector_0, Plane 2;
-- Bit_1 - Pro/A 01 = Sector_0, Plane 1;
-- Bit_0 - Pro/A 00 = Sector_0, Plane 0;
--------------------------------------------

-- Copyright I.Tsurin, University of Antwerpen,
-- on behalf of DESY.
--------------------------------------------
-- Preparing to the low energy run:

-- The serial data transmission was moved to the
-- APEX chip. The ACEX memory is being uccessed
-- through a parellel inter-chip link.

-- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-- The power-on reset has been omitted to improve
-- the system reliability. The board initialization
-- must proceed through the control register access

-- Changed on 18.02.07 by I.Tsurin, DESY Zeuthen
--------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;


--	OK. Here the entity starts...
--------------------------------------------
entity Newctr is

port(
	P50_Ok: in std_logic;	  -- Power watchdog On/Off = 1/0;
	P33_Ok: in std_logic;	  -- Power watchdog On/Off = 1/0;
	P25_Ok: in std_logic;	  -- Power watchdog On/Off = 1/0;
	P18_Ok: in std_logic;	  -- Power watchdog On/Off = 1/0;
	DS_Ok: in std_logic;	  -- Power watchdog On/Off = 1/0;
	DD_Ok: in std_logic;	  -- Power watchdog On/Off = 1/0;
	AS_Ok: in std_logic;	  -- Power watchdog On/Off = 1/0;
	AD_Ok: in std_logic;	  -- Power watchdog On/Off = 1/0;
	
	TCLK: in std_logic;		  -- HERA clock frequency (main clock);

	TXD: in std_logic;		  -- Serial interface output;
	RXD: in std_logic;		  -- serial interface input;

	LAM_PDS: out std_logic;   -- "Look at mee request" after download;
	LAM_APX: out std_logic;   -- gate for the trigger signals;

	DAT_STB: out std_logic;	  -- ASICs write strobe (common for all);
	STB_RES: out std_logic;	  -- ASICs write strobe (spare signal);
	
	Dig_PR: out std_logic;	  -- Digital power control (spare signal);
	Dig_NR: out std_logic;	  -- Digital power control (spare signal);
	Ana_PR: out std_logic;	  -- Analog power control (spare signal);
	Ana_NR: out std_logic;	  -- Analog power control (spare signal);

	RegIn03: out std_logic;	  --  |
	RegIn13: out std_logic;	  --  |
	RegIn02: out std_logic;	  --  |
	RegIn12: out std_logic;	  --  | Data sent to ASICs;
	RegIn01: out std_logic;	  --  |
	RegIn11: out std_logic;	  --  |
	RegIn00: out std_logic;	  --  |
	RegIn10: out std_logic;   --  |

	CH_PUMP0: out std_logic;  --  |
	CH_PUMP1: out std_logic;  --  |
	CH_PUMP2: out std_logic;  --  |
	CH_PUMP3: out std_logic;  --  | charge pumps
	CH_PUMP4: out std_logic;  --  | for thresholds;
	CH_PUMP5: out std_logic;  --  |
	CH_PUMP6: out std_logic;  --  |
	CH_PUMP7: out std_logic;  --  |
	
	RgOut00: in std_logic;	  --  |
	RgOut10: in std_logic;	  --  |
	RgOut01: in std_logic;	  --  |
	RgOut11: in std_logic;	  --  | Data reading from ASICs;
	RgOut02: in std_logic;	  --  |
	RgOut12: in std_logic;	  --  |
	RgOut03: in std_logic;	  --  |
	RgOut13: in std_logic;	  --  |
	
	Ana_NON: out std_logic;	  -- Analog power control (negative);
	Ana_PON: out std_logic;	  -- Analog power control (positive);
	Dig_NON: out std_logic;	  -- Digital power control (negative);
	Dig_PON: out std_logic;	  -- Digital power control (positive);

	CalEn: out std_logic;	  -- Cal. pulse Enable/Disable = 1/0;

	ACX_DAT: inout std_logic_vector(7 downto 0);
	ACX_ADR: in std_logic_vector(6 downto 0);
    ACX_WRI: in std_logic;
	ACX_CLK: in std_logic;

	Cglobal: in std_logic
	);

	attribute pinnum: string;

	attribute pinnum of P50_Ok: signal is "9";
	attribute pinnum of P33_Ok: signal is "10";
	attribute pinnum of P25_Ok: signal is "12";
	attribute pinnum of P18_Ok: signal is "13";
	attribute pinnum of DS_Ok: signal is "17";
	attribute pinnum of DD_Ok: signal is "18";
	attribute pinnum of AS_Ok: signal is "19";
	attribute pinnum of AD_Ok: signal is "20";
	
	attribute pinnum of TCLK: signal is "21";

	attribute pinnum of TXD: signal is "22";
	attribute pinnum of RXD: signal is "26";

	attribute pinnum of LAM_PDS: signal is "38";
	attribute pinnum of LAM_APX: signal is "72";

	attribute pinnum of DAT_STB: signal is "39";
	attribute pinnum of STB_RES: signal is "41";
	
	attribute pinnum of Dig_PR: signal is "49";
	attribute pinnum of Dig_NR: signal is "51";
	attribute pinnum of Ana_PR: signal is "59";
	attribute pinnum of Ana_NR: signal is "60";

	attribute pinnum of RegIn03: signal is "62";
	attribute pinnum of RegIn13: signal is "63";
	attribute pinnum of RegIn02: signal is "64";
	attribute pinnum of RegIn12: signal is "65";
	attribute pinnum of RegIn01: signal is "67";
	attribute pinnum of RegIn11: signal is "68";
	attribute pinnum of RegIn00: signal is "69";
	attribute pinnum of RegIn10: signal is "70";

	attribute pinnum of CH_PUMP7: signal is "92";
	attribute pinnum of CH_PUMP6: signal is "95";
	attribute pinnum of CH_PUMP5: signal is "96";
	attribute pinnum of CH_PUMP4: signal is "97";

	attribute pinnum of CH_PUMP3: signal is "91";
	attribute pinnum of CH_PUMP2: signal is "90";
	attribute pinnum of CH_PUMP1: signal is "89";
	attribute pinnum of CH_PUMP0: signal is "88";

	attribute pinnum of RgOut00: signal is "130";
	attribute pinnum of RgOut10: signal is "131";
	attribute pinnum of RgOut01: signal is "132";
	attribute pinnum of RgOut11: signal is "133";
	attribute pinnum of RgOut02: signal is "135";
	attribute pinnum of RgOut12: signal is "136";
	attribute pinnum of RgOut03: signal is "137";
	attribute pinnum of RgOut13: signal is "138";
	
	attribute pinnum of Ana_NON: signal is "109";
	attribute pinnum of Ana_PON: signal is "110";
	attribute pinnum of Dig_NON: signal is "111";
	attribute pinnum of Dig_PON: signal is "112";

	attribute pinnum of CalEn: signal is "140";

	attribute pinnum of ACX_DAT: signal is "36,33,32,31,30,29,28,23";
	attribute pinnum of ACX_ADR: signal is "117,102,101,100,99,98,81";
	attribute pinnum of ACX_WRI: signal is "80";
	attribute pinnum of ACX_CLK: signal is "73";

	attribute pinnum of Cglobal: signal is "27";
end;

architecture behavior of Newctr is

-- internal frequency and strobe pulse
--------------------------------------------
	signal STB_CNT: natural range 0 to 8191;	-- frequency division signal;
	signal Clock: std_logic;					-- Synchronizes RAM readout;
	signal Strobe: std_logic;					-- Latches data in DAC and ASICs;
--------------------------------------------

-- Initialization
--------------------------------------------
	signal DUM_RES: std_logic;
	signal RES_PUL: std_logic;
	signal RES_GTE: std_logic;
	signal INI_CNT: natural range 0 to 511;		-- for 0.5 seconds period with
												-- the 1 kHz internal frequency;
--------------------------------------------

-- Power variables
--------------------------------------------
	signal PWR_REG: std_logic_vector(7 downto 0);	-- Power supply failure latch;
	signal WDG_RES: std_logic;						-- Reset power watchdogs;
	signal Power: std_logic;						-- Vital power supply check;
	signal nFail: std_logic;						-- inhibits the watchdog reset;

	signal PWR_RDA: std_logic;
	signal PWR_ON: std_logic;
--------------------------------------------

-- Memory access variables
--------------------------------------------
	signal RDA_BUF: std_logic_vector(6 downto 0);
	signal REG_DAT: std_logic_vector(7 downto 0);
	signal REG_ADR: natural range 0 to 127;
--------------------------------------------

-- State machine variables
--------------------------------------------
	signal CTR_REG: std_logic_vector(2 downto 0);

	signal COM_INI: natural range 0 to 2047;	-- Start address for subroutine;
	signal COM_LIM: natural range 0 to 2047;	-- Stop address for subroutine;

	signal ACT_PUL: std_logic;
	signal COM_GTE: std_logic;					-- Counter increment enable;
	signal COM_LDE: std_logic;					-- Counter load enable;

	signal COM_CNT: natural range 0 to 2047;

-- COM_CNT =    2 - turn off an. and dig.;
-- COM_CNT =  511 - turn on analog supply;
-- COM_CNT = 1279 - turn on digital supply;
-- COM_CNT = 1824 - reset power watchdogs,
--					open gate for strobes;
-- COM_CNT = 1896 - close gate for strobes;
-- COM_CNT = 1897 - stop command counter;
--------------------------
-- COM_CNT = 1898 - start command counter
-- COM_CNT = 1899 - first PRO/A data, open gate for strobes;
--   ...
-- COM_CNT = 1963 - enable calibration regime;
--   ...
-- COM_CNT = 1970 - last PRO/A data;
-- COM_CNT = 1971 - close gate for strobes;
-- COM_CNT = 1972 - stop command counter;
--------------------------
-- COM_CNT = 1973 - clear Status register;
-- COM_CNT = 1974 - first PRO/A data, open gate for strobes;
--   ...
-- COM_CNT = 2045 - last PRO/A data;
-- COM_CNT = 2046 - close gate for strobes;
-- COM_CNT = 2047 - stop command counter;
--------------------------------------------

-- Executable module variables
--------------------------------------------
	signal HYB_GTE: std_logic;						-- Gate for the ASICs strobe;

	signal CMP_REG: std_logic_vector(7 downto 0);	-- Register for the online data check;

	signal SET_H7: std_logic;	--  | 
	signal SET_H6: std_logic;	--  |
	signal SET_H5: std_logic;	--  |
	signal SET_H4: std_logic;	--  | Current data for every hybrid;
	signal SET_H3: std_logic;	--  |
	signal SET_H2: std_logic;	--  |
	signal SET_H1: std_logic;	--  |
	signal SET_H0: std_logic;	--  |

 	signal GET_H7: std_logic;	--  |
	signal GET_H6: std_logic;	--  |
	signal GET_H5: std_logic;	--  |
	signal GET_H4: std_logic;	--  | Buffered readout data;
	signal GET_H3: std_logic;	--  |
	signal GET_H2: std_logic;	--  |
	signal GET_H1: std_logic;	--  |
	signal GET_H0: std_logic;	--  |
--------------------------------------------

-- Charge pump variables for thresholds
--------------------------------------------
	signal THR_R00: std_logic_vector(7 downto 0);
	signal THR_R01: std_logic_vector(7 downto 0);
	signal THR_R02: std_logic_vector(7 downto 0);
	signal THR_R03: std_logic_vector(7 downto 0);
	signal THR_R10: std_logic_vector(7 downto 0);
	signal THR_R11: std_logic_vector(7 downto 0);
	signal THR_R12: std_logic_vector(7 downto 0);
	signal THR_R13: std_logic_vector(7 downto 0);

	signal THR_CNT: natural range 0 to 255;
	signal THR_REG: std_logic_vector(7 downto 0);
--------------------------------------------

-- PRO/A data
--------------------------------------------
	signal TestEna03: std_logic_vector(7 downto 0);
	signal TestEna02: std_logic_vector(7 downto 0);
	signal TestEna01: std_logic_vector(7 downto 0);
	signal TestEna00: std_logic_vector(7 downto 0);
	signal TestEna23: std_logic_vector(7 downto 0);
	signal TestEna22: std_logic_vector(7 downto 0);
	signal TestEna21: std_logic_vector(7 downto 0);
	signal TestEna20: std_logic_vector(7 downto 0);
	signal TestEna43: std_logic_vector(7 downto 0);
	signal TestEna42: std_logic_vector(7 downto 0);
	signal TestEna41: std_logic_vector(7 downto 0);
	signal TestEna40: std_logic_vector(7 downto 0);
	signal TestEna63: std_logic_vector(7 downto 0);
	signal TestEna62: std_logic_vector(7 downto 0);
	signal TestEna61: std_logic_vector(7 downto 0);
	signal TestEna60: std_logic_vector(7 downto 0);
	signal TestEna70: std_logic_vector(7 downto 0);
	signal TestEna71: std_logic_vector(7 downto 0);
	signal TestEna72: std_logic_vector(7 downto 0);
	signal TestEna73: std_logic_vector(7 downto 0);
	signal TestEna50: std_logic_vector(7 downto 0);
	signal TestEna51: std_logic_vector(7 downto 0);
	signal TestEna52: std_logic_vector(7 downto 0);
	signal TestEna53: std_logic_vector(7 downto 0);
	signal TestEna30: std_logic_vector(7 downto 0);
	signal TestEna31: std_logic_vector(7 downto 0);
	signal TestEna32: std_logic_vector(7 downto 0);
	signal TestEna33: std_logic_vector(7 downto 0);
	signal TestEna10: std_logic_vector(7 downto 0);
	signal TestEna11: std_logic_vector(7 downto 0);
	signal TestEna12: std_logic_vector(7 downto 0);
	signal TestEna13: std_logic_vector(7 downto 0);

	signal OutDis03: std_logic_vector(7 downto 0);
	signal OutDis02: std_logic_vector(7 downto 0);
	signal OutDis01: std_logic_vector(7 downto 0);
	signal OutDis00: std_logic_vector(7 downto 0);
	signal OutDis23: std_logic_vector(7 downto 0);
	signal OutDis22: std_logic_vector(7 downto 0);
	signal OutDis21: std_logic_vector(7 downto 0);
	signal OutDis20: std_logic_vector(7 downto 0);
	signal OutDis43: std_logic_vector(7 downto 0);
	signal OutDis42: std_logic_vector(7 downto 0);
	signal OutDis41: std_logic_vector(7 downto 0);
	signal OutDis40: std_logic_vector(7 downto 0);
	signal OutDis63: std_logic_vector(7 downto 0);
	signal OutDis62: std_logic_vector(7 downto 0);
	signal OutDis61: std_logic_vector(7 downto 0);
	signal OutDis60: std_logic_vector(7 downto 0);
	signal OutDis70: std_logic_vector(7 downto 0);
	signal OutDis71: std_logic_vector(7 downto 0);
	signal OutDis72: std_logic_vector(7 downto 0);
	signal OutDis73: std_logic_vector(7 downto 0);
	signal OutDis50: std_logic_vector(7 downto 0);
	signal OutDis51: std_logic_vector(7 downto 0);
	signal OutDis52: std_logic_vector(7 downto 0);
	signal OutDis53: std_logic_vector(7 downto 0);
	signal OutDis30: std_logic_vector(7 downto 0);
	signal OutDis31: std_logic_vector(7 downto 0);
	signal OutDis32: std_logic_vector(7 downto 0);
	signal OutDis33: std_logic_vector(7 downto 0);
	signal OutDis10: std_logic_vector(7 downto 0);
	signal OutDis11: std_logic_vector(7 downto 0);
	signal OutDis12: std_logic_vector(7 downto 0);
	signal OutDis13: std_logic_vector(7 downto 0);

	signal CAL_ENA: std_logic_vector(7 downto 0);
	signal CUR_COM: std_logic_vector(7 downto 0);
	signal GAIN_S0: std_logic_vector(7 downto 0);
	signal GAIN_S1: std_logic_vector(7 downto 0);
	signal ANS_ENA: std_logic_vector(7 downto 0);
	signal IND_MOD: std_logic_vector(7 downto 0);
	signal NEG_POL: std_logic_vector(7 downto 0);
	signal TOT_MOD: std_logic_vector(7 downto 0);
--------------------------------------------

-- Data type conversion:
-- binary#7 -> natural
--------------------------------------------
	function BIT7_to_NUM(BIT_ARR: std_logic_vector(6 downto 0)) return natural is
		variable TEMP: natural range 0 to 127;
	begin
			TEMP:=0;
		for I in BIT_ARR'range loop
			TEMP:= TEMP * 2;
			if (BIT_ARR(I) = '1') then
				TEMP:= TEMP + 1;
			else
				null;
			end if;
		end loop;
	return TEMP;
	end BIT7_to_NUM;
--------------------------------------------

begin	

-- Permanent statements
--------------------------------------------
	DUM_RES <= '0';
-------------------------
	Dig_PR <= '0';
	Dig_NR <= '0';
	Ana_PR <= '0';
	Ana_NR <= '0';
	STB_RES <= '0';
-------------------------
	SET_H7 <= REG_DAT(7);
	SET_H6 <= REG_DAT(6);
	SET_H5 <= REG_DAT(5);
	SET_H4 <= REG_DAT(4);
	SET_H3 <= REG_DAT(3);
	SET_H2 <= REG_DAT(2);
	SET_H1 <= REG_DAT(1);
	SET_H0 <= REG_DAT(0);
--------------------------------------------

-- HERA clock frequency division (TCLK ->)
--------------------------------------------
	process(TCLK)
	begin
		if (TCLK'event and TCLK = '1') then
			STB_CNT <= STB_CNT + 1;
		end if;
	end process;
--------------------------------------------

-- Generating internal frequency
-- and PRO/A data strobe (TCLK <-)
--------------------------------------------
	process(TCLK, STB_CNT)
	begin
		if (TCLK'event and TCLK = '0') then
			if (STB_CNT = 0) then
				Clock  <= '1';
				Strobe <= '0';
			elsif (STB_CNT = 1638) then
				Clock  <= '1';
				Strobe <= '1';
			elsif (STB_CNT = 3276) then
				Clock  <= '1';
				Strobe <= '0';
			elsif (STB_CNT = 4914) then
				Clock  <= '0';
				Strobe <= '0';
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Start-up counter (Clock <-), (TCLK <-)
--------------------------------------------
	process(DUM_RES, Clock, RES_GTE)
	begin
		if (DUM_RES = '1') then
			INI_CNT <= 0;
		elsif (Clock'event and Clock = '0') then
			if (RES_GTE = '1') then
				INI_CNT <= INI_CNT + 1;
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Start-up gate
-- (Clock ->), (TCLK <-)
--------------------------------------------
	process(DUM_RES, Clock, INI_CNT)
	begin
		if (DUM_RES = '1') then
			RES_GTE <= '1';
		elsif (Clock'event and Clock = '1') then
			if (INI_CNT = 511) then
				RES_GTE <= '0';
			else
				RES_GTE <= '1';
			end if;
		end if;
	end process;
--------------------------------------------

-- Start-up reset pulse
-- (Clock <-), (TCLK <-)
--------------------------------------------
	process(RES_GTE, Clock)
	begin
		if (RES_GTE = '0') then
			RES_PUL <= '0';
		elsif (Clock'event and Clock = '0') then
			RES_PUL <= '1';
		end if;
	end process;
--------------------------------------------

-- Assign registers (TCLK ->)
--------------------------------------------
	process(RES_PUL, ACX_CLK, COM_GTE, ACX_WRI, REG_ADR, ACX_DAT)
	begin
		if (RES_PUL = '1' or
		   (ACX_CLK = '1' and COM_GTE = '0' and ACX_WRI = '1' and REG_ADR = 85)) then
			CTR_REG <= "111";		-- Reset power, load & check;

			THR_R00 <= "11001000";	-- -200 mV default threshold;
			THR_R01 <= "11001000";	-- -200 mV default threshold;
			THR_R02 <= "11001000";	-- -200 mV default threshold;
			THR_R03 <= "11001000";	-- -200 mV default threshold;
			THR_R10 <= "11001000";	-- -200 mV default threshold;
			THR_R11 <= "11001000";	-- -200 mV default threshold;
			THR_R12 <= "11001000";	-- -200 mV default threshold;
			THR_R13 <= "11001000";	-- -200 mV default threshold;

			TestEna03 <= (others => '0');
			TestEna02 <= (others => '0');
			TestEna01 <= (others => '0');
			TestEna00 <= (others => '0');
			TestEna23 <= (others => '0');
			TestEna22 <= (others => '0');
			TestEna21 <= (others => '0');
			TestEna20 <= (others => '0');
			TestEna43 <= (others => '0');
			TestEna42 <= (others => '0');
			TestEna41 <= (others => '0');
			TestEna40 <= (others => '0');
			TestEna63 <= (others => '0');
			TestEna62 <= (others => '0');
			TestEna61 <= (others => '0');
			TestEna60 <= (others => '0');

			TestEna70 <= (others => '0');
			TestEna71 <= (others => '0');
			TestEna72 <= (others => '0');
			TestEna73 <= (others => '0');
			TestEna50 <= (others => '0');
			TestEna51 <= (others => '0');
			TestEna52 <= (others => '0');
			TestEna53 <= (others => '0');
			TestEna30 <= (others => '0');
			TestEna31 <= (others => '0');
			TestEna32 <= (others => '0');
			TestEna33 <= (others => '0');
			TestEna10 <= (others => '0');
			TestEna11 <= (others => '0');
			TestEna12 <= (others => '0');
			TestEna13 <= (others => '0');

			OutDis03 <= (others => '0');
			OutDis02 <= (others => '0');
			OutDis01 <= (others => '0');
			OutDis00 <= (others => '0');
			OutDis23 <= (others => '0');
			OutDis22 <= (others => '0');
			OutDis21 <= (others => '0');
			OutDis20 <= (others => '0');
			OutDis43 <= (others => '0');
			OutDis42 <= (others => '0');
			OutDis41 <= (others => '0');
			OutDis40 <= (others => '0');
			OutDis63 <= (others => '0');
			OutDis62 <= (others => '0');
			OutDis61 <= (others => '0');
			OutDis60 <= (others => '0');

			OutDis70 <= (others => '0');
			OutDis71 <= (others => '0');
			OutDis72 <= (others => '0');
			OutDis73 <= (others => '0');
			OutDis50 <= (others => '0');
			OutDis51 <= (others => '0');
			OutDis52 <= (others => '0');
			OutDis53 <= (others => '0');
			OutDis30 <= (others => '0');
			OutDis31 <= (others => '0');
			OutDis32 <= (others => '0');
			OutDis33 <= (others => '0');
			OutDis10 <= (others => '0');
			OutDis11 <= (others => '0');
			OutDis12 <= (others => '0');
			OutDis13 <= (others => '0');

			CAL_ENA <= (others => '0');
			CUR_COM <= (others => '0');
			GAIN_S0 <= (others => '0');
			GAIN_S1 <= (others => '0');
			ANS_ENA <= (others => '0');
			IND_MOD <= (others => '0');
			NEG_POL <= (others => '0');
			TOT_MOD <= (others => '0');
		elsif (ACX_CLK'event and ACX_CLK = '1') then
			if (COM_GTE = '0' and ACX_WRI = '1') then
				case REG_ADR is
					when 86 =>
						CTR_REG(2 downto 0) <= ACX_DAT(2 downto 0);

					when 3 =>
						THR_R00 <= ACX_DAT;
					when 4 =>
						THR_R01 <= ACX_DAT;
					when 5 =>
						THR_R02 <= ACX_DAT;
					when 6 =>
						THR_R03 <= ACX_DAT;
					when 7 =>
						THR_R10 <= ACX_DAT;
					when 8 =>
						THR_R11 <= ACX_DAT;
					when 9 =>
						THR_R12 <= ACX_DAT;
					when 10 =>
						THR_R13 <= ACX_DAT;

					when 12 =>
						TestEna03 <= ACX_DAT;
					when 13 =>
						TestEna02 <= ACX_DAT;
					when 14 =>
						TestEna01 <= ACX_DAT;
					when 15 =>
						TestEna00 <= ACX_DAT;
					when 16 =>
						TestEna23 <= ACX_DAT;
					when 17 =>
						TestEna22 <= ACX_DAT;
					when 18 =>
						TestEna21 <= ACX_DAT;
					when 19 =>
						TestEna20 <= ACX_DAT;
					when 20 =>
						TestEna43 <= ACX_DAT;
					when 21 =>
						TestEna42 <= ACX_DAT;
					when 22 =>
						TestEna41 <= ACX_DAT;
					when 23 =>
						TestEna40 <= ACX_DAT;
					when 24 =>
						TestEna63 <= ACX_DAT;
					when 25 =>
						TestEna62 <= ACX_DAT;
					when 26 =>
						TestEna61 <= ACX_DAT;
					when 27 =>
						TestEna60 <= ACX_DAT;

					when 28 =>
						TestEna70 <= ACX_DAT;
					when 29 =>
						TestEna71 <= ACX_DAT;
					when 30 =>
						TestEna72 <= ACX_DAT;
					when 31 =>
						TestEna73 <= ACX_DAT;
					when 32 =>
						TestEna50 <= ACX_DAT;
					when 33 =>
						TestEna51 <= ACX_DAT;
					when 34 =>
						TestEna52 <= ACX_DAT;
					when 35 =>
						TestEna53 <= ACX_DAT;
					when 36 =>
						TestEna30 <= ACX_DAT;
					when 37 =>
						TestEna31 <= ACX_DAT;
					when 38 =>
						TestEna32 <= ACX_DAT;
					when 39 =>
						TestEna33 <= ACX_DAT;
					when 40 =>
						TestEna10 <= ACX_DAT;
					when 41 =>
						TestEna11 <= ACX_DAT;
					when 42 =>
						TestEna12 <= ACX_DAT;
					when 43 =>
						TestEna13 <= ACX_DAT;

					when 44 =>
						OutDis03 <= ACX_DAT;
					when 45 =>
						OutDis02 <= ACX_DAT;
					when 46 =>
						OutDis01 <= ACX_DAT;
					when 47 =>
						OutDis00 <= ACX_DAT;
					when 48 =>
						OutDis23 <= ACX_DAT;
					when 49 =>
						OutDis22 <= ACX_DAT;
					when 50 =>
						OutDis21 <= ACX_DAT;
					when 51 =>
						OutDis20 <= ACX_DAT;
					when 52 =>
						OutDis43 <= ACX_DAT;
					when 53 =>
						OutDis42 <= ACX_DAT;
					when 54 =>
						OutDis41 <= ACX_DAT;
					when 55 =>
						OutDis40 <= ACX_DAT;
					when 56 =>
						OutDis63 <= ACX_DAT;
					when 57 =>
						OutDis62 <= ACX_DAT;
					when 58 =>
						OutDis61 <= ACX_DAT;
					when 59 =>
						OutDis60 <= ACX_DAT;

					when 60 =>
						OutDis70 <= ACX_DAT;
					when 61 =>
						OutDis71 <= ACX_DAT;
					when 62 =>
						OutDis72 <= ACX_DAT;
					when 63 =>
						OutDis73 <= ACX_DAT;
					when 64 =>
						OutDis50 <= ACX_DAT;
					when 65 =>
						OutDis51 <= ACX_DAT;
					when 66 =>
						OutDis52 <= ACX_DAT;
					when 67 =>
						OutDis53 <= ACX_DAT;
					when 68 =>
						OutDis30 <= ACX_DAT;
					when 69 =>
						OutDis31 <= ACX_DAT;
					when 70 =>
						OutDis32 <= ACX_DAT;
					when 71 =>
						OutDis33 <= ACX_DAT;
					when 72 =>
						OutDis10 <= ACX_DAT;
					when 73 =>
						OutDis11 <= ACX_DAT;
					when 74 =>
						OutDis12 <= ACX_DAT;
					when 75 =>
						OutDis13 <= ACX_DAT;

					when 76 =>
						CAL_ENA <= ACX_DAT;
					when 77 =>
						CUR_COM <= ACX_DAT;
					when 78 =>
						GAIN_S0 <= ACX_DAT;
					when 79 =>
						GAIN_S1 <= ACX_DAT;
					when 80 =>
						ANS_ENA <= ACX_DAT;
					when 81 =>
						IND_MOD <= ACX_DAT;
					when 82 =>
						NEG_POL <= ACX_DAT;
					when 83 =>
						TOT_MOD <= ACX_DAT;
					when others =>
						null;
				end case;
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Select registers (TCLK <-)
--------------------------------------------
	process(REG_ADR,
			CTR_REG, PWR_REG, CMP_REG,
			THR_R00, THR_R01, THR_R02, THR_R03,
			THR_R10, THR_R11, THR_R12, THR_R13,
			TestEna03, TestEna02, TestEna01, TestEna00,
			TestEna23, TestEna22, TestEna21, TestEna20,
			TestEna43, TestEna42, TestEna41, TestEna40,
			TestEna63, TestEna62, TestEna61, TestEna60,
			TestEna70, TestEna71, TestEna72, TestEna73,
			TestEna50, TestEna51, TestEna52, TestEna53,
			TestEna30, TestEna31, TestEna32, TestEna33,
			TestEna10, TestEna11, TestEna12, TestEna13,
			OutDis03, OutDis02, OutDis01, OutDis00,
			OutDis23, OutDis22, OutDis21, OutDis20,
			OutDis43, OutDis42, OutDis41, OutDis40,
			OutDis63, OutDis62, OutDis61, OutDis60,
			OutDis70, OutDis71, OutDis72, OutDis73,
			OutDis50, OutDis51, OutDis52, OutDis53,
			OutDis30, OutDis31, OutDis32, OutDis33,
			OutDis10, OutDis11, OutDis12, OutDis13,
			CAL_ENA, CUR_COM, GAIN_S0, GAIN_S1,
			ANS_ENA, IND_MOD, NEG_POL, TOT_MOD)
	begin
		case REG_ADR is
			when 86 =>
				REG_DAT(7 downto 3) <= "00000";
				REG_DAT(2 downto 0) <= CTR_REG(2 downto 0);

			when 1 =>
				REG_DAT <= PWR_REG;
			when 2 =>
				REG_DAT <= CMP_REG;

			when 3 =>
				REG_DAT <= THR_R00;
			when 4 =>
				REG_DAT <= THR_R01;
			when 5 =>
				REG_DAT <= THR_R02;
			when 6 =>
				REG_DAT <= THR_R03;
			when 7 =>
				REG_DAT <= THR_R10;
			when 8 =>
				REG_DAT <= THR_R11;
			when 9 =>
				REG_DAT <= THR_R12;
			when 10 =>
				REG_DAT <= THR_R13;

			when 12 =>
				REG_DAT <= TestEna03;
			when 13 =>
				REG_DAT <= TestEna02;
			when 14 =>
				REG_DAT <= TestEna01;
			when 15 =>
				REG_DAT <= TestEna00;
			when 16 =>
				REG_DAT <= TestEna23;
			when 17 =>
				REG_DAT <= TestEna22;
			when 18 =>
				REG_DAT <= TestEna21;
			when 19 =>
				REG_DAT <= TestEna20;
			when 20 =>
				REG_DAT <= TestEna43;
			when 21 =>
				REG_DAT <= TestEna42;
			when 22 =>
				REG_DAT <= TestEna41;
			when 23 =>
				REG_DAT <= TestEna40;
			when 24 =>
				REG_DAT <= TestEna63;
			when 25 =>
				REG_DAT <= TestEna62;
			when 26 =>
				REG_DAT <= TestEna61;
			when 27 =>
				REG_DAT <= TestEna60;

			when 28 =>
				REG_DAT <= TestEna70;
			when 29 =>
				REG_DAT <= TestEna71;
			when 30 =>
				REG_DAT <= TestEna72;
			when 31 =>
				REG_DAT <= TestEna73;
			when 32 =>
				REG_DAT <= TestEna50;
			when 33 =>
				REG_DAT <= TestEna51;
			when 34 =>
				REG_DAT <= TestEna52;
			when 35 =>
				REG_DAT <= TestEna53;
			when 36 =>
				REG_DAT <= TestEna30;
			when 37 =>
				REG_DAT <= TestEna31;
			when 38 =>
				REG_DAT <= TestEna32;
			when 39 =>
				REG_DAT <= TestEna33;
			when 40 =>
				REG_DAT <= TestEna10;
			when 41 =>
				REG_DAT <= TestEna11;
			when 42 =>
				REG_DAT <= TestEna12;
			when 43 =>
				REG_DAT <= TestEna13;

			when 44 =>
				REG_DAT <= OutDis03;
			when 45 =>
				REG_DAT <= OutDis02;
			when 46 =>
				REG_DAT <= OutDis01;
			when 47 =>
				REG_DAT <= OutDis00;
			when 48 =>
				REG_DAT <= OutDis23;
			when 49 =>
				REG_DAT <= OutDis22;
			when 50 =>
				REG_DAT <= OutDis21;
			when 51 =>
				REG_DAT <= OutDis20;
			when 52 =>
				REG_DAT <= OutDis43;
			when 53 =>
				REG_DAT <= OutDis42;
			when 54 =>
				REG_DAT <= OutDis41;
			when 55 =>
				REG_DAT <= OutDis40;
			when 56 =>
				REG_DAT <= OutDis63;
			when 57 =>
				REG_DAT <= OutDis62;
			when 58 =>
				REG_DAT <= OutDis61;
			when 59 =>
				REG_DAT <= OutDis60;

			when 60 =>
				REG_DAT <= OutDis70;
			when 61 =>
				REG_DAT <= OutDis71;
			when 62 =>
				REG_DAT <= OutDis72;
			when 63 =>
				REG_DAT <= OutDis73;
			when 64 =>
				REG_DAT <= OutDis50;
			when 65 =>
				REG_DAT <= OutDis51;
			when 66 =>
				REG_DAT <= OutDis52;
			when 67 =>
				REG_DAT <= OutDis53;
			when 68 =>
				REG_DAT <= OutDis30;
			when 69 =>
				REG_DAT <= OutDis31;
			when 70 =>
				REG_DAT <= OutDis32;
			when 71 =>
				REG_DAT <= OutDis33;
			when 72 =>
				REG_DAT <= OutDis10;
			when 73 =>
				REG_DAT <= OutDis11;
			when 74 =>
				REG_DAT <= OutDis12;
			when 75 =>
				REG_DAT <= OutDis13;

			when 76 =>
				REG_DAT <= CAL_ENA;
			when 77 =>
				REG_DAT <= CUR_COM;
			when 78 =>
				REG_DAT <= GAIN_S0;
			when 79 =>
				REG_DAT <= GAIN_S1;
			when 80 =>
				REG_DAT <= ANS_ENA;
			when 81 =>
				REG_DAT <= IND_MOD;
			when 82 =>
				REG_DAT <= NEG_POL;
			when 83 =>
				REG_DAT <= TOT_MOD;
			when others =>
				REG_DAT <= (others => '0');
		end case;
	end process;
--------------------------------------------

-- Command launch pulse (TCLK ->)
--------------------------------------------
	process(COM_LDE, ACX_CLK, COM_GTE, ACX_WRI, REG_ADR)
	begin
		if (COM_LDE = '1') then
			ACT_PUL <= '0';
		elsif (ACX_CLK'event and ACX_CLK = '0') then
			if (COM_GTE = '0' and ACX_WRI = '1' and REG_ADR = 86) then
				ACT_PUL <= '1';
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Gate for the command counter
-- (Clock ->), (TCLK <-)
--------------------------------------------
	process(Clock, RES_PUL, ACT_PUL, COM_CNT, COM_LIM)
	begin
		if (Clock'event and Clock = '1') then
			if (RES_PUL = '1' or ACT_PUL = '1') then
				COM_GTE <= '1';
			elsif (COM_CNT = COM_LIM) then
				COM_GTE <= '0';
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Command counter (Clock <-), (TCLK <-)
--------------------------------------------
	process(Clock, RES_GTE, COM_LDE, COM_INI, COM_GTE)
	begin
		if (Clock'event and Clock = '0') then
			if (RES_GTE = '1') then
				COM_CNT <= 0;
			elsif (COM_LDE = '1') then
				COM_CNT <= COM_INI;
			elsif (COM_GTE = '1') then
				COM_CNT <= COM_CNT + 1;
			else
				COM_CNT <= 0;
			end if;
		end if;
	end process;
--------------------------------------------

-- Counter load enable (Clock ->), (TCLK <-)
--------------------------------------------
	process(Clock, COM_CNT)
	begin
		if (Clock'event and Clock = '1') then
			if (COM_CNT = 1) then
				COM_LDE <= '1';
			else
				COM_LDE <= '0';
			end if;
		end if;
	end process;
--------------------------------------------

-- Counter limits
--------------------------------------------
	process(CTR_REG)
	begin
		case CTR_REG is
			when "001" =>		-- reset only
				COM_INI <= 2;
				COM_LIM <= 1897;
			when "010" =>		-- load ASICs only
				COM_INI <= 1898;
				COM_LIM <= 1972;
			when "011" =>		-- reset and load ASICs
				COM_INI <= 2;
				COM_LIM <= 1972;
			when "100" =>		-- read ASICs only
				COM_INI <= 1973;
				COM_LIM <= 2047;
			when "101" =>		-- reset and read ASICs
				COM_INI <= 2;	-- (impractical action)
				COM_LIM <= 2047;
			when "110" =>		-- load and read ASICs
				COM_INI <= 1898;
				COM_LIM <= 2047;
			when "111" =>		-- reset, load and read
				COM_INI <= 2;
				COM_LIM <= 2047;
			when others =>		-- do nothing;
				COM_INI <= 2047;
				COM_LIM <= 2047;
		end case;
	end process;
--------------------------------------------

-- LAM generation (TCLK <-)
--------------------------------------------
	LAM_APX <= not COM_GTE;
	LAM_PDS <= Power and (not COM_GTE);
--------------------------------------------

-- Analog distribution box
--------------------------------------------
	process(Clock, COM_CNT)
	begin
		if (Clock'event and Clock = '1') then
			if (COM_CNT = 2) then
				Ana_PON <= '0';
				Ana_NON <= '0';
			elsif (COM_CNT = 511) then
				Ana_PON <= '1';
				Ana_NON <= '1';
			else
				null;
			end if;
		end if;
	end process;	
--------------------------------------------
	
-- Digital distribution box
--------------------------------------------
	process(Clock, COM_CNT, AS_Ok, AD_Ok)
	begin
		if (Clock'event and Clock = '1') then
			if (COM_CNT = 2) then
				Dig_PON <= '0';
				Dig_NON <= '0';
			elsif (COM_CNT = 1279 and AS_Ok = '1' and AD_Ok = '1') then
				Dig_PON <= '1';
				Dig_NON <= '1';
			else
				null;
			end if;
		end if;
	end process;				
--------------------------------------------

-- Power failure latch
--------------------------------------------
	process(P50_Ok, WDG_RES)
	begin
		if (P50_Ok = '0') then
			PWR_REG(7) <= '0';
		elsif (WDG_RES'event and WDG_RES = '1') then
			PWR_REG(7) <= '1';
		end if;
	end process;
--------------------------
	process(P33_Ok, WDG_RES)
	begin
		if (P33_Ok = '0') then
			PWR_REG(6) <= '0';
		elsif (WDG_RES'event and WDG_RES = '1') then
			PWR_REG(6) <= '1';
		end if;
	end process;
--------------------------
	process(P25_Ok, WDG_RES)
	begin
		if (P25_Ok = '0') then
			PWR_REG(5) <= '0';
		elsif (WDG_RES'event and WDG_RES = '1') then
			PWR_REG(5) <= '1';
		end if;
	end process;
--------------------------
	process(P18_Ok, WDG_RES)
	begin
		if (P18_Ok = '0') then
			PWR_REG(4) <= '0';
		elsif (WDG_RES'event and WDG_RES = '1') then
			PWR_REG(4) <= '1';
		end if;
	end process;
--------------------------
	process(DS_Ok, WDG_RES)
	begin
		if (DS_Ok = '0') then
			PWR_REG(3) <= '0';
		elsif (WDG_RES'event and WDG_RES = '1') then
			PWR_REG(3) <= '1';
		end if;
	end process;
--------------------------
	process(DD_Ok, WDG_RES)
	begin
		if (DD_Ok = '0') then
			PWR_REG(2) <= '0';
		elsif (WDG_RES'event and WDG_RES = '1') then
			PWR_REG(2) <= '1';
		end if;
	end process;
--------------------------
	process(AS_Ok, WDG_RES)
	begin
		if (AS_Ok = '0') then
			PWR_REG(1) <= '0';
		elsif (WDG_RES'event and WDG_RES = '1') then
			PWR_REG(1) <= '1';
		end if;
	end process;
--------------------------
	process(AD_Ok, WDG_RES)
	begin
		if (AD_Ok = '0') then
			PWR_REG(0) <= '0';
		elsif (WDG_RES'event and WDG_RES = '1') then
			PWR_REG(0) <= '1';
		end if;
	end process;
--------------------------------------------

-- Clear watchdogs after ASICs power-on (TCLK <-)
--------------------------------------------
	process(nFail, Clock, COM_CNT)
	begin
		if (nFail = '0') then
			PWR_ON <= '0';
		elsif (Clock'event and Clock = '1') then
			if (COM_CNT = 1896) then
				PWR_ON <= '1';
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Clear watchdogs after the power
-- status readout by ACX_CLK (TCLK ->)
--------------------------------------------
	process(nFail, ACX_CLK, COM_GTE, ACX_WRI, REG_ADR)
	begin
		if (nFail = '0') then
			PWR_RDA <= '0';
		elsif (ACX_CLK'event and ACX_CLK = '0') then
			if (COM_GTE = '1' and ACX_WRI = '0' and REG_ADR = 1) then
				PWR_RDA <= '1';
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- combine clear signals
--------------------------------------------
	WDG_RES <= PWR_ON or PWR_RDA;
--------------------------------------------

-- Power control
--------------------------------------------
	nFail <= P50_Ok and P33_Ok and P25_Ok and P18_Ok
		 and DS_Ok and DD_Ok and AS_Ok and AD_Ok;
--------------------------
	Power <= PWR_REG(7) and PWR_REG(6) and PWR_REG(5) and PWR_REG(4)
		 and PWR_REG(3) and PWR_REG(2) and PWR_REG(1) and PWR_REG(0);
--------------------------------------------

-- Threshold's update loop
--------------------------------------------
	process(TCLK)
	begin
		if (TCLK'event and TCLK = '1') then
			THR_CNT <= THR_CNT + 1;
		end if;
	end process;
--------------------------
	THR_REG <= conv_std_logic_vector(THR_CNT, 8);
--------------------------------------------

-- Charge pump strobe (TCLK <-)
-- (register assignment TCLK ->) OK
--------------------------------------------
	process(THR_R00, TCLK, THR_REG)
	begin
		if (THR_R00 = "11111111") then
			CH_PUMP0 <= '1';
		elsif (TCLK'event and TCLK = '0') then
			if (THR_REG = THR_R00) then
				CH_PUMP0 <= '0';
			elsif (THR_REG = "00000000") then
				CH_PUMP0 <= '1';
			else
				null;
			end if;
		end if;
	end process;
--------------------------
	process(THR_R01, TCLK, THR_REG)
	begin
		if (THR_R01 = "11111111") then
			CH_PUMP1 <= '1';
		elsif (TCLK'event and TCLK = '0') then
			if (THR_REG = THR_R01) then
				CH_PUMP1 <= '0';
			elsif (THR_REG = "00000000") then
				CH_PUMP1 <= '1';
			else
				null;
			end if;
		end if;
	end process;
--------------------------
	process(THR_R02, TCLK, THR_REG)
	begin
		if (THR_R02 = "11111111") then
			CH_PUMP2 <= '1';
		elsif (TCLK'event and TCLK = '0') then
			if (THR_REG = THR_R02) then
				CH_PUMP2 <= '0';
			elsif (THR_REG = "00000000") then
				CH_PUMP2 <= '1';
			else
				null;
			end if;
		end if;
	end process;
--------------------------
	process(THR_R03, TCLK, THR_REG)
	begin
		if (THR_R03 = "11111111") then
			CH_PUMP3 <= '1';
		elsif (TCLK'event and TCLK = '0') then
			if (THR_REG = THR_R03) then
				CH_PUMP3 <= '0';
			elsif (THR_REG = "00000000") then
				CH_PUMP3 <= '1';
			else
				null;
			end if;
		end if;
	end process;
--------------------------
	process(THR_R10, TCLK, THR_REG)
	begin
		if (THR_R10 = "11111111") then
			CH_PUMP4 <= '1';
		elsif (TCLK'event and TCLK = '0') then
			if (THR_REG = THR_R10) then
				CH_PUMP4 <= '0';
			elsif (THR_REG = "00000000") then
				CH_PUMP4 <= '1';
			else
				null;
			end if;
		end if;
	end process;
--------------------------
	process(THR_R11, TCLK, THR_REG)
	begin
		if (THR_R11 = "11111111") then
			CH_PUMP5 <= '1';
		elsif (TCLK'event and TCLK = '0') then
			if (THR_REG = THR_R11) then
				CH_PUMP5 <= '0';
			elsif (THR_REG = "00000000") then
				CH_PUMP5 <= '1';
			else
				null;
			end if;
		end if;
	end process;
--------------------------
	process(THR_R12, TCLK, THR_REG)
	begin
		if (THR_R12 = "11111111") then
			CH_PUMP6 <= '1';
		elsif (TCLK'event and TCLK = '0') then
			if (THR_REG = THR_R12) then
				CH_PUMP6 <= '0';
			elsif (THR_REG = "00000000") then
				CH_PUMP6 <= '1';
			else
				null;
			end if;
		end if;
	end process;
--------------------------
	process(THR_R13, TCLK, THR_REG)
	begin
		if (THR_R13 = "11111111") then
			CH_PUMP7 <= '1';
		elsif (TCLK'event and TCLK = '0') then
			if (THR_REG = THR_R13) then
				CH_PUMP7 <= '0';
			elsif (THR_REG = "00000000") then
				CH_PUMP7 <= '1';
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- ASICs supervisor
--------------------------------------------
	process(Clock, COM_CNT,
			SET_H7, SET_H6, SET_H5, SET_H4,
			SET_H3, SET_H2, SET_H1, SET_H0,
			GET_H7, GET_H6, GET_H5, GET_H4,
			GET_H3, GET_H2, GET_H1, GET_H0)
	begin
		if (Clock'event and Clock = '1') then
			case COM_CNT is
				when 1899 to 1970 =>
					RegIn13 <= SET_H7;		--  |
					RegIn12 <= SET_H6;		--  |
					RegIn11 <= SET_H5;		--  |
					RegIn10 <= SET_H4;		--  | Load data from RAM

					RegIn03 <= SET_H3;		--  |
					RegIn02 <= SET_H2;		--  |
					RegIn01 <= SET_H1;		--  |
					RegIn00 <= SET_H0;		--  |
				when 1974 to 2045 =>
					RegIn13 <= GET_H7;		--  |
					RegIn12 <= GET_H6;		--  |
					RegIn11 <= GET_H5;		--  |
					RegIn10 <= GET_H4;		--  | Rewrite ASICs data

					RegIn03 <= GET_H3;		--  |
					RegIn02 <= GET_H2;		--  |
					RegIn01 <= GET_H1;		--  |
					RegIn00 <= GET_H0;		--  |
				when others =>
					RegIn13 <= '0';
					RegIn12 <= '0';
					RegIn11 <= '0';
					RegIn10 <= '0';

					RegIn03 <= '0';
					RegIn02 <= '0';
					RegIn01 <= '0';
					RegIn00 <= '0';
			end case;
		end if;
	end process;
--------------------------------------------

-- Generating the data strobe (Clock ->)
-- (reference values are 12 and 84 dec.)
--------------------------------------------
	process(Clock, COM_CNT)
	begin
		if (Clock'event and Clock = '1') then
			if (COM_CNT = 1824 or COM_CNT = 1899 or COM_CNT = 1974) then
				HYB_GTE <= '1';
			elsif (COM_CNT = 1896 or COM_CNT = 1971 or COM_CNT = 2046) then
				HYB_GTE <= '0';
			else
				null;
			end if;
		end if;				
	end process;
--------------------------
	DAT_STB <= Strobe and HYB_GTE;
--------------------------------------------

-- Calibration pulse enable (Strobe ->) (TCLK <-)
--------------------------------------------
	process(Strobe, COM_CNT, REG_DAT)
	begin
		if (Strobe'event and Strobe = '1') then
			if (COM_CNT = 1963) then
				if (REG_DAT = "00000000") then
					CalEn <= '0';
				else
					CalEn <= '1';
				end if;
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- ASICs readout buffer (Clock <-)
-- (latches the previous result)
--------------------------------------------
	process(Clock,
			RgOut13, RgOut12, RgOut11, RgOut10,
			RgOut03, RgOut02, RgOut01,  RgOut00)
	begin
		if (Clock'event and Clock = '0') then
			GET_H7 <= RgOut13;
			GET_H6 <= RgOut12;
			GET_H5 <= RgOut11;
			GET_H4 <= RgOut10;

			GET_H3 <= RgOut03;
			GET_H2 <= RgOut02;
			GET_H1 <= RgOut01;
			GET_H0 <= RgOut00;
		end if;
	end process;
--------------------------------------------

-- Perform ASIC and RAM comparison
--------------------------------------------
	process (Strobe, COM_CNT,
			SET_H7, SET_H6, SET_H5, SET_H4,
			SET_H3, SET_H2, SET_H1, SET_H0,
			GET_H7, GET_H6, GET_H5, GET_H4,
			GET_H3, GET_H2, GET_H1, GET_H0)
	begin
		if (Strobe'event and Strobe = '1') then
			if (COM_CNT = 1973) then
				CMP_REG <= (others => '1');
			elsif (1974 <= COM_CNT and COM_CNT <= 2045) then
				if (GET_H7 /= SET_H7) then CMP_REG(7) <= '0';
					else null; end if;
				if (GET_H6 /= SET_H6) then CMP_REG(6) <= '0';
					else null; end if;
				if (GET_H5 /= SET_H5) then CMP_REG(5) <= '0';
						else null; end if;
				if (GET_H4 /= SET_H4) then CMP_REG(4) <= '0';
					else null; end if;
				if (GET_H3 /= SET_H3) then CMP_REG(3) <= '0';
					else null; end if;
				if (GET_H2 /= SET_H2) then CMP_REG(2) <= '0';
					else null; end if;
				if (GET_H1 /= SET_H1) then CMP_REG(1) <= '0';
					else null; end if;
				if (GET_H0 /= SET_H0) then CMP_REG(0) <= '0';
					else null; end if;
			else
				null;
			end if;
		end if;
	end process;
--------------------------------------------

-- Computing readout address
-- for the state machine
--------------------------------------------
	process(COM_CNT)
	begin
		case COM_CNT is
			when 1899 to 1971 =>
				RDA_BUF <= conv_std_logic_vector((COM_CNT - 1887), 7);
			when 1974 to 2046 =>
				RDA_BUF <= conv_std_logic_vector((COM_CNT - 1887 - 75), 7);
			when others =>
				RDA_BUF <= (others => '0');
		end case;
	end process;
--------------------------------------------

-- Multiplexing the readout address
--------------------------------------------
	process(COM_GTE, RDA_BUF, ACX_ADR)
	begin
		if (COM_GTE = '1') then
			REG_ADR <= BIT7_to_NUM(RDA_BUF);
		else
			REG_ADR <= BIT7_to_NUM(ACX_ADR);
		end if;
	end process;
--------------------------------------------

-- Data output through bidirectional port
--------------------------------------------
	process(ACX_WRI, REG_DAT)
	begin
		if (ACX_WRI = '0') then
			ACX_DAT <= REG_DAT;
		else
			ACX_DAT <= (others => 'Z');
		end if;
	end process;
--------------------------------------------

end;