The BST trigger system required a new front-end with enhanced signal-to-noise (SN) characteristics. The signal from the minimum-ionizing particle (MIP) crossing normally the silicon wafer (380 um), amounts to 25000 electron-hole pairs on average. The number of free charge carriers, produced by one MIP in a thin (with respect to the particle radiation length) absorber, obeys the Landau distribution law. The statistical fluctuation of this number is a random noise component. The systematic (electrical) noise is a superposition of the detector's noise, the inherent noise of the readout chip and the pickup noise. Both, thermal and shot noises of the silicon sensor are comparably small due to the low input impedance of the readout electronics. The ASIC's noise is determined by several design parameters and implementation technology and the pickup noise depends on the detector screening scheme and the power supply circuitry.
  The new 32-channel readout chip PRO/A designed in collaboration with IDE AS Company in Oslo, has an improved SN-performance and eliminates all shortcomings of the previous ASIC. Every channel of the new PRO/A chip contains a charge-sensitive preamplifier with variable gain, an active low-pass filter with 30 ns time constant, a differential amplifier, a pulse discriminator, a mono-flop (which can be excluded for the time-over-threshold mode) and an open-drain output buffer. The differential amplifier allows subtracting the analog contents of two neighboring channels from each other. This removes those signal harmonics which are common to both pads. This method was studied in a test beam and then implemented into the chip design. The inherent noise of the readout chip (one standard deviation of the Gaussian fit to the noise pedestal) is equivalent to the input charge of 600 electrons. The resulting noise performance is a linear function of the input detector's capacitance with a positive slope of 15 electrons per 1 picofarad. The common mode rejection power in the subtraction mode amounts to 20 dB for the frequency range from 100 Hz to 10 MHz.
  The new ASIC contains a calibration pulse circuitry which multiplexes an external charge pulse from a special input to one of the odd and (or) even channels. In every channel there is an input current compensation scheme which draws (sinks) up to 500 nanoamperes of the DC current. The idea was to equalize two potentials between the detector and the chip itself, when one or more pads have their decoupling capacitors shortened. This scheme can be turned on and off. Several so-called "bias" voltages generated by the chip itself, define the IC's operating regime. Their superposition gives a common threshold voltage for 32 pulse discriminators, but external thresholds can overdrive these settings in 8 groups of 4 channels. The chip steering is done via the 72-bit control register. The register content, so-called "sequencer code", has a default "power on" configuration, but it could be exchanged any time during the chip operation.

More than 200 dies were fabricated in a 1.2 um N-well CMOS process by the AMS enterprise and then shipped to the IDE AS Company for the quality check.