The data reduction algorithm contains synchronization of detector pulses, pipelining the raw data, matching the input word to a similar pattern from the database and coding the output information. The synchronization scheme provides a timing gate for the input trigger pulses. Their arrival times could be different from one event to another and this delay may also scatter among channels. This negative effect has a special term "timing walk" and in our case it is as high as 50 ns. Thus one input pattern may contain signals from two different bunch crossings (BC) and the trigger decision will be false anyway. The solution offered relies on the the following statements:

1. Trigger signal is understood as a high-to-low level transition (the leading edge of the pulse). This definition helps also to resolve bad channels, which drive the permanent low level.

2. All signals are registered within some certain time interval, which doesn't exceed one BC. This gate starts from the earliest trigger pulse and closes from the HERA clock frequency. The delay for clock pulses provides a variable gate width. All signals passing through the synchronization module receive the uniform duration and the unique timing phase.

  The full pad detector information is stored in the pipeline which depth allows for keeping 22 HERA bunch crossings. The memory write enable signal, so-called "Pipeline Enable", or simply "PEN", is driven by the central data acquisition system (CDAQ). A matching scheme for tracks is based on a content addressable memory (CAM) for the fast multiple searches. The CAM capacity needed per one motherboard amounts to 1024 32-bit records. These records, so-called "masks", are obtained from the Monte Carlo simulation and from the offline data analysis. The CAM module supports "don't care" values for masks. This allows for seeking for the whole mask entirely and also for smaller mask patterns. Signals from any three, two and even one plane could be used to make the trigger decision. Therefore more than one signature will be programmed for every possible track to provide higher trigger efficiency.
  The data output from the front-end is performed in two stages. When the first level trigger is transparent for subdetectors, the "PEN" signal is active and the BST is sending out the topology data of validated tracks, i.e. their polar angles "theta" and "phi" and hit multiplicities for pads. It allows the master card making the fast trigger decision. Alone or in a combination with any other subdetectors, the BST "L1" decision could be accepted by the H1 central DAQ. Afterwards the "PEN" goes low, the readout phase starts and the pipeline content is multiplexed to the output. Some other subroutines: the H1 radiation monitor, the hit multiplicity check and the recognition algorithm for upstream going tracks were added to the main trigger program. The firmware was prepared in the "Quartus" development system with the entry code written in the VHDL.