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\begin{document}

\begin{center}
{\Large\bf Summary of Constraints and Performance}
\end{center}


\section{Introduction}

From our studies at Liverpool, a number
of points have become clear and  certain arguments crystallised,
so that we are now in a position to 
focus on a relatively small number of solutions
and examine their respective merits.

The major constraints and performance related issues are discussed
and conclusions drawn.



\section{Mechanical Constraints}

There may be mechanical constraints on building a very small
detector.  We need to think how the silicon will be mounted,
how the cables will be taken out, and how the detector will be cooled.  
Some degree of overlap between
plaquettes is needed: firstly, to allow for dead regions at the
edge of the plaquettes due to guard rings and the silicon manufacture;
and secondly, to provide overlap for alignment.
We assume a dead region of 1mm and require an overlap of 10\%.

Three designs amongst many present 
themselves (Figure~\ref{pretty}.)
\begin{itemize}
\item
An angled design:
Each side of a regular polygon is tilted through an angle and
the width of the plaquette extended.
\item
A castellated design:
Every other side of a regular polygon is
displaced outwards by $\delta R$ which allows the width of the
plaquettes to be extended.
\item
An overlapping design:
Each side of a regular polygon is extended, but in one direction only.
\end{itemize}

Although an angled or overlapping design may make
fanning out the cables easier, it appears from sections~\ref{SEC:SN}
\& \ref{SEC:OCC}
that a castellated 
design may be necessary in order to reduce the
crossing angles.

Another mechanical concern to be addressed, is whether the
very smallest designs pose and yield problems from
the point of view of handling and testing by the manufacturer.
To assess this, it is urgent to agree final dimensions in time to
get any adverse feed-back on this point quickly from potential suppliers.




\section{Crossing Angles}
\label{SEC:SN}
The modularity of the detector and the pitch of the strips must
be matched so that the majority of tracks deposit their charge
over one, two or three strips.
Designs in which a large number $(>20\%)$  of
tracks spread their charge over  greater than three strips
will not work.  A rule of thumb is that the strip pitch should
be no smaller than the projected distance in the silicon
of the largest angled track.
In other words, for a $300\mu$m pitch detector, 
the modularity $N$, and the pitch $p$ are related via
\begin{equation}
p > 300 \Bigl( \tan (\pi/N + \theta ) + y \Bigr)
\end{equation}
where $\theta$ is the angle through which the modules are tilted
and $y=.1/1.6$ for an overlapping design 
implies a sideways shift per plaquette of 1mm.
Reducing the pitch below this number would only
compromise efficiency without much significant gain in resolution.

The table below calculates an approximate 
minimum strip pitch for a given
modularity,  for three geometries.

\begin{center}
\begin{tabular}{|c|c|c|c|}
\hline
Modularity & \multicolumn{3}{c|}{Minimum strip pitch} \\
\cline{2-4}
           & Angled          &  Castellated      & Overlapping \\
           & Tilt $=10^o$    &  Tilt $=0^o$     & $y=.1/1.6$ \\
\hline
8 & $191\mu$m & $124\mu$m & $143\mu$m \\
9 & $173\mu$m & $109\mu$m & $127\mu$m \\
10 & $160\mu$m & $97\mu$m & $115\mu$m \\
11 & $149\mu$m & $88\mu$m & $106\mu$m \\
12 & $140\mu$m & $80\mu$m & $98\mu$m \\
13 & $132\mu$m & $74\mu$m & $92\mu$m \\
14 & $126\mu$m & $68\mu$m & $86\mu$m \\
15 & $121\mu$m & $64\mu$m & $82\mu$m \\
16 & $117\mu$m & $60\mu$m & $78\mu$m \\
\hline
\end{tabular}
\end{center}

This effectively eliminates the
8-fold $50\mu$m pitch solution 
since, as section~\ref{SEC:OCC} will show,
38\% of tracks spread
their charge over 4 or more strips.
We must go to a) greater modularity and/or b) larger strip pitches.






\section{Readout Chip Constraints}

Given that there is a reasonably hard limit of about 128 readout chips,
only a limited number of solutions exist in terms of 
modularity $N$, and strip pitch $p$.  
If
the radius of the detector is assumed to be 1.6cm and
an overlap of 10\% is requested for alignment purposes;
then the minimum strip pitch allowed can be calculated:
\begin{equation}
p > \Bigl( 2 \times 1.6 \times 1.1 \times f  \tan(\pi/N)\Bigr) / 128
\end{equation}
where $f$ is a factor of about 1.1 to ensure $2\pi$ coverage.
For a castellated design with alternate plaquettes offset by
$\delta R$ then $f=1+\delta R/(2\times 1.6)$ while for an angled design
\mbox{$f=\cos(\pi/N) / cos(\pi/N+\theta)$.}

The following table shows the results for an angled design of $10^o$
and a castellated design with $\delta R =2mm$.

\begin{tabular}{|c||c|c|c||c|c|c||c|}
\hline
Modularity & \multicolumn{3}{c||}{ Angled Design} 
& \multicolumn{3}{c||}{Castellated Design} & No.Chips\\
\cline{2-7}
& Circumfer- & Width     & Minimum         & Circumfer- & Width & Minimum & \\
& ence (cm)  & Plaq. (cm)& Pitch $(\mu$m) & ence (cm)  & Plaq. (cm)& Pitch $(\mu$m) & \\
\hline
8 & 12.77 & 1.597 & 125 (62) & 12.39 & 1.549 & 121 (60) & 64 (128) \\
9 & 12.51 & 1.390 & 109 (55) & 12.25 & 1.361 & 106 (53) & 72 (144) \\
10& 12.32 & 1.232 & 96       & 12.15 & 1.215 & 95 & 80       \\
11& 12.17 & 1.107 & 86       & 12.08 & 1.098 & 86 & 88 \\
12& 12.06 & 1.005 & 78       & 12.03 & 1.002 & 78 & 96 \\
13& 11.97 & 0.921 & 72       & 11.98 & 0.922 & 72 & 104 \\
14& 11.90 & 0.850 & 66       & 11.95 & 0.854 & 67 & 112 \\
15& 11.83 & 0.789 & 62       & 11.92 & 0.795 & 62 & 120 \\
16& 11.79 & 0.737 & 58       & 11.90 & 0.744 & 58 & 128 \\
\hline
\multicolumn{8}{r}{Numbers in brackets are for {\bf two} readout chips per plaquette}
\end{tabular}

Whatever solution we choose must conform, more or less, to these limits:
small variations on these numbers can be obtained
by reducing the overlaps
or the tilt.

\section{Rad-Hard Technology Constraint}


We have looked at the increase in voltage which would be
necessary to fully deplete the detectors as they become progressively
more damaged due to radiation.


An integrated 
luminosity of 1fb$^{-1}$ per year was assumed, 
which corresponds to 1MRad per year
which is equivalent
to $1.7\times 10^{13}$ neutrons per cm$^2$ or 
   $3. \times 10^{13}$ protons   per cm$^2$.
The CV parameterisation, as found in the ATLAS TDR~\cite{atlas} was used.
The detector was assumed to run at~$-10$C.
The short term favourable annealing effects were
ignored, while reverse annealing was calculated assuming that the
detectors were allowed to heat to 20C for one week at the end of each year
for maintenance purposes.

Figure~\ref{gian} shows the predicted evolution of the Voltage 
for $300\mu$m thick detectors.  
After 2 years (2fb$^{-1}$) the detectors would need to be run at
100 volts, while 
after 3 years (3fb$^{-1}$) it would be necessary to rise
to 150 volts.

A comparison of this prediction with a parameterisation
from recent test-beam data~\cite{didier} gives similar results.
A further comparison has been made with the curve in the CMS TDR~\cite{cms}
(reproduced in the Layer00 proposal~\cite{loo},) 
which shows very similar behaviour after inversion.
 
If we are only designing for 2fb$^{-1}$, p-in-n technology can be
used.  For luminosities above this value, the voltage must be 
raised above the 100V which constitutes the maximum specification
of the capacitor dielectric.
%One risks damaging this if voltages $\gg$ 100V are used, as large
%charge deposits in the bulk silicon could lead to this voltage
%being briefly applied across the oxide, causing irreparable damage.

We would probably be safe up to 3fb$^{-1}$ (150 volts) as
there is experience with Hamamatsu detectors performing
reliably at this voltage.   Above this value however, we run
the risk of irreversible damage to the capacitors should 
bad beam conditions, for example, lead to 
large local ionisation in the silicon.
The resulting permanent damage to the dielectric leaves the
affected region dead with large currents flowing into
the front-end of the CMOS pre-amplifier (usually also killing
neighbouring channels.)
Up to now, no HEP detectors have needed to operate well above the 
rating of the capacitors so no relevant experience of the magnitude
of this problem exists.  



With a n-in-n technology, this risk can be avoided by running
the detectors partially depleted below the
voltage rating of the dielectric.
Figures~\ref{cam1}\&\ref{cam2} show an analysis by the Cambridge group
of various n-in-n and p-in-n detectors 
run in a test-beam at CERN~\cite{didier}. 
The efficiency for registering a hit at a 1fC single
strip threshold (which corresponds to three times the noise for 2000 enc,
or four times for 1500 enc),
is plotted 
as a function of voltage, 
after irradiation at a fluence of $3\times10^{14}$ protons/cm$^2$.
Running p-in-n detectors at 100 to 150 volts gives poor performance
($<$50\% efficiency) while n-in-n detectors can be run at 150 volts with
$>$90\% efficiency.
The full depletion voltages for these detectors was about 300V, confirming
earlier studies showing that n-side read-out allows
efficient operation well below the depletion voltage.
If high operating voltages are undesirable, this is a strong argument
for adopting the n-in-n solution.



\subsection{N-in-N Technology}

We do not have time for
a prototyping run for the sensors for Layer~00.
This means we must work with proven
solutions adapted only in terms of external geometry to fit
the needs of Layer~00.


If we require n-in-n technology, 
we are confident that
a design based on
a pitch of $70\mu$m to $90\mu$m pitch will work, 
as these detectors have already been 
extensively prototyped and tested, giving
excellent performance both before and after irradiation
up to 10MRad in test-beam studies.
N-side read-out designs with $50\mu$m pitch have been
prototyped for RD20 and SDC and results after irradiation can be
found in the literature, but little is available on results after
irradiation with fast read-out electronics.

Double metal n-in-n detectors for LHCb with variable pitch 
down to $40\mu$m have been designed at Liverpool
and produced by Hamamatsu.  They work well pre-irradiation
but the study of their post-irradiation properties is only
just starting.  We would conclude that the most reliable and 
systematic results with full read-out of irradiated detectors
are those of ATLAS at $70-90\mu$m pitch~\cite{didier}.

\subsection{P-in-N Technology}

For the p-in-n technology, working prototypes already exist for
a range of strip pitches between $50\mu$m and $100\mu$m.
This follows from the work of RD20, ATLAS and CMS.
In ATLAS, detectors irradiated up to 10MRad have been studied
extensively in beam with fast electronics and found
to work satisfactorily albeit with voltages $>$300V.


\section{The Operating Temperature of Layer~00}


It may be that the limiting design feature is not given from
physics arguments but from mechanical constraints.  For example,
there may not be enough room to embed a cooling system within
the silicon  support structure.  We therefore ask what effect
higher operating temperatures have on the depletion voltage
and reverse current.


\subsection{Depletion Voltage}

Figure~\ref{gianluigivolt} shows the operating voltage as a function
of running time, for temperatures of -10, 0, 10 and 20C.
It is assumed that in addition, the detector is brought to 25C for
one week per year for maintenance.

As regards the voltage required, there is very little difference
between the performance with Layer~00 maintained at -10C, and
Layer~00 operating at the temperature of the rest of SVX (10C).
It is only at room temperature operation (20C) that appreciable
differences in the voltage are observed. 
These observations may mean that a much simplified cooling system
could be designed for Layer~00.


\subsection{Reverse Current}

The reverse current, $I_r$, depends on the trap concentration, $N_t$ and
on the temperature $T$:
\begin{equation}
I_r \propto N_t T^2\exp(-E_g/2kT)
\end{equation}
where $E_g\approx 1.2$eV is the silicon energy band gap.
Figure~\ref{gianluigicurr} shows the strip current 
for a fully depleted, $50\mu$m pitch,
8cm long, $300\mu$m thick detector, as a function
of running time, for temperatures of -10, 0, 5, 7.5, 10 and 20C.
The current increases with increasing trap concentration due to
irradiation, and with increasing temperature.
For detectors with $75\mu$m pitch, these currents should be
increased by 50\%.


\section{Noise Calculation}


We now turn to an evaluation of the total noise to
see the effect of both an intermediate strip and running
the detector at a higher temperature on a $50\mu$m pitch detector.

The total noise, $N$, can be expressed as the sum of two components:
\begin{equation}
N= N_{ir} \oplus N_{cap} 
\end{equation}
where $N_{ir}$ is the noise induced by the reverse current,
and $N_{cap}$ is the noise induced by the detector capacitance.


\subsection{Shot Noise}
\label{shot}
Running the detector at 10C rather than -10C has a small
effect on the depletion voltage due to radiation damage
but a larger effect in the reverse current.  This has implications
for the noise.

A simple model~\cite{trigger,spieler} to relate the current to the 
noise in equivalent electrons is 
through 
\begin{equation}
\sqrt{ {I_r \times \Delta t}\over{q_e}}
\end{equation}
where $q_e$ is the electron charge ($1.6\times 10^{-19}$ C),
and $\Delta t$ is the sampling time, taken here to be 132ns, the time
between beam crossings.
From Fig.~\ref{gianluigicurr}, the reverse current after two years 
would be
$0.2 \mu$A at $-10$C and $0.9 \mu$A at 10C.
Thus
\begin{equation}
N_{ir} = 410 {\rm\ enc.\ at\ -10C\ or\ 860\ enc.\ at\ 10C}
\end{equation}
This number is subject to two caveats.
Firstly, this assumes correlated double sampling where the sampling interval
$>>$ The Rise Time.  This is probably incorrect for the Layer~00
electronics;
a fuller knowledge of the workings of the readout chip is required
to make an accurate calculation.
Secondly, the voltage required for full charge collection may be greater
than the full depletion voltage for irradiated detectors, due to
edge current effects.  These extra currents are processing dependent,
are not well understood, and could contribute up to 40\% more to
$N_{ir}$.   The edge currents, if they occur,  
could however be reduced by running the
detectors under-depleted.  



\subsection{Intermediate Strip}

The addition of an intermediate strip helps to linearise
the distribution of charge on neighbouring strips for
tracks which are close to normal.
For crossing angles less than 0.05 radians (about one quarter of all
tracks) this would improve the resolution from 8 or 9$\mu$m to
$7\mu$m.
As \cite{joes} already implies an average
resolution of $10\mu$m, which is dominated by other effects, the improvement
which the intermediate strip provides is small.

On the other hand, an intermediate strip results in a 
larger noise component.
The noise of the Honeywell SVX3D chip~\cite{honey}
after  2MRad irradiation in
units of electron noise equivalents can be expressed as
$800 + 60 \times$ (Capacitance in pF).  
From \cite{rd20}, the silicon will have a capacitance of 1.2 pF/cm
while including an intermediary strip will add 0.4pF/cm\cite{loo}.
Thus 
\begin{equation}
N_{cap}=1400 {\rm \  enc.\ or\ 1640\ enc.\  with\ a\ Intermediate\ Strip.}
\end{equation}

\subsection {Total Noise}

With the assumptions discussed above,
the total noise for a detector without an intermediate strip, operating
at -10C, is 1460 enc.
With an intermediate strip, this increases to 1690 enc.
Without an intermediate strip, but operating at 10C, it increases to
1640 enc.  With both an intermediate strip and a temperature of 10C, it
is 1850 enc.

These numbers represent an attempt to calculate the total noise.
There may be inaccuracies in our assumptions, particularly with
respect to the performance of the readout chip.  We welcome any
clarifications which will follow our discussions next week and any 
conclusions we have drawn from the above will be appropriately modified.



\section{Occupancy Studies (Summary)}
\label{SEC:OCC}
We come now to the impact the design will have on the physics.
The
myriad of numbers in the previous reports~\cite{ronan3}
are condensed 
and the salient points are reproduced in the table below.
The results are for $t\bar t$ events with one minimum bias event superimposed.
The numbers are similar for $b\bar b$ events;
Percentages are similar for events with five minimum bias events superimposed.

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|}
\hline
Modu- & Pitch & \multicolumn{4}{c|}{Tracks spreading over}
&  Strip  & B-Strip  &  Track  &
 B-Track  \\
\cline{3-6}
  larity         && 2-strips & 3-strips & 4-strips & 5-strips &Sharing&Sharing&Sharing&Sharing\\
\hline
\multicolumn{10}{|c|}{Castellated Design} \\
\hline
8 & $50\mu$m & 21\% & 41\% & 33\% & 5\% & 4.0\% & ? & 12 (10\%) & 3.2 (26\%) \\
8 &$100\mu$m &41\% &57\% & 2\% & 0\% & 6.2\% & ? & 16 (14\%) & 4.1 (34\%) \\
12& $75\mu$m & 48\% & 51\% & 1\% & 0\%  & 4.8\% & 18\% & 13(11\%) & 3.4(28\%)\\
16& $50\mu$m & 42\% & 55\% & 2\% & 0\% &  3.5\% & 13\%&9.8(8.4\%)&2.7(21\%)\\
\hline
\multicolumn{10}{|c|}{Angled Design}\\
\hline
8 & $50\mu$m &22\% & 39\% & 21\% & 19\% & 4.4\% & ? & 13 (11\%) & 3.4 (28\%) \\
8 &$100\mu$m &41\% & 48\% & 12\% & 0\% & 6.4\% & ? & 17 (15\%) & 4.2 (36\%) \\
12& $75\mu$m &40\% & 48\% & 14\% & 0\%  & 5.3\% & 19\% & 14(12\%) & 3.7(31\%)\\
16& $50\mu$m &25\% & 42\% & 32\% & 3\% &  4.1\% & 15\%& 12(10\%)&3.3(27\%)\\
\hline
\end{tabular}

Increasing the modularity and decreasing the pitch gives a small
but nonetheless significant improvement.  Going from 
12-fold $75\mu$m to 16-fold $50\mu$m for the castellated design
improves the doublely hit B-strips from 18\% to 13\%
and improves the mis-measured b tracks from 3.4 to 2.7.  That is
an improvement of 0.7 tracks per event or 25\% less badly measured
b tracks.  

However, It is important to ensure that the relationship
between modularity and pitch, as described in section~\ref{SEC:SN},
is adhered to.  As can be seen in the table above,
the 8-fold $50\mu$m solution, although giving reasonable occupancy
numbers, fails on account of the large number of tracks depositing
their charge over 4 or more strips.


\section{Impact Parameter Resolution}
The most important reason for Layer00 however is in recovering
good impact parameter resolution for low momentum tracks.
To evaluate the effect of different strip pitches for Layer00,
a simulation has been performed.
Tracks were followed outwards from the
interaction point, scattered randomly on passing through
the beam-pipe and the layers of silicon, and measured with
the expected resolution in Layer00, SVX2 and ISL.
Then the process was reversed, and
a full track fit performed including the
(correlated) effects of multiple scattering.
Finally, the results were parameterised according to the formula
$A \oplus B/p_T$.  Note, this is a very {\it poor} parameterisation
for the particular geometry we are considering.  
Therefore, results are also
given for  the average resolution at 1,2,3 and 4 GeV.  
These are
considerably {\it worse} than you would expect from the formula.


The inputs to the simulation are as given in Joe's talk~\cite{joes}:
The radius of Layer00 is taken to be 1.6cm and the radius
of the inner layer of SVX2 is 2.615cm.
The resolution in SVX2 is $12\mu$m and in ISL is $32\mu$m.
The Moli\`ere scattering formula~\cite{pdg}, 
$\theta_0 = .0136\sqrt X_0(1+.038\log X_0)$,
is used but the $\log$ term
is neglected.

\begin{center}
\begin{tabular}{|c|c|c|c|c|c|}
\hline
Pitch & Parameterisation & \multicolumn{4}{c|}{Resolution at} \\
\cline{3-6}
      &                  & 1 GeV & 2 GeV & 3 GeV & 4 GeV \\
\hline
$50\mu$m & $8\oplus 29/P_T$ & $29\mu$m & $20 (37) \mu$m & $17 (45)\mu$m & $15 (51)\mu$m \\
$75\mu$m & $9\oplus 36/P_T$ & $35\mu$m & $25(47)\mu$m & $21(57)\mu$m & $18 (62)\mu$m \\
$100\mu$m & $10\oplus 42/P_T$ & $40\mu$m & $28(52)\mu$m & $23(62)\mu$m & $20(69)\mu$m \\
No L00 & $10\oplus 63/P_T$ & $57\mu$m & $37(74)\mu$m & $30(90)\mu$m & $24(96)\mu$m \\
\hline
\multicolumn{6}{l}{The numbers in brackets are the implied values of B in the 
formula $A\oplus B/p_T$}
\end{tabular}
\end{center}


Reducing the strip pitch clearly affects both the asymptotic term and
the multiple scattering term.
It is felt that 
the asymptotic term improvement is somewhat irrelevant, especially
as we read in the Layer~00 proposal~\cite{loo}
``The intrinsic asymptotic resolution of
9-10$\mu$m will of course not be realized in practice.''
The multiple scattering term is the important parameter and it
improves from $42\mu$m for $100\mu$m pitch to $29\mu$m for $50\mu$m pitch
which is significant.  Just as importantly, for 2GeV tracks it reduces
from $28\mu$m to $20\mu$m.

With the inputs to the simulation detailed above, we
were successful in reproducing the 
numbers in the Layer~00 proposal~\cite{loo}.
These numbers may however be somewhat pessimistic.
There are two inputs which could be better than has been 
assumed:
firstly, why is the $\log$ term in Moli\`ere scattering ignored;
secondly, why is the resolution $12\mu$m for a $60\mu$m pitch
detector?  At LEP a $7\mu$m resolution is obtained for a $50\mu$m pitch,
a number which includes alignment effects.  
In the table below, 
the effect that altering these inputs has on
the impact parameter resolution is examined.


\begin{center}
\begin{tabular}{|c|c|c|c|c|}
\hline
Pitch & Description & \multicolumn{3}{c|}{Resolution at} \\
\cline{3-5}
      &                  & Infinity & 1 GeV & 2 GeV \\
\hline
No L00 & As in Proposal & $10\mu$m & $55\mu$m & $37\mu$m \\
No L00 & Include $\log$ term & $10\mu$m & $50\mu$m & $34\mu$m \\
No L00 & $8.5\mu$m precision for SVXII& $8\mu$m & $50\mu$m & $32\mu$m \\
No L00 & $8.5\mu$m for SVXII \& log term $\log$ & $8\mu$m & $45\mu$m & $29\mu$m \\
$100\mu$m L00 & ``''          & $7\mu$m & $28\mu$m & $21\mu$m \\
$75\mu$m L00 & ``''          & $6\mu$m & $25\mu$m & $19\mu$m \\
$50\mu$m L00 & ``''          & $6\mu$m & $19\mu$m & $15\mu$m \\
\hline
\end{tabular}
\end{center}

From this parameterisation of the scattering and with a more 
realistic detector resolution, there is perhaps a less compelling reason
for going to smaller strip pitches.  Nonetheless, a multiple
scattering term of $18/p_T$ as derived from the last line of this
table, would be truly excellent, approaching the level to which
the alignment was successful in Run1.




\section{Discussion}

These points are now summarised and our conclusions presented.

The facts are (hopefully) objective, but the conclusions are inevitably
subjective and open to debate.  
It is entirely possible to argue the matter in a completely
different manner.

In terms of the physics, both occupancies and impact parameter resolutions,
it is clear that as the pitch reduces, so too do the occupancies and
resolutions.  In order to maintain efficiency however, the modularity
of the detector must be correspondingly increased.


A continuous improvement is seen with smaller
strip pitches and increased modularity; there are no hard cut-offs.
We see a sliding scale of progressive benefits from increasing
the granularity and the improvements, though small, are significant.

Therefore, it seems reasonable to aim for the
smallest strip pitch which is technically feasible and 
which can confidently be built in the time-scales allowed.
The physics gains from the best granularity.
One must now factor in what is technically possible.

We have a hard limit for the modularity at 16-fold
from the cost of the readout chain.  Can we therefore take on
a 16-fold, $50\mu$m pitch detector ?

The crucial issue here would appear to be the radiation dose.
If we are only planning for 2fb$^{-1}$, then 
p-in-n sensors are sufficient.
If however we wish to plan for higher luminosities, or foresee
Layer~00 as providing a clearly defined  upgrade path for Run-III,
then we would recommend n-in-n sensors.
In that case, given the time-scales, $75\mu$ pitch sensors are
known to work and we would propose building a 12-fold 
detector which would provide almost as good physics output.

A further issue, which may be important, is the technical difficulty
of cooling the detector to -10C, given the space at our disposal.
With the assumptions as given in section~\ref{shot}, it would appear
that running the detector at +10C introduces no more noise
than adding an intermediary strip.  
There is some uncertainty at the moment with regard to the edge currents
that could develop with irradiation.  The noise these would induce
could be reduced by running the detectors under-depleted.  This would
therefore constitute an additional argument for a choice of the n-in-n
technology.

\section{Conclusion}
In summary, we see two design options.

\begin{itemize}
\item
A 16-fold, $\approx 50\mu$m pitch detector based on p-in-n technology.
\item
A 12-fold, $\approx 75\mu$m pitch detector based on n-in-n technology.
\end{itemize}


Notwithstanding the above,
we still have a number of issues which need resolving:
castellated versus angled design; how to fan the cables out;
cable capacitances; cooling.  


We hope that this document can provide some of the starting points for
our discussions on Nov.23rd-25th.
We feel it is important to finalise the geometry and detector technology
as soon as possible in view of feedback on timescales we have received 
from silicon  manufacturers and 
of the overall timescale of the Layer~00 project.
We understand that if we were to order p-in-n sensors from Hamamatsu today,
delivery could be expected in mid-April, while for n-in-n sensors, 
delivery would be in mid-June.




\begin{thebibliography}{99}
\bibitem{atlas} The ATLAS TDR.

\bibitem{didier} P.Allport et al.,
`ATLAS Irradiation Studies of n-in-n and p-in-n Silicon
Microstrip Detectors', {\it submitted to NIM}

\bibitem{cms} The CMS TDR.

\bibitem{loo} P.Azzi-Bacchetta et al.,
`Proposal for a Very Low Mass, Very Small Radius Silicon Layer
in the CDFII Upgrade.'


\bibitem{trigger}C.Leroy et al., `Study of Charge Collection and Noise in Non-Irradiated and Irradiated Silicon Detectors',
{\it Nucl. Inst. and Meth.}{\bf A388} (1997) 289.

\bibitem{spieler}H.\ Spieler `Electronic Noise and Pulse Shaping in Radiation Detector
Systems', {\it 3rd Int. (Hiroshima) Symposium on the Development and
Application of Semiconductor Tracking Detectors, Melbourne, Dec. 9-12, 1997}

\bibitem{joes} J.Incandela \& R.Snider, `Effect of material on SVXII
impact parameter resolution', Transparencies to the Upgrade Meeting Jan 9th,
1998.  Available at 
{\tt http://www-cdf.fnal.gov/internal/upgrades/xvsii/Mechanical/Mass/mass.html}

\bibitem{honey}See {\tt http://cdfsg6.lbl.gov/~dfish/cdf/chips/svx3d/hd2\_noise.gif}

\bibitem{rd20}A.Holmes-Siedle, `Radiation tolerance of single-sided silicon microstrips.', RD20 Coll., {\it Nucl. Inst. and Meth.}{\bf A339} (1994) 511.

\bibitem{ronan3}  `The third study' on occupancies at {\tt http://hep.ph.liv.ac.uk:80/cdf}


\bibitem{pdg}  Particle Data Group Book.


\end{thebibliography}

\begin{figure}
\begin{center}
\mbox{\epsfig{figure=picy.ps,width=15cm,
bbllx=25pt,bblly=140pt,bburx=550pt,bbury=690pt}}
\caption[]{Three possible designs.
From top to bottom:
An angled design; a castellated design; an overlapping design.
\label{pretty}}
\end{center}
\end{figure}

\begin{figure}
\begin{center}
\mbox{\epsfig{figure=vfd.ps,width=15cm,
bbllx=25pt,bblly=140pt,bburx=550pt,bbury=690pt}}
\caption[]{
Full Depletion Voltage (vertical axis) as a function of
time in hours (horizontal axis.)
\label{gian}}
\end{center}
\end{figure}

\begin{figure}
\begin{center}
\mbox{\epsfig{figure=figure5.ps,width=15cm,
bbllx=25pt,bblly=140pt,bburx=550pt,bbury=690pt}}
\caption[]{
Measured efficiency as a function of bias voltage for three irradiated
p-in-n detectors.
This figure for {\bf p-in-n} detectors is taken directly from \cite{didier}.
\label{cam1}}
\end{center}
\end{figure}

\begin{figure}
\begin{center}
\mbox{\epsfig{figure=figure6.ps,width=15cm,
bbllx=25pt,bblly=140pt,bburx=550pt,bbury=690pt}}
\caption[]{
Measured efficiency as a function of bias voltage for three irradiated
n-in-n detectors.
This figure for {\bf n-in-n} detectors is taken directly from \cite{didier}.
\label{cam2}}
\end{center}
\end{figure}

\begin{figure}
\begin{center}
\mbox{\epsfig{figure=neff1.ps,width=15cm,
bbllx=25pt,bblly=140pt,bburx=550pt,bbury=690pt}}
\caption[]{
The depletion voltage as a function of time for detectors at temperatures,
reading from top to bottom, of 20C, 10C,  0C, -10C.
\label{gianluigivolt}}
\end{center}
\end{figure}

\begin{figure}
\begin{center}
\mbox{\epsfig{figure=curr2.ps,width=15cm,
bbllx=25pt,bblly=140pt,bburx=550pt,bbury=690pt}}
\caption[]{
The strip current as a function of time for detectors at temperatures,
reading from top to bottom, of 20C, 10C, 7.5C, 5C, 0C, -10C.
\label{gianluigicurr}}
\end{center}
\end{figure}


\end{document}




