Liverpool BeO Forward Hybrid with ABCD
The Efficiency Problem.
Tests of ABCDs have revealed that some channels on individual chips
exhibit low efficiency (they never attain 100% efficiency). Testing
and simulation has revealed that some channels (but not all) which exhibit
low efficiency can be explained by:
-
Defects in the 12 cell pipeline which can result in either every 12th data
being lost for a particular channel, i.e. this will produce 91.6% efficiency,
for 2 or 3 bad cells this will produce efficiencies of 83.3% and 75% respectively.
But if the same bin is always readout from the pipeline, which has no defects,
some channels are still found to have low efficiency, which do not correspond
to the efficiencies stated above. By increasing VDD from the nominal setting
of 4.0V to 4.5V, this appeared to 'fix' the bad channels, they now produce
100% efficiency.
Upon closer invstigation it has become apparent that the ABCD is sensitive
to the mark-space ratio of the 40MHz clock that is supplied. Tests here
in Liverpool have revealed that if the clock is high for less than 11ns
(the clock is monitored on the Melbourne support card at the output of
the LVDS receiver (Reference U1), where it is converted to a CMOS single
ended signal) then some channels will still exhibit low efficiency. Ideally
the mark-space ratio of the clock should be 1:1 (on/off for 12.5ns) for
all channels to achieve 100% efficiency. If the clock is not set correctly
then those channels with low efficiency have their missing hits actually
falling in the previous time bin. This can be seen quite clearly in the
results shown below in the 3D plots of 17 channels on an ABCD showing efficiency
as a function of the mark-space ratio of the clock. The ABCDs tested
here where found to perform correctly if the clock is high within the range
of 11ns to 16ns, less than 11ns can result in inefficient channels, greater
than 16ns then they actually stopped working.
All tests where done with VDD = 4.0V and VCC = 3.50V.
The idea for checking the mark-space ratio was prompted by Peter Phillips
at RAL who has experienced a similar problem and found one cure was to
invert the 40MHz clock that he was providing.
If the clock is derived from a crystal oscillator module (which tend
to produce a duty cycle of 40% to 60%, on for 10ns to 15ns), then
there could be a problem with the mark-space ratio of the clock. If the
duty cycle is at the low end i.e. 40%, this could be borderline for some
ABCDs and possibly result in low efficiencies in some channels. A simple
solution would then be to invert the clock so that the duty cycle is then
60% (which corresponds to being on for 15ns).
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Last modified: 09/10/98